[llvm] [CodeGen] Do not retype an already typed vreg in constrainRegAttrs (PR #217410)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Arseniy Obolenskiy (aobolensk)

<details>
<summary>Changes</summary>

With extended LLTs s32 and i32 compare equal, so the unconditional setType could silently retype a register behind the CSE map

This fixes the failing test (llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir) introduced in https://github.com/llvm/llvm-project/pull/207419

---
Full diff: https://github.com/llvm/llvm-project/pull/217410.diff


3 Files Affected:

- (modified) llvm/lib/CodeGen/MachineRegisterInfo.cpp (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir (+4-5) 
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll (+2-2) 


``````````diff
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index dbba413548018..98deb84176c02 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -111,7 +111,7 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg,
     } else if (RegCB != ConstrainingRegCB)
       return false;
   }
-  if (ConstrainingRegTy.isValid())
+  if (ConstrainingRegTy.isValid() && !RegTy.isValid())
     setType(Reg, ConstrainingRegTy);
   return true;
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
index 1c42ae83694d1..329149ed6907f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
@@ -1,5 +1,4 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# UNSUPPORTED: true
 # RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s
 
 ---
@@ -158,8 +157,8 @@ body:             |
     ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr1
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: $sgpr0 = COPY [[C]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: $sgpr0 = COPY [[C]](i32)
     ; CHECK-NEXT: $sgpr1 = COPY [[COPY]](s32)
     ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
     %0:_(s32) = COPY $sgpr0
@@ -286,9 +285,9 @@ body:             |
     ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1
     ; CHECK-NEXT: $sgpr0 = COPY [[COPY]](s32)
-    ; CHECK-NEXT: $sgpr1 = COPY [[C]](s32)
+    ; CHECK-NEXT: $sgpr1 = COPY [[C]](i32)
     ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
index b9afd0dbdb7d7..c250d492f04ac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
@@ -120,7 +120,7 @@ define amdgpu_kernel void @test_uniform_indirect_call_from_kernel(ptr %fptr) {
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr16
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr15
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14
@@ -149,7 +149,7 @@ define amdgpu_kernel void @test_uniform_indirect_call_from_kernel(ptr %fptr) {
   ; CHECK-NEXT:   $sgpr13 = COPY [[COPY12]](s32)
   ; CHECK-NEXT:   $sgpr14 = COPY [[COPY13]](s32)
   ; CHECK-NEXT:   $sgpr15 = COPY [[DEF]](s32)
-  ; CHECK-NEXT:   $vgpr31 = COPY [[COPY]](i32)
+  ; CHECK-NEXT:   $vgpr31 = COPY [[COPY]](s32)
   ; CHECK-NEXT:   $sgpr30_sgpr31 = noconvergent G_SI_CALL [[LOAD]](p0), 0, csr_amdgpu_gfx90ainsts, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $scc
   ; CHECK-NEXT:   S_ENDPGM 0

``````````

</details>


https://github.com/llvm/llvm-project/pull/217410