[llvm] [AArch64] Fold four and eight way partial reductions with [SU]ADDLP (PR #214636)

[Adam Scott via llvm-commits]

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@@ -1551,6 +1551,15 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setPartialReduceMLAAction(MLAOps, MVT::v8i16, MVT::v16i8, Custom);
       setPartialReduceMLAAction(MLAOps, MVT::v4i32, MVT::v8i16, Custom);
       setPartialReduceMLAAction(MLAOps, MVT::v2i64, MVT::v4i32, Custom);
+
+      // Wider folds are a ladder of the two-way step above. +dotprod has no
+      // i16 form so that shape registers unconditionally.
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as4230 wrote:

Yes I have been thinking about this but ran into some headaches with the mul. The products need widening before the reduce and a 64 bit operand has no half to feed the widening multiply at all. Also probably need isPartialReduceMLALegalOrCustom to loop into narrower steps, otherwise DAGCombiner won't fold the extends in and the expansion never sees the narrow type.

https://github.com/llvm/llvm-project/pull/214636