[llvm] [AArch64] Fold four and eight way partial reductions with [SU]ADDLP (PR #214636)

[Adam Scott via llvm-commits]

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@@ -6079,12 +6079,21 @@ defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd
 defm XTN    : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
 
 // Patterns for plain partial add reductions, which lower to [SU]ADALP.
+// A zero accumulator has nothing to add to, so it lowers to [SU]ADDLP.
 multiclass SelectVectorPartialReduceAdd<ValueType DstVT, ValueType SrcVT, dag immOneV> {
   def : Pat<(DstVT (partial_reduce_smla DstVT:$Acc, SrcVT:$Input, (SrcVT immOneV))),
             (!cast<Instruction>("SADALP" # SrcVT # "_" # DstVT) $Acc, $Input)>;
 
   def : Pat<(DstVT (partial_reduce_umla DstVT:$Acc, SrcVT:$Input, (SrcVT immOneV))),
             (!cast<Instruction>("UADALP" # SrcVT # "_" # DstVT) $Acc, $Input)>;
+
+  def : Pat<(DstVT (partial_reduce_smla (DstVT immAllZerosV), SrcVT:$Input,
+                                        (SrcVT immOneV))),
+            (!cast<Instruction>("SADDLP" # SrcVT # "_" # DstVT) $Input)>;
+
+  def : Pat<(DstVT (partial_reduce_umla (DstVT immAllZerosV), SrcVT:$Input,
+                                        (SrcVT immOneV))),
+            (!cast<Instruction>("UADDLP" # SrcVT # "_" # DstVT) $Input)>;
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as4230 wrote:

Sure, but only this PR creates that shape so more like a followup after this lands.

https://github.com/llvm/llvm-project/pull/214636