[llvm] [RISCV] Fold vmand of mask comparisons into a masked comparison (PR #216264)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> > > > Only LMUL <= 1 is folded: for larger LMUL the masked comparison's dest
> > > > is earlyclobbered into vrnov0 and cannot share v0 with the mask, which
> > > > would introduce extra vmv1r.v moves and regress.
> > > 
> > > 
> > > Is that earlyclobber a real restriction required by the ISA?
> > 
> > 
> > Yes I think so:
> > https://github.com/llvm/llvm-project/blob/3cc0457eb8f91ec655fbc0910a4852fbb3c0310f/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td#L2602-L2629
> 
> The ISA should be able to support a v0 destination on a masked compare. We can't have the other sources overlap v0 when lmul>1. But that's the general can't read two registers with the same EEW rule which we don't enforce today on any instruction.

Yes, that's correct. And if there is no `earlyclobber`, we may generate illegal  instructions like `vmseq.vv v9, v8, v10 # LMUL=2` where `v9` overlaps `v8_v9` (not only v0 actually). Fractional LMULs doesn't have such constraints because there is only one register.

https://github.com/llvm/llvm-project/pull/216264