[llvm] [AMDGPU] Fix BFMPatterns mutliclass operand type for i64 (PR #216690)

[Madhur Kumar via llvm-commits]

https://github.com/MadhurKumar004 updated https://github.com/llvm/llvm-project/pull/216690

>From cb569e61a451bc52da0d14e028b300487bd0e2f7 Mon Sep 17 00:00:00 2001
From: Madhur Kumar <madhurkumar004 at gmail.com>
Date: Mon, 17 Aug 2026 15:29:20 +0530
Subject: [PATCH 1/2] Pre-commit test

---
 llvm/test/CodeGen/AMDGPU/bfm.ll | 41 +++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/bfm.ll b/llvm/test/CodeGen/AMDGPU/bfm.ll
index 1db9f9344f8ca..661de8cc4ce21 100644
--- a/llvm/test/CodeGen/AMDGPU/bfm.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfm.ll
@@ -89,6 +89,47 @@ define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
   ret void
 }
 
+define amdgpu_ps i64 @s_bfm64_pattern(i64 inreg %x, i64 inreg %y) {
+; SI-LABEL: s_bfm64_pattern:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_lshl_b64 s[0:1], 1, s0
+; SI-NEXT:    s_add_u32 s0, s0, -1
+; SI-NEXT:    s_addc_u32 s1, s1, -1
+; SI-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
+; SI-NEXT:    ; return to shader part epilog
+;
+; VI-LABEL: s_bfm64_pattern:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_lshl_b64 s[0:1], 1, s0
+; VI-NEXT:    s_add_u32 s0, s0, -1
+; VI-NEXT:    s_addc_u32 s1, s1, -1
+; VI-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
+; VI-NEXT:    ; return to shader part epilog
+  %a = shl i64 1, %x
+  %b = sub i64 %a, 1
+  %c = shl i64 %b, %y
+  ret i64 %c
+}
+
+define amdgpu_ps i64 @s_bfm64_pattern_simple(i64 inreg %x) {
+; SI-LABEL: s_bfm64_pattern_simple:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_lshl_b64 s[0:1], 1, s0
+; SI-NEXT:    s_add_u32 s0, s0, -1
+; SI-NEXT:    s_addc_u32 s1, s1, -1
+; SI-NEXT:    ; return to shader part epilog
+;
+; VI-LABEL: s_bfm64_pattern_simple:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_lshl_b64 s[0:1], 1, s0
+; VI-NEXT:    s_add_u32 s0, s0, -1
+; VI-NEXT:    s_addc_u32 s1, s1, -1
+; VI-NEXT:    ; return to shader part epilog
+  %a = shl i64 1, %x
+  %b = sub i64 %a, 1
+  ret i64 %b
+}
+
 define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
 ; SI-LABEL: v_bfm_pattern_simple:
 ; SI:       ; %bb.0:

>From 4f064f98f795d4e0f037729c117b9c9a5724e8b1 Mon Sep 17 00:00:00 2001
From: Madhur Kumar <madhurkumar004 at gmail.com>
Date: Mon, 17 Aug 2026 16:43:53 +0530
Subject: [PATCH 2/2] [AMDGPU] Fix BFMPatterns mutliclass operand type for i64

---
 llvm/lib/Target/AMDGPU/SIInstructions.td |  6 +++---
 llvm/test/CodeGen/AMDGPU/bfm.ll          | 18 ++++--------------
 2 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 36cacfd47f62c..5fce07e2ac262 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4385,18 +4385,18 @@ def : GCNPat<
 
 multiclass BFMPatterns <ValueType vt, PatFrag SHL, PatFrag ADD, InstSI BFM> {
   def : GCNPat <
-    (vt (SHL (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
+    (vt (SHL (vt (add (vt (shl 1, i32:$a)), -1)), i32:$b)),
     (BFM $a, $b)
   >;
 
   def : GCNPat <
-    (vt (ADD (vt (shl 1, vt:$a)), -1)),
+    (vt (ADD (vt (shl 1, i32:$a)), -1)),
     (BFM $a, (i32 0))
   >;
 }
 
 defm : BFMPatterns <i32, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B32>;
-// FIXME: defm : BFMPatterns <i64, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B64>;
+defm : BFMPatterns <i64, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B64>;
 defm : BFMPatterns <i32, DivergentBinFrag<shl>, DivergentBinFrag<add>, V_BFM_B32_e64>;
 
 // Bitfield extract patterns
diff --git a/llvm/test/CodeGen/AMDGPU/bfm.ll b/llvm/test/CodeGen/AMDGPU/bfm.ll
index 661de8cc4ce21..34c0ce17deb61 100644
--- a/llvm/test/CodeGen/AMDGPU/bfm.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfm.ll
@@ -92,18 +92,12 @@ define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
 define amdgpu_ps i64 @s_bfm64_pattern(i64 inreg %x, i64 inreg %y) {
 ; SI-LABEL: s_bfm64_pattern:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_lshl_b64 s[0:1], 1, s0
-; SI-NEXT:    s_add_u32 s0, s0, -1
-; SI-NEXT:    s_addc_u32 s1, s1, -1
-; SI-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
+; SI-NEXT:    s_bfm_b64 s[0:1], s0, s2
 ; SI-NEXT:    ; return to shader part epilog
 ;
 ; VI-LABEL: s_bfm64_pattern:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_lshl_b64 s[0:1], 1, s0
-; VI-NEXT:    s_add_u32 s0, s0, -1
-; VI-NEXT:    s_addc_u32 s1, s1, -1
-; VI-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
+; VI-NEXT:    s_bfm_b64 s[0:1], s0, s2
 ; VI-NEXT:    ; return to shader part epilog
   %a = shl i64 1, %x
   %b = sub i64 %a, 1
@@ -114,16 +108,12 @@ define amdgpu_ps i64 @s_bfm64_pattern(i64 inreg %x, i64 inreg %y) {
 define amdgpu_ps i64 @s_bfm64_pattern_simple(i64 inreg %x) {
 ; SI-LABEL: s_bfm64_pattern_simple:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_lshl_b64 s[0:1], 1, s0
-; SI-NEXT:    s_add_u32 s0, s0, -1
-; SI-NEXT:    s_addc_u32 s1, s1, -1
+; SI-NEXT:    s_bfm_b64 s[0:1], s0, 0
 ; SI-NEXT:    ; return to shader part epilog
 ;
 ; VI-LABEL: s_bfm64_pattern_simple:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_lshl_b64 s[0:1], 1, s0
-; VI-NEXT:    s_add_u32 s0, s0, -1
-; VI-NEXT:    s_addc_u32 s1, s1, -1
+; VI-NEXT:    s_bfm_b64 s[0:1], s0, 0
 ; VI-NEXT:    ; return to shader part epilog
   %a = shl i64 1, %x
   %b = sub i64 %a, 1