[llvm] [AMDGPU] Fix BFMPatterns mutliclass operand type for i64 (PR #216690)

[Matt Arsenault via llvm-commits]

================
@@ -89,6 +89,75 @@ define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
   ret void
 }
 
+define amdgpu_kernel void @s_bfm64_pattern(ptr addrspace(1) %out, i64 %x, i64 %y) #0 {
+; SI-LABEL: s_bfm64_pattern:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-NEXT:    s_load_dword s3, s[4:5], 0xd
+; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s6, -1
+; SI-NEXT:    s_mov_b32 s4, s0
+; SI-NEXT:    s_mov_b32 s5, s1
+; SI-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-NEXT:    s_bfm_b64 s[0:1], s2, s3
+; SI-NEXT:    v_mov_b32_e32 v0, s0
+; SI-NEXT:    v_mov_b32_e32 v1, s1
+; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT:    s_endpgm
+;
+; VI-LABEL: s_bfm64_pattern:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    s_load_dword s3, s[4:5], 0x34
+; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    s_bfm_b64 s[0:1], s2, s3
+; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; VI-NEXT:    s_endpgm
+  %a = shl i64 1, %x
+  %b = sub i64 %a, 1
+  %c = shl i64 %b, %y
+  store i64 %c, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_kernel void @s_bfm64_pattern_simple(ptr addrspace(1) %out, i64 %x) #0 {
----------------
arsenm wrote:

can you move to amdgpu_ps and return the SGPR return value by using an integer return type, kernels with loads and stores are much more verbose 

https://github.com/llvm/llvm-project/pull/216690