[llvm] [BOLT][AArch64] Add support for LDR relaxation on LDRSl/LDRDl/LDRQl (PR #196983)

[Shanzhi Chen via llvm-commits]

chenshanzhi wrote:

> For generating `ADRP+ADD+LDR` relaxation sequence, in majority cases the linker will leave one NOP instruction as a result of relaxation, and plus the LDR instruction itself BOLT would then have a two instruction budget if we don't want to increase code size or if this is a non-simple function for which we can't go over the budget. It is a tradeoff between setting a bigger alignment for constant data island (16 bytes vs. the old default 8 bytes) and generating longer relaxation sequence.
> 
> There is a TODO comment in the code:
> 
> ```
>         // TODO: If possible, use the actual alignment of the target label
>         // instead of conservatively assuming 1-byte alignment when relaxing a
>         // LoadLiteral instruction.
> ```
> 
> With 1 byte alignment assumption, we will then always produce the three instruction sequence. Wondering if it would be simpler (and better) if we just set 16-byte alignment for constant data islands and always generate `ADRP+LDR` sequence?
> 
> Thanks.

The major reason is that that I found setting 16-byte alignment for constant data does not work for test cases like the newly-added test cases in `ldr-relaxation.s` that are guarded by `RELAX_MISALIGNED_LDR` and `RELAX_MISALIGNED_LDR_FP`. Although these two test cases are manually constructed, I think similar cases are still possible in real-world scenarios.

> Based on commit 16016d95a180a4f25fe0bc466929a5a1c6ddb844, changing `DefaultAlignment` to 16 will make the test case guarded by `RELAX_CONSTANT_ISLANDS` no longer report `BOLT-ERROR: JITLink failed: PAGEOFF12 target is not aligned`. The reason is that `LongJumpPass::tentativeLayoutRelocMode` will make `ci_data` 16-byte aligned again after `remove-nops` or `eliminate-unreachable` removes the nops before `ci_data`. But changing `DefaultAlignment` to 16 cannot fix the same `BOLT-ERROR` reported by the other 2 test cases guarded by `RELAX_MISALIGNED_LDR` and `RELAX_MISALIGNED_LDR_FP`, whereas using `adrp+add+ldr` will fix all the three test cases.

https://github.com/llvm/llvm-project/pull/196983