[llvm] [BOLT][AArch64] Add support for LDR relaxation on LDRSl/LDRDl/LDRQl (PR #196983)

[Rafael Auler via llvm-commits]

rafaelauler wrote:

> For generating `ADRP+ADD+LDR` relaxation sequence, in majority cases the linker will leave one NOP instruction as a result of relaxation, and plus the LDR instruction itself BOLT would then have a two instruction budget if we don't want to increase code size or if this is a non-simple function for which we can't go over the budget. It is a tradeoff between setting a bigger alignment for constant data island (16 bytes vs. the old default 8 bytes) and generating longer relaxation sequence.
> 
> There is a TODO comment in the code:
> 
> ```
>         // TODO: If possible, use the actual alignment of the target label
>         // instead of conservatively assuming 1-byte alignment when relaxing a
>         // LoadLiteral instruction.
> ```
> 
> With 1 byte alignment assumption, we will then always produce the three instruction sequence. Wondering if it would be simpler (and better) if we just set 16-byte alignment for constant data islands and always generate `ADRP+LDR` sequence?
> 
> Thanks.

Oh that's a good point.

https://github.com/llvm/llvm-project/pull/196983