[llvm] [RISCV][GlobalISel] Legalize and select G_PREFETCH (PR #215466)

[Craig Topper via llvm-commits]

================
@@ -1444,11 +1445,56 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     return selectExtractSubvector(MI);
   case TargetOpcode::G_INSERT_SUBVECTOR:
     return selectInsertSubVector(MI);
+  case TargetOpcode::G_PREFETCH:
+    return selectPrefetch(MI);
   default:
     return false;
   }
 }
 
+bool RISCVInstructionSelector::selectPrefetch(MachineInstr &MI) const {
----------------
topperc wrote:

I don't think GIM_CheckConstantInt can handle inline immediate. I think we need GIM_CheckLiteralInt.

I think this will fix the declaration of G_PREFETCH so it will use GIM_CheckLiteralInt

```
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index da65487ce9c6..59325414f802 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -74,9 +74,11 @@ enum OperandType {
 
   OPERAND_FIRST_GENERIC_IMM = 12,
   OPERAND_GENERIC_IMM_0 = 12,
-  OPERAND_LAST_GENERIC_IMM = 12,
+  OPERAND_GENERIC_IMM_1 = 13,
+  OPERAND_GENERIC_IMM_2 = 14,
+  OPERAND_LAST_GENERIC_IMM = 14,
 
-  OPERAND_FIRST_TARGET = 13,
+  OPERAND_FIRST_TARGET = 15,
 };
 
 } // namespace MCOI
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 2153401e5de1..55572f230b96 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1506,7 +1506,7 @@ def G_FENCE : GenericInstruction {
 // Generic opcode equivalent to the llvm.prefetch intrinsic.
 def G_PREFETCH : GenericInstruction {
   let OutOperandList = (outs);
-  let InOperandList = (ins ptype0:$address, untyped_imm_0:$rw, untyped_imm_0:$locality, untyped_imm_0:$cachetype);
+  let InOperandList = (ins ptype0:$address, untyped_imm_0:$rw, untyped_imm_1:$locality, untyped_imm_2:$cachetype);
   let hasSideEffects = true;
   let mayLoad = true;
   let mayStore = true;
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 7d1e7a28b7b6..3acb2531a546 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -1243,8 +1243,10 @@ let IsPointer = true in {
 
 // untyped_imm is for operands where isImm() will be true. It currently has no
 // special behaviour and is only used for clarity.
-def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> {
-  let IsImmediate = true;
+let IsImmediate = true in {
+  def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0">;
+  def untyped_imm_1 : TypedOperand<"OPERAND_GENERIC_IMM_1">;
+  def untyped_imm_2 : TypedOperand<"OPERAND_GENERIC_IMM_2">;
 }
 
 /// zero_reg definition - Special node to stand for the zero register.
```

https://github.com/llvm/llvm-project/pull/215466