[llvm] [RISCV][GlobalISel] Legalize and select G_PREFETCH (PR #215466)

[Kane Wang via llvm-commits]

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@@ -1444,11 +1445,56 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     return selectExtractSubvector(MI);
   case TargetOpcode::G_INSERT_SUBVECTOR:
     return selectInsertSubVector(MI);
+  case TargetOpcode::G_PREFETCH:
+    return selectPrefetch(MI);
   default:
     return false;
   }
 }
 
+bool RISCVInstructionSelector::selectPrefetch(MachineInstr &MI) const {
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ReVe1uv wrote:

I tried the tablegen route — added `GIComplexOperandMatcher+GIComplexPatternEquiv` for `AddrRegImmLsb00000` and the patterns do import (rules for PREFETCH_R/W/I appear in RISCVGenGlobalISel.inc for both RV32/RV64, and timm operands import fine). But selection fails: the importer emit GIM_CheckType for the (i32 0)/(i32 1) cache-type/rw operands in the patterns, while IRTranslator represents G_PREFETCH's rw/locality/cache-type as inline immediates (MachineIRBuilder::buildPrefetch uses addImm). GIM_CheckType rejects non-register operands, so the rule never matches. GIM_CheckConstantInt would handle the inline imm, but the type check precedes it.

So it's not tablegenable today without either an IRTranslator change (materialize the immediates as G_CONSTANT) or an importer change (don't type-check constant Pat operands against imm MIR operands).

https://github.com/llvm/llvm-project/pull/215466