[llvm] [1/7][PISA] Add PISA target registration and backend stub (PR #214094)

[Renato Golin via llvm-commits]

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@@ -0,0 +1,39 @@
+//===-- PISARegisterInfo.td - PISA Register defs ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+let Namespace = "PISA" in {
+
+  class PISARegisterClass<list<ValueType> regTypes, int alignment, dag regList>
+      : RegisterClass<"PISA", regTypes, alignment, regList> {}
+
+  // .reg style registers.
+  class GeneralRegisterClass<list<ValueType> regTypes, int alignment,
+                             dag regList>
+      : PISARegisterClass<regTypes, alignment, regList> {}
+
+  // .pred style registers.
+  class PredRegisterClass<list<ValueType> regTypes, int alignment, dag regList>
+      : PISARegisterClass<regTypes, alignment, regList> {}
+
+  def DummyReg : Register<"%null">;
+
+  foreach Index = 0-63 in {
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rengolin wrote:

One thing we did in the Arm back-end was to add comments before each section (GPRs, VRs, Insts, schedules) to the chapter in the manual that refered to them. For pISA, the docs are in a webpage, so perhaps links to them?

This helps understand some magic numbers and class definitions better during code review, even by people who don't know pISA.

https://github.com/llvm/llvm-project/pull/214094