[llvm] [1/7][PISA] Add PISA target registration and backend stub (PR #214094)
Michal Paszkowski via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 13:55:25 PDT 2026
https://github.com/michalpaszkowski updated https://github.com/llvm/llvm-project/pull/214094
>From fc2f4176644c42d3c04d1bc3347e629ea7f1efbc Mon Sep 17 00:00:00 2001
From: Michal Paszkowski <michal.paszkowski at intel.com>
Date: Tue, 28 Jul 2026 14:19:22 -0700
Subject: [PATCH 1/2] Add PISA target registration and backend stub
Register the Intel GPU portable ISA (PISA) target. Add the pisa Triple
arch, data layout, and a minimal MC/TargetMachine skeleton.
---
llvm/CMakeLists.txt | 1 +
llvm/include/llvm/TargetParser/Triple.h | 4 +
llvm/lib/Target/PISA/CMakeLists.txt | 36 ++++++++
.../Target/PISA/MCTargetDesc/CMakeLists.txt | 16 ++++
.../PISA/MCTargetDesc/PISAInstPrinter.cpp | 35 ++++++++
.../PISA/MCTargetDesc/PISAInstPrinter.h | 34 ++++++++
.../PISA/MCTargetDesc/PISAMCAsmInfo.cpp | 41 +++++++++
.../Target/PISA/MCTargetDesc/PISAMCAsmInfo.h | 25 ++++++
.../PISA/MCTargetDesc/PISAMCTargetDesc.cpp | 64 ++++++++++++++
.../PISA/MCTargetDesc/PISAMCTargetDesc.h | 36 ++++++++
llvm/lib/Target/PISA/PISA.h | 19 +++++
llvm/lib/Target/PISA/PISA.td | 35 ++++++++
llvm/lib/Target/PISA/PISAFeatures.td | 11 +++
llvm/lib/Target/PISA/PISAFrameLowering.h | 31 +++++++
llvm/lib/Target/PISA/PISAInstrInfo.cpp | 19 +++++
llvm/lib/Target/PISA/PISAInstrInfo.h | 31 +++++++
llvm/lib/Target/PISA/PISAInstrInfo.td | 20 +++++
llvm/lib/Target/PISA/PISARegisterInfo.cpp | 29 +++++++
llvm/lib/Target/PISA/PISARegisterInfo.h | 36 ++++++++
llvm/lib/Target/PISA/PISARegisterInfo.td | 39 +++++++++
llvm/lib/Target/PISA/PISASubtarget.cpp | 30 +++++++
llvm/lib/Target/PISA/PISASubtarget.h | 61 +++++++++++++
llvm/lib/Target/PISA/PISATargetMachine.cpp | 85 +++++++++++++++++++
llvm/lib/Target/PISA/PISATargetMachine.h | 46 ++++++++++
.../lib/Target/PISA/TargetInfo/CMakeLists.txt | 10 +++
.../Target/PISA/TargetInfo/PISATargetInfo.cpp | 23 +++++
.../Target/PISA/TargetInfo/PISATargetInfo.h | 20 +++++
llvm/lib/TargetParser/TargetDataLayout.cpp | 20 +++++
llvm/lib/TargetParser/Triple.cpp | 15 ++++
llvm/test/CodeGen/PISA/lit.local.cfg | 2 +
llvm/test/CodeGen/PISA/target-registration.ll | 6 ++
31 files changed, 880 insertions(+)
create mode 100644 llvm/lib/Target/PISA/CMakeLists.txt
create mode 100644 llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt
create mode 100644 llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.cpp
create mode 100644 llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.h
create mode 100644 llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.cpp
create mode 100644 llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.h
create mode 100644 llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.cpp
create mode 100644 llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.h
create mode 100644 llvm/lib/Target/PISA/PISA.h
create mode 100644 llvm/lib/Target/PISA/PISA.td
create mode 100644 llvm/lib/Target/PISA/PISAFeatures.td
create mode 100644 llvm/lib/Target/PISA/PISAFrameLowering.h
create mode 100644 llvm/lib/Target/PISA/PISAInstrInfo.cpp
create mode 100644 llvm/lib/Target/PISA/PISAInstrInfo.h
create mode 100644 llvm/lib/Target/PISA/PISAInstrInfo.td
create mode 100644 llvm/lib/Target/PISA/PISARegisterInfo.cpp
create mode 100644 llvm/lib/Target/PISA/PISARegisterInfo.h
create mode 100644 llvm/lib/Target/PISA/PISARegisterInfo.td
create mode 100644 llvm/lib/Target/PISA/PISASubtarget.cpp
create mode 100644 llvm/lib/Target/PISA/PISASubtarget.h
create mode 100644 llvm/lib/Target/PISA/PISATargetMachine.cpp
create mode 100644 llvm/lib/Target/PISA/PISATargetMachine.h
create mode 100644 llvm/lib/Target/PISA/TargetInfo/CMakeLists.txt
create mode 100644 llvm/lib/Target/PISA/TargetInfo/PISATargetInfo.cpp
create mode 100644 llvm/lib/Target/PISA/TargetInfo/PISATargetInfo.h
create mode 100644 llvm/test/CodeGen/PISA/lit.local.cfg
create mode 100644 llvm/test/CodeGen/PISA/target-registration.ll
diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index a9d9f1d11ab44..3120758f6e8dd 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -597,6 +597,7 @@ set(LLVM_ALL_EXPERIMENTAL_TARGETS
CSKY
DirectX
M68k
+ PISA
Xtensa
)
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index 18634a8bbe6ff..9165b78106293 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -98,6 +98,7 @@ class Triple {
xtensa, // Tensilica: Xtensa
nvptx, // NVPTX: 32-bit
nvptx64, // NVPTX: 64-bit
+ pisa, // PISA: Intel GPU portable ISA (64-bit)
amdil, // AMDIL
amdil64, // AMDIL with 64-bit pointers
hsail, // AMD HSAIL
@@ -986,6 +987,9 @@ class Triple {
return getArch() == Triple::nvptx || getArch() == Triple::nvptx64;
}
+ /// Tests whether the target is PISA (64-bit only).
+ bool isPISA() const { return getArch() == Triple::pisa; }
+
/// Tests whether the target is AMDGCN
bool isAMDGCN() const { return getArch() == Triple::amdgpu; }
diff --git a/llvm/lib/Target/PISA/CMakeLists.txt b/llvm/lib/Target/PISA/CMakeLists.txt
new file mode 100644
index 0000000000000..fafef2a3c3fe8
--- /dev/null
+++ b/llvm/lib/Target/PISA/CMakeLists.txt
@@ -0,0 +1,36 @@
+add_llvm_component_group(PISA)
+
+set(LLVM_TARGET_DEFINITIONS PISA.td)
+
+tablegen(LLVM PISAGenAsmWriter.inc -gen-asm-writer)
+tablegen(LLVM PISAGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM PISAGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM PISAGenSubtargetInfo.inc -gen-subtarget)
+
+add_public_tablegen_target(PISACommonTableGen)
+
+add_llvm_target(PISACodeGen
+ PISAInstrInfo.cpp
+ PISARegisterInfo.cpp
+ PISASubtarget.cpp
+ PISATargetMachine.cpp
+
+ LINK_COMPONENTS
+ Analysis
+ CodeGen
+ CodeGenTypes
+ Core
+ MC
+ SelectionDAG
+ Support
+ Target
+ TargetParser
+ PISADesc
+ PISAInfo
+
+ ADD_TO_COMPONENT
+ PISA
+ )
+
+add_subdirectory(MCTargetDesc)
+add_subdirectory(TargetInfo)
diff --git a/llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt
new file mode 100644
index 0000000000000..1e7639e93d484
--- /dev/null
+++ b/llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt
@@ -0,0 +1,16 @@
+add_llvm_component_library(LLVMPISADesc
+ PISAMCAsmInfo.cpp
+ PISAMCTargetDesc.cpp
+ PISAInstPrinter.cpp
+
+ LINK_COMPONENTS
+ CodeGenTypes
+ Core
+ MC
+ PISAInfo
+ Support
+ TargetParser
+
+ ADD_TO_COMPONENT
+ PISA
+ )
diff --git a/llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.cpp b/llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.cpp
new file mode 100644
index 0000000000000..f16a2e1177fc8
--- /dev/null
+++ b/llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.cpp
@@ -0,0 +1,35 @@
+//===-- PISAInstPrinter.cpp - Output PISA MCInsts as ASM ------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "PISAInstPrinter.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#include "PISAGenAsmWriter.inc"
+
+void PISAInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) {
+ OS << getRegisterName(Reg);
+}
+
+void PISAInstPrinter::printInst(const MCInst *MI, uint64_t Address,
+ StringRef Annot, const MCSubtargetInfo &STI,
+ raw_ostream &OS) {
+ printInstruction(MI, Address, OS);
+ printAnnotation(OS, Annot);
+}
+
+void PISAInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O) {
+ const MCOperand &Op = MI->getOperand(OpNo);
+ if (Op.isReg())
+ printRegName(O, Op.getReg());
+ else if (Op.isImm())
+ O << Op.getImm();
+}
diff --git a/llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.h b/llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.h
new file mode 100644
index 0000000000000..11ab2987397bb
--- /dev/null
+++ b/llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.h
@@ -0,0 +1,34 @@
+//===-- PISAInstPrinter.h - Output PISA MCInsts as ASM --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAINSTPRINTER_H
+#define LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAINSTPRINTER_H
+
+#include "llvm/MC/MCInstPrinter.h"
+
+namespace llvm {
+
+class PISAInstPrinter : public MCInstPrinter {
+public:
+ using MCInstPrinter::MCInstPrinter;
+
+ void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
+ const MCSubtargetInfo &STI, raw_ostream &OS) override;
+ void printRegName(raw_ostream &OS, MCRegister Reg) override;
+ void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+
+ // Autogenerated by tblgen.
+ std::pair<const char *, uint64_t>
+ getMnemonic(const MCInst &MI) const override;
+ void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
+ static const char *getRegisterName(MCRegister Reg);
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAINSTPRINTER_H
diff --git a/llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.cpp b/llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.cpp
new file mode 100644
index 0000000000000..4543554dcc123
--- /dev/null
+++ b/llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.cpp
@@ -0,0 +1,41 @@
+//===-- PISAMCAsmInfo.cpp - PISA asm properties ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "PISAMCAsmInfo.h"
+
+#include "llvm/TargetParser/Triple.h"
+
+using namespace llvm;
+
+PISAMCAsmInfo::PISAMCAsmInfo(const Triple &TT, const MCTargetOptions &Options)
+ : MCAsmInfo(Options) {
+ IsLittleEndian = true;
+
+ HasSingleParameterDotFile = false;
+ HasDotTypeDotSizeDirective = false;
+
+ MinInstAlignment = 4;
+ CodePointerSize = 4;
+ HasFunctionAlignment = false;
+
+ SeparatorString = ";";
+ CommentString = "//";
+
+ InlineAsmStart = "Inline assembly start";
+ InlineAsmEnd = "Inline assembly end";
+
+ UseIntegratedAssembler = false;
+
+ // Allow '$' in identifier names so that register names like %$ or %$foo
+ // are correctly lexed as identifiers rather than as AsmToken::Dollar.
+ AllowDollarAtStartOfIdentifier = true;
+}
+
+bool PISAMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const {
+ return true;
+}
diff --git a/llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.h b/llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.h
new file mode 100644
index 0000000000000..497e083d2c721
--- /dev/null
+++ b/llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.h
@@ -0,0 +1,25 @@
+//===-- PISAMCAsmInfo.h - PISA asm properties -----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAMCASMINFO_H
+#define LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAMCASMINFO_H
+
+#include "llvm/MC/MCAsmInfo.h"
+
+namespace llvm {
+
+class Triple;
+
+class PISAMCAsmInfo : public MCAsmInfo {
+public:
+ explicit PISAMCAsmInfo(const Triple &TT, const MCTargetOptions &Options);
+ bool shouldOmitSectionDirective(StringRef SectionName) const override;
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAMCASMINFO_H
diff --git a/llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.cpp b/llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.cpp
new file mode 100644
index 0000000000000..5dab8ea1bba59
--- /dev/null
+++ b/llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.cpp
@@ -0,0 +1,64 @@
+//===-- PISAMCTargetDesc.cpp - PISA Target Descriptions -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "PISAMCTargetDesc.h"
+#include "PISAInstPrinter.h"
+#include "PISAMCAsmInfo.h"
+#include "TargetInfo/PISATargetInfo.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+
+#define GET_INSTRINFO_MC_DESC
+#define ENABLE_INSTR_PREDICATE_VERIFIER
+#include "PISAGenInstrInfo.inc"
+
+#define GET_SUBTARGETINFO_MC_DESC
+#include "PISAGenSubtargetInfo.inc"
+
+#define GET_REGINFO_MC_DESC
+#include "PISAGenRegisterInfo.inc"
+
+using namespace llvm;
+
+static MCInstrInfo *createPISAMCInstrInfo() {
+ MCInstrInfo *X = new MCInstrInfo();
+ InitPISAMCInstrInfo(X);
+ return X;
+}
+
+static MCRegisterInfo *createPISAMCRegisterInfo(const Triple &TT) {
+ MCRegisterInfo *X = new MCRegisterInfo();
+ InitPISAMCRegisterInfo(X, PISA::DummyReg);
+ return X;
+}
+
+static MCSubtargetInfo *createPISAMCSubtargetInfo(const Triple &TT,
+ StringRef CPU, StringRef FS) {
+ return createPISAMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, FS);
+}
+
+static MCInstPrinter *createPISAMCInstPrinter(const Triple &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI,
+ const MCInstrInfo &MII,
+ const MCRegisterInfo &MRI) {
+ assert(SyntaxVariant == 0);
+ return new PISAInstPrinter(MAI, MII, MRI);
+}
+
+// NOLINTNEXTLINE(readability-identifier-naming)
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePISATargetMC() {
+ Target *T = &getThePISATarget();
+ RegisterMCAsmInfo<PISAMCAsmInfo> X(*T);
+ TargetRegistry::RegisterMCInstrInfo(*T, createPISAMCInstrInfo);
+ TargetRegistry::RegisterMCRegInfo(*T, createPISAMCRegisterInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(*T, createPISAMCSubtargetInfo);
+ TargetRegistry::RegisterMCInstPrinter(*T, createPISAMCInstPrinter);
+}
diff --git a/llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.h b/llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.h
new file mode 100644
index 0000000000000..cb47d07cf4565
--- /dev/null
+++ b/llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.h
@@ -0,0 +1,36 @@
+//===-- PISAMCTargetDesc.h - PISA Target Descriptions ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAMCTARGETDESC_H
+#define LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAMCTARGETDESC_H
+
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/Support/DataTypes.h"
+#include <memory>
+
+namespace llvm {
+class MCInstrInfo;
+class MCRegisterInfo;
+class MCSubtargetInfo;
+class Target;
+} // namespace llvm
+
+// Defines symbolic names for PISA registers. This defines a mapping from
+// register name to register number.
+#define GET_REGINFO_ENUM
+#include "PISAGenRegisterInfo.inc"
+
+// Defines symbolic names for the PISA instructions.
+#define GET_INSTRINFO_ENUM
+#define GET_INSTRINFO_MC_HELPER_DECLS
+#include "PISAGenInstrInfo.inc"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "PISAGenSubtargetInfo.inc"
+
+#endif // LLVM_LIB_TARGET_PISA_MCTARGETDESC_PISAMCTARGETDESC_H
diff --git a/llvm/lib/Target/PISA/PISA.h b/llvm/lib/Target/PISA/PISA.h
new file mode 100644
index 0000000000000..21e5c367ce48e
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISA.h
@@ -0,0 +1,19 @@
+//===-- PISA.h - Top-level interface for PISA representation --------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_PISA_H
+#define LLVM_LIB_TARGET_PISA_PISA_H
+
+#include "MCTargetDesc/PISAMCTargetDesc.h"
+
+namespace llvm {
+class PISATargetMachine;
+class PassRegistry;
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PISA_PISA_H
diff --git a/llvm/lib/Target/PISA/PISA.td b/llvm/lib/Target/PISA/PISA.td
new file mode 100644
index 0000000000000..71277b826162b
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISA.td
@@ -0,0 +1,35 @@
+//===-- PISA.td - Describe the PISA Target Machine ---------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+include "PISAFeatures.td"
+include "PISARegisterInfo.td"
+include "PISAInstrInfo.td"
+
+// Map the pointer-like operands of the target-independent pseudo instructions
+// (STACKMAP, PATCHPOINT, ...) onto a concrete PISA register class.
+defm : RemapAllTargetPseudoPointerOperands<Reg64b>;
+
+def PISAInstrInfo : InstrInfo;
+
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+// Valid -mcpu values.
+def : Proc<"100", [Feature100]>;
+
+def PISAInstPrinter : AsmWriter {
+ string AsmWriterClassName = "InstPrinter";
+ bit isMCAsmWriter = 1;
+}
+
+def PISA : Target {
+ let InstructionSet = PISAInstrInfo;
+ let AssemblyWriters = [PISAInstPrinter];
+}
diff --git a/llvm/lib/Target/PISA/PISAFeatures.td b/llvm/lib/Target/PISA/PISAFeatures.td
new file mode 100644
index 0000000000000..7d0c7f158acd1
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISAFeatures.td
@@ -0,0 +1,11 @@
+//===-- PISAFeatures.td - Describe the PISA Features -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// Target architecture feature.
+def Feature100 : SubtargetFeature<"100", "PISATarget100", "true",
+ "Support PISA 100 instruction/feature set", []>;
diff --git a/llvm/lib/Target/PISA/PISAFrameLowering.h b/llvm/lib/Target/PISA/PISAFrameLowering.h
new file mode 100644
index 0000000000000..c3a3b88031240
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISAFrameLowering.h
@@ -0,0 +1,31 @@
+//===-- PISAFrameLowering.h - Define frame lowering for PISA --------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_PISAFRAMELOWERING_H
+#define LLVM_LIB_TARGET_PISA_PISAFRAMELOWERING_H
+
+#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/Support/Alignment.h"
+
+namespace llvm {
+class PISASubtarget;
+
+class PISAFrameLowering : public TargetFrameLowering {
+public:
+ explicit PISAFrameLowering(const PISASubtarget &Sti)
+ : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(8), 0) {}
+
+ void emitPrologue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const override {}
+ void emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const override {}
+
+ bool hasFPImpl(const MachineFunction &MF) const override { return false; }
+};
+} // namespace llvm
+#endif // LLVM_LIB_TARGET_PISA_PISAFRAMELOWERING_H
diff --git a/llvm/lib/Target/PISA/PISAInstrInfo.cpp b/llvm/lib/Target/PISA/PISAInstrInfo.cpp
new file mode 100644
index 0000000000000..c20e1a022db71
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISAInstrInfo.cpp
@@ -0,0 +1,19 @@
+//===-- PISAInstrInfo.cpp - PISA Instruction Information ------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "PISAInstrInfo.h"
+#include "PISA.h"
+#include "PISASubtarget.h"
+
+#define GET_INSTRINFO_CTOR_DTOR
+#include "PISAGenInstrInfo.inc"
+
+using namespace llvm;
+
+PISAInstrInfo::PISAInstrInfo(const PISASubtarget &STI)
+ : PISAGenInstrInfo(STI, RI), RI() {}
diff --git a/llvm/lib/Target/PISA/PISAInstrInfo.h b/llvm/lib/Target/PISA/PISAInstrInfo.h
new file mode 100644
index 0000000000000..0b411221edf54
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISAInstrInfo.h
@@ -0,0 +1,31 @@
+//===-- PISAInstrInfo.h - PISA Instruction Information --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_PISAINSTRINFO_H
+#define LLVM_LIB_TARGET_PISA_PISAINSTRINFO_H
+
+#include "PISARegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+
+#define GET_INSTRINFO_HEADER
+#include "PISAGenInstrInfo.inc"
+
+namespace llvm {
+class PISASubtarget;
+
+class PISAInstrInfo : public PISAGenInstrInfo {
+ const PISARegisterInfo RI;
+
+public:
+ PISAInstrInfo(const PISASubtarget &STI);
+
+ const PISARegisterInfo &getRegisterInfo() const { return RI; }
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PISA_PISAINSTRINFO_H
diff --git a/llvm/lib/Target/PISA/PISAInstrInfo.td b/llvm/lib/Target/PISA/PISAInstrInfo.td
new file mode 100644
index 0000000000000..de93f39b2dc01
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISAInstrInfo.td
@@ -0,0 +1,20 @@
+//===-- PISAInstrInfo.td - PISA Instruction defs ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+class PISAInst<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : Instruction {
+ let Namespace = "PISA";
+ dag OutOperandList = outs;
+ dag InOperandList = ins;
+ let AsmString = asmstr;
+ let Pattern = pattern;
+ let hasSideEffects = 0;
+}
+
+// Placeholder instruction. Real PISA instructions are added in later changes.
+def NOP : PISAInst<(outs), (ins), "nop", []>;
diff --git a/llvm/lib/Target/PISA/PISARegisterInfo.cpp b/llvm/lib/Target/PISA/PISARegisterInfo.cpp
new file mode 100644
index 0000000000000..f66db9c9e0283
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISARegisterInfo.cpp
@@ -0,0 +1,29 @@
+//===-- PISARegisterInfo.cpp - PISA Register Information ------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "PISARegisterInfo.h"
+#include "PISA.h"
+#include "PISASubtarget.h"
+#include "llvm/CodeGen/MachineFunction.h"
+
+#define GET_REGINFO_TARGET_DESC
+#include "PISAGenRegisterInfo.inc"
+
+using namespace llvm;
+
+PISARegisterInfo::PISARegisterInfo() : PISAGenRegisterInfo(PISA::DummyReg) {}
+
+const MCPhysReg *
+PISARegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+ static const MCPhysReg CalleeSavedRegs[] = {0};
+ return CalleeSavedRegs;
+}
+
+BitVector PISARegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ return BitVector(getNumRegs());
+}
diff --git a/llvm/lib/Target/PISA/PISARegisterInfo.h b/llvm/lib/Target/PISA/PISARegisterInfo.h
new file mode 100644
index 0000000000000..f10780d825eda
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISARegisterInfo.h
@@ -0,0 +1,36 @@
+//===-- PISARegisterInfo.h - PISA Register Information --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_PISAREGISTERINFO_H
+#define LLVM_LIB_TARGET_PISA_PISAREGISTERINFO_H
+
+#include "llvm/ADT/BitVector.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+#define GET_REGINFO_HEADER
+#include "PISAGenRegisterInfo.inc"
+
+namespace llvm {
+
+class PISARegisterInfo : public PISAGenRegisterInfo {
+public:
+ PISARegisterInfo();
+ const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
+ BitVector getReservedRegs(const MachineFunction &MF) const override;
+ bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
+ unsigned FIOperandNum,
+ RegScavenger *RS = nullptr) const override {
+ llvm_unreachable("unexpected execution");
+ }
+ Register getFrameRegister(const MachineFunction &MF) const override {
+ return 0;
+ }
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PISA_PISAREGISTERINFO_H
diff --git a/llvm/lib/Target/PISA/PISARegisterInfo.td b/llvm/lib/Target/PISA/PISARegisterInfo.td
new file mode 100644
index 0000000000000..b2c06a57c27a2
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISARegisterInfo.td
@@ -0,0 +1,39 @@
+//===-- PISARegisterInfo.td - PISA Register defs ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+let Namespace = "PISA" in {
+
+ class PISARegisterClass<list<ValueType> regTypes, int alignment, dag regList>
+ : RegisterClass<"PISA", regTypes, alignment, regList> {}
+
+ // .reg style registers.
+ class GeneralRegisterClass<list<ValueType> regTypes, int alignment,
+ dag regList>
+ : PISARegisterClass<regTypes, alignment, regList> {}
+
+ // .pred style registers.
+ class PredRegisterClass<list<ValueType> regTypes, int alignment, dag regList>
+ : PISARegisterClass<regTypes, alignment, regList> {}
+
+ def DummyReg : Register<"%null">;
+
+ foreach Index = 0-63 in {
+ def Reg32b_#Index : Register<"">;
+ }
+ foreach Index = 0-3 in {
+ def Reg64b_#Index : Register<"">;
+ def Pred_#Index : Register<"">;
+ }
+
+ def Pred : PredRegisterClass<[i1], 8,
+ (add DummyReg, (sequence "Pred_%u", 0, 3))>;
+ def Reg32b : GeneralRegisterClass<[i32, f32], 32,
+ (add DummyReg, (sequence "Reg32b_%u", 0, 63))>;
+ def Reg64b : GeneralRegisterClass<[i64, f64], 64,
+ (add (sequence "Reg64b_%u", 0, 3))>;
+}
diff --git a/llvm/lib/Target/PISA/PISASubtarget.cpp b/llvm/lib/Target/PISA/PISASubtarget.cpp
new file mode 100644
index 0000000000000..84d48180cae2e
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISASubtarget.cpp
@@ -0,0 +1,30 @@
+//===-- PISASubtarget.cpp - PISA Subtarget Information --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "PISASubtarget.h"
+#include "PISA.h"
+#include "PISATargetMachine.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "pisa-subtarget"
+
+#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
+#include "PISAGenSubtargetInfo.inc"
+
+PISASubtarget::PISASubtarget(const Triple &TT, const std::string &CPU,
+ const std::string &FS, const PISATargetMachine &TM)
+ : PISAGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), InstrInfo(*this),
+ FrameLowering(initSubtargetDependencies(CPU, FS)) {}
+
+PISASubtarget &PISASubtarget::initSubtargetDependencies(StringRef CPU,
+ StringRef FS) {
+ ParseSubtargetFeatures(CPU, /*TuneCPU=*/CPU, FS);
+ return *this;
+}
diff --git a/llvm/lib/Target/PISA/PISASubtarget.h b/llvm/lib/Target/PISA/PISASubtarget.h
new file mode 100644
index 0000000000000..1e2c05a37a1ce
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISASubtarget.h
@@ -0,0 +1,61 @@
+//===-- PISASubtarget.h - PISA Subtarget Information ----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_PISASUBTARGET_H
+#define LLVM_LIB_TARGET_PISA_PISASUBTARGET_H
+
+#include "PISAFrameLowering.h"
+#include "PISAInstrInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Target/TargetMachine.h"
+
+#define GET_SUBTARGETINFO_HEADER
+#include "PISAGenSubtargetInfo.inc"
+
+namespace llvm {
+class StringRef;
+class PISATargetMachine;
+
+class PISASubtarget : public PISAGenSubtargetInfo {
+private:
+ // Bool members of the SubtargetFeatures defined in tablegen.
+#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
+ bool ATTRIBUTE = DEFAULT;
+#include "PISAGenSubtargetInfo.inc"
+
+ PISAInstrInfo InstrInfo;
+ PISAFrameLowering FrameLowering;
+
+public:
+ // This constructor initializes the data members to match that
+ // of the specified triple.
+ PISASubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
+ const PISATargetMachine &TM);
+ PISASubtarget &initSubtargetDependencies(StringRef CPU, StringRef FS);
+
+ // Parses features string setting specified subtarget options.
+ // The definition of this function is auto generated by tblgen.
+ void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
+
+ const PISAInstrInfo *getInstrInfo() const override { return &InstrInfo; }
+ const PISAFrameLowering *getFrameLowering() const override {
+ return &FrameLowering;
+ }
+ const PISARegisterInfo *getRegisterInfo() const override {
+ return &InstrInfo.getRegisterInfo();
+ }
+
+ // Getters for SubtargetFeatures defined in tablegen.
+#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
+ bool GETTER() const { return ATTRIBUTE; }
+#include "PISAGenSubtargetInfo.inc"
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PISA_PISASUBTARGET_H
diff --git a/llvm/lib/Target/PISA/PISATargetMachine.cpp b/llvm/lib/Target/PISA/PISATargetMachine.cpp
new file mode 100644
index 0000000000000..79bb260240b3a
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISATargetMachine.cpp
@@ -0,0 +1,85 @@
+//===-- PISATargetMachine.cpp - Define TargetMachine for PISA -------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "PISATargetMachine.h"
+#include "PISA.h"
+#include "TargetInfo/PISATargetInfo.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/Function.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+// NOLINTNEXTLINE(readability-identifier-naming)
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePISATarget() {
+ // Register the target.
+ RegisterTargetMachine<PISATargetMachine> Y(getThePISATarget());
+}
+
+static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
+ if (!RM)
+ return Reloc::PIC_;
+ return *RM;
+}
+
+PISATargetMachine::PISATargetMachine(const Target &T, const Triple &TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ std::optional<Reloc::Model> RM,
+ std::optional<CodeModel::Model> CM,
+ CodeGenOptLevel OL, bool JIT)
+ : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
+ getEffectiveRelocModel(RM),
+ getEffectiveCodeModel(CM, CodeModel::Small), OL),
+ TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
+ Subtarget(TT, CPU.str(), FS.str(), *this) {
+ initAsmInfo();
+ setGlobalISel(true);
+ setFastISel(false);
+ setO0WantsFastISel(false);
+ setRequiresStructuredCFG(false);
+}
+
+const PISASubtarget *
+PISATargetMachine::getSubtargetImpl(const Function &F) const {
+ Attribute CPUAttr = F.getFnAttribute("target-cpu");
+ Attribute FSAttr = F.getFnAttribute("target-features");
+
+ StringRef CPU =
+ CPUAttr.isValid() ? CPUAttr.getValueAsString() : getTargetCPU();
+ StringRef FS =
+ FSAttr.isValid() ? FSAttr.getValueAsString() : getTargetFeatureString();
+
+ SmallString<128> Key(CPU);
+ Key.append(FS);
+
+ auto &I = SubtargetMap[Key];
+ if (!I)
+ I = std::make_unique<PISASubtarget>(TargetTriple, CPU.str(), FS.str(),
+ *this);
+ return I.get();
+}
+
+namespace {
+class PISAPassConfig : public TargetPassConfig {
+public:
+ PISAPassConfig(PISATargetMachine &TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
+
+ PISATargetMachine &getPISATargetMachine() const {
+ return getTM<PISATargetMachine>();
+ }
+};
+} // namespace
+
+TargetPassConfig *PISATargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new PISAPassConfig(*this, PM);
+}
diff --git a/llvm/lib/Target/PISA/PISATargetMachine.h b/llvm/lib/Target/PISA/PISATargetMachine.h
new file mode 100644
index 0000000000000..a378e4f20401a
--- /dev/null
+++ b/llvm/lib/Target/PISA/PISATargetMachine.h
@@ -0,0 +1,46 @@
+//===-- PISATargetMachine.h - Define TargetMachine for PISA ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_PISATARGETMACHINE_H
+#define LLVM_LIB_TARGET_PISA_PISATARGETMACHINE_H
+
+#include "PISASubtarget.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
+#include <memory>
+#include <optional>
+
+namespace llvm {
+class PISATargetMachine : public CodeGenTargetMachineImpl {
+ std::unique_ptr<TargetLoweringObjectFile> TLOF;
+ PISASubtarget Subtarget;
+ mutable StringMap<std::unique_ptr<PISASubtarget>> SubtargetMap;
+
+public:
+ PISATargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+ StringRef FS, const TargetOptions &Options,
+ std::optional<Reloc::Model> RM,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
+ bool JIT);
+
+ const PISASubtarget *getSubtargetImpl(const Function &F) const override;
+ // DO NOT IMPLEMENT: subtargets are per-function entities based on the
+ // target-specific attributes of each function.
+ const PISASubtarget *getSubtargetImpl() const = delete;
+
+ TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+
+ bool usesPhysRegsForValues() const override { return false; }
+
+ TargetLoweringObjectFile *getObjFileLowering() const override {
+ return TLOF.get();
+ }
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PISA_PISATARGETMACHINE_H
diff --git a/llvm/lib/Target/PISA/TargetInfo/CMakeLists.txt b/llvm/lib/Target/PISA/TargetInfo/CMakeLists.txt
new file mode 100644
index 0000000000000..15bb98644bee4
--- /dev/null
+++ b/llvm/lib/Target/PISA/TargetInfo/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_llvm_component_library(LLVMPISAInfo
+ PISATargetInfo.cpp
+
+ LINK_COMPONENTS
+ MC
+ Support
+
+ ADD_TO_COMPONENT
+ PISA
+ )
diff --git a/llvm/lib/Target/PISA/TargetInfo/PISATargetInfo.cpp b/llvm/lib/Target/PISA/TargetInfo/PISATargetInfo.cpp
new file mode 100644
index 0000000000000..eb3e9ec6f86a2
--- /dev/null
+++ b/llvm/lib/Target/PISA/TargetInfo/PISATargetInfo.cpp
@@ -0,0 +1,23 @@
+//===-- PISATargetInfo.cpp - PISA Target Implementation -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "TargetInfo/PISATargetInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+
+using namespace llvm;
+
+Target &llvm::getThePISATarget() {
+ static Target ThePISATarget;
+ return ThePISATarget;
+}
+
+// NOLINTNEXTLINE(readability-identifier-naming)
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePISATargetInfo() {
+ RegisterTarget<Triple::pisa> Y(getThePISATarget(), "pisa", "PISA 64-bit",
+ "PISA");
+}
diff --git a/llvm/lib/Target/PISA/TargetInfo/PISATargetInfo.h b/llvm/lib/Target/PISA/TargetInfo/PISATargetInfo.h
new file mode 100644
index 0000000000000..a8e4467d7a0ff
--- /dev/null
+++ b/llvm/lib/Target/PISA/TargetInfo/PISATargetInfo.h
@@ -0,0 +1,20 @@
+//===-- PISATargetInfo.h - PISA Target Implementation ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PISA_TARGETINFO_PISATARGETINFO_H
+#define LLVM_LIB_TARGET_PISA_TARGETINFO_PISATARGETINFO_H
+
+namespace llvm {
+
+class Target;
+
+Target &getThePISATarget();
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PISA_TARGETINFO_PISATARGETINFO_H
diff --git a/llvm/lib/TargetParser/TargetDataLayout.cpp b/llvm/lib/TargetParser/TargetDataLayout.cpp
index 8b6f46642e4fa..b25fb4feaaf17 100644
--- a/llvm/lib/TargetParser/TargetDataLayout.cpp
+++ b/llvm/lib/TargetParser/TargetDataLayout.cpp
@@ -509,6 +509,24 @@ static std::string computeSPIRVDataLayout(const Triple &TT) {
"v512:512-v1024:1024-n8:16:32:64-G1";
}
+static std::string computePISADataLayout(const Triple &) {
+ // little endian
+ std::string Ret = "e";
+ // pointers
+ Ret += "-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32";
+ // data type alignment
+ Ret += "-i1:8:8-i8:8:8-i16:16:16-i32:32:32"
+ "-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32"
+ "-v32:32:32-v48:64:64-v64:64:64-v96:128:128"
+ "-v128:128:128-v192:256:256-v256:256:256";
+ // default address space of global variable
+ Ret += "-G1";
+ // default address space for alloca
+ Ret += "-A4";
+
+ return Ret;
+}
+
static std::string computeLanaiDataLayout() {
// Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
return "E" // Big endian
@@ -654,6 +672,8 @@ std::string Triple::computeDataLayout(StringRef ABIName) const {
case Triple::spirv32:
case Triple::spirv64:
return computeSPIRVDataLayout(*this);
+ case Triple::pisa:
+ return computePISADataLayout(*this);
case Triple::lanai:
return computeLanaiDataLayout();
case Triple::wasm32:
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index 1e421c428d8b4..ad8a9a01d921d 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -98,6 +98,8 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
return "nvptx64";
case nvptx:
return "nvptx";
+ case pisa:
+ return "pisa";
case ppc64:
return "powerpc64";
case ppc64le:
@@ -367,6 +369,9 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case loongarch64:
return "loongarch";
+ case pisa:
+ return "pisa";
+
case dxil:
return "dx";
@@ -502,6 +507,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
.Case("xcore", xcore)
.Case("nvptx", nvptx)
.Case("nvptx64", nvptx64)
+ .Case("pisa", pisa)
.Case("amdil", amdil)
.Case("amdil64", amdil64)
.Case("hsail", hsail)
@@ -649,6 +655,7 @@ Triple::ArchType Triple::parseArch(StringRef ArchName) {
.Case("xcore", Triple::xcore)
.Case("nvptx", Triple::nvptx)
.Case("nvptx64", Triple::nvptx64)
+ .Case("pisa", Triple::pisa)
.Case("amdil", Triple::amdil)
.Case("amdil64", Triple::amdil64)
.Case("hsail", Triple::hsail)
@@ -1032,6 +1039,9 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::spirv64:
return Triple::SPIRV;
+ case Triple::pisa:
+ return Triple::ELF;
+
case Triple::dxil:
return Triple::DXContainer;
}
@@ -1782,6 +1792,7 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
case llvm::Triple::nvptx64:
+ case llvm::Triple::pisa:
case llvm::Triple::ppc64:
case llvm::Triple::ppc64le:
case llvm::Triple::renderscript64:
@@ -1840,6 +1851,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::bpfeb:
case Triple::bpfel:
case Triple::msp430:
+ case Triple::pisa:
case Triple::systemz:
case Triple::ve:
T.setArch(UnknownArch);
@@ -1978,6 +1990,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::mips64:
case Triple::mips64el:
case Triple::nvptx64:
+ case Triple::pisa:
case Triple::ppc64:
case Triple::ppc64le:
case Triple::renderscript64:
@@ -2086,6 +2099,7 @@ Triple Triple::getBigEndianArchVariant() const {
case Triple::msp430:
case Triple::nvptx64:
case Triple::nvptx:
+ case Triple::pisa:
case Triple::r600:
case Triple::renderscript32:
case Triple::renderscript64:
@@ -2226,6 +2240,7 @@ bool Triple::isLittleEndian() const {
case Triple::msp430:
case Triple::nvptx64:
case Triple::nvptx:
+ case Triple::pisa:
case Triple::ppcle:
case Triple::ppc64le:
case Triple::r600:
diff --git a/llvm/test/CodeGen/PISA/lit.local.cfg b/llvm/test/CodeGen/PISA/lit.local.cfg
new file mode 100644
index 0000000000000..3c06900f9161e
--- /dev/null
+++ b/llvm/test/CodeGen/PISA/lit.local.cfg
@@ -0,0 +1,2 @@
+if "PISA" not in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/CodeGen/PISA/target-registration.ll b/llvm/test/CodeGen/PISA/target-registration.ll
new file mode 100644
index 0000000000000..0d48deb6d9bb8
--- /dev/null
+++ b/llvm/test/CodeGen/PISA/target-registration.ll
@@ -0,0 +1,6 @@
+; Smoke test that the PISA target is registered with and selectable by llc.
+
+; RUN: llc --version 2>&1 | FileCheck %s
+
+; CHECK: Registered Targets:
+; CHECK: pisa{{.*}}- PISA 64-bit
>From e88ceb7e453985d674600aebcea601159d7944f4 Mon Sep 17 00:00:00 2001
From: Michal Paszkowski <michal.paszkowski at intel.com>
Date: Wed, 5 Aug 2026 13:54:47 -0700
Subject: [PATCH 2/2] Review fixes
---
llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt | 2 +-
llvm/lib/Target/PISA/PISARegisterInfo.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt
index 1e7639e93d484..6728d3243c695 100644
--- a/llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt
+++ b/llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt
@@ -1,7 +1,7 @@
add_llvm_component_library(LLVMPISADesc
+ PISAInstPrinter.cpp
PISAMCAsmInfo.cpp
PISAMCTargetDesc.cpp
- PISAInstPrinter.cpp
LINK_COMPONENTS
CodeGenTypes
diff --git a/llvm/lib/Target/PISA/PISARegisterInfo.h b/llvm/lib/Target/PISA/PISARegisterInfo.h
index f10780d825eda..087285386007e 100644
--- a/llvm/lib/Target/PISA/PISARegisterInfo.h
+++ b/llvm/lib/Target/PISA/PISARegisterInfo.h
@@ -28,7 +28,7 @@ class PISARegisterInfo : public PISAGenRegisterInfo {
llvm_unreachable("unexpected execution");
}
Register getFrameRegister(const MachineFunction &MF) const override {
- return 0;
+ return Register();
}
};
} // namespace llvm
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