[llvm] [AArch64] Use [SU]ADALP for partial (nx)v4i32 -> (nx)v2i64 add reduce. (PR #213915)

[Paul Walker via llvm-commits]

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@@ -34709,6 +34697,17 @@ AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
     return DAG.getExtractSubvector(DL, MVT::v2i32, Reduced, 0);
   }
 
+  // Handle (v2i64, v16i8) in two steps via v4i32 and Neon [SU]ADALP.
+  if (Subtarget->isNeonAvailable() && ResultVT == MVT::v2i64 &&
+      OpVT == MVT::v16i8) {
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paulwalker-arm wrote:

Do you think this needs restricting to just SMLA and UMLA? The block above doesn't split the extension, but this block does and makes me wonder if that's valid for SUMLA?

https://github.com/llvm/llvm-project/pull/213915