[llvm] [AArch64] Use [SU]ADALP for partial (nx)v4i32 -> (nx)v2i64 add reduce. (PR #213915)

[Ricardo Jesus via llvm-commits]

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@@ -34755,11 +34743,23 @@ AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
 
   bool IsUnsigned = Op.getOpcode() == ISD::PARTIAL_REDUCE_UMLA;
 
+  // Attempt to fold v4i32 -> v2i64 via Neon *ADALP.
+  if (Subtarget->isNeonAvailable() && OrigResultVT == MVT::v2i64) {
+    unsigned Opc = IsUnsigned ? AArch64ISD::UADDLP : AArch64ISD::SADDLP;
+    if (ConvertToScalable)
+      DotNode = convertFromScalableVector(DAG, MVT::v4i32, DotNode);
+    SDValue Res = DAG.getNode(Opc, DL, OrigResultVT, DotNode);
+    return DAG.getNode(ISD::ADD, DL, OrigResultVT, OrigAcc, Res);
+  }
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rj-jesus wrote:

Thanks for the suggestion, I've moved it just after the v16i8->v2i32 code. I think it's ConvertToScalable that's a bit too aggressive perhaps and prefers converting to scalable vectors even when Neon could be used.

https://github.com/llvm/llvm-project/pull/213915