[llvm] [AMDGPU][GISel] RegBankLegalize rule for amdgcn_lerp (PR #214324)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Chinmay Deshpande (chinmaydd)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/214324.diff


2 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+4) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll (+60-3) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 499a018828957..30f44a6fe3d67 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1961,6 +1961,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
       .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
 
+  addRulesForIOpcs({amdgcn_lerp}, Standard)
+      .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
+      .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
+
   addRulesForIOpcs(
       {amdgcn_wave_reduce_add, amdgcn_wave_reduce_and, amdgcn_wave_reduce_fadd,
        amdgcn_wave_reduce_fmax, amdgcn_wave_reduce_fmin,
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
index 8a368f69e55c2..57cb71d0328c1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
@@ -1,13 +1,70 @@
-; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL %s
 
 declare i32 @llvm.amdgcn.lerp(i32, i32, i32) #0
 
-; GCN-LABEL: {{^}}v_lerp:
-; GCN: v_lerp_u8 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
 define amdgpu_kernel void @v_lerp(ptr addrspace(1) %out, i32 %src) nounwind {
+; GCN-SDAG-LABEL: v_lerp:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_load_dword s2, s[4:5], 0x2c
+; GCN-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GCN-SDAG-NEXT:    s_movk_i32 s3, 0x64
+; GCN-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v0, s2
+; GCN-SDAG-NEXT:    v_lerp_u8 v2, v0, s3, s3
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v0, s0
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, s1
+; GCN-SDAG-NEXT:    flat_store_dword v[0:1], v2
+; GCN-SDAG-NEXT:    s_endpgm
+;
+; GCN-GISEL-LABEL: v_lerp:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_load_dword s2, s[4:5], 0x2c
+; GCN-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, 0x64
+; GCN-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_lerp_u8 v2, s2, v0, v0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, s1
+; GCN-GISEL-NEXT:    flat_store_dword v[0:1], v2
+; GCN-GISEL-NEXT:    s_endpgm
   %result= call i32 @llvm.amdgcn.lerp(i32 %src, i32 100, i32 100) #0
   store i32 %result, ptr addrspace(1) %out, align 4
   ret void
 }
 
+define amdgpu_kernel void @v_lerp_non_immediate(ptr addrspace(1) %out, i32 %src, i32 %a, i32 %b) nounwind {
+; GCN-SDAG-LABEL: v_lerp_non_immediate:
+; GCN-SDAG:       ; %bb.0:
+; GCN-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GCN-SDAG-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GCN-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v0, s1
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, s2
+; GCN-SDAG-NEXT:    v_lerp_u8 v2, s0, v0, v1
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v0, s4
+; GCN-SDAG-NEXT:    v_mov_b32_e32 v1, s5
+; GCN-SDAG-NEXT:    flat_store_dword v[0:1], v2
+; GCN-SDAG-NEXT:    s_endpgm
+;
+; GCN-GISEL-LABEL: v_lerp_non_immediate:
+; GCN-GISEL:       ; %bb.0:
+; GCN-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GCN-GISEL-NEXT:    s_load_dword s4, s[4:5], 0x34
+; GCN-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, s3
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, s4
+; GCN-GISEL-NEXT:    v_lerp_u8 v2, s2, v0, v1
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; GCN-GISEL-NEXT:    v_mov_b32_e32 v1, s1
+; GCN-GISEL-NEXT:    flat_store_dword v[0:1], v2
+; GCN-GISEL-NEXT:    s_endpgm
+  %result= call i32 @llvm.amdgcn.lerp(i32 %src, i32 %a, i32 %b) #0
+  store i32 %result, ptr addrspace(1) %out, align 4
+  ret void
+}
+
 attributes #0 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GCN: {{.*}}

``````````

</details>


https://github.com/llvm/llvm-project/pull/214324