[llvm] [AMDGPU][GISel] RegBankLegalize rule for amdgcn_cvt_pk_u8_f32 (PR #214325)
Chinmay Deshpande via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 12:59:12 PDT 2026
https://github.com/chinmaydd created https://github.com/llvm/llvm-project/pull/214325
None
>From e50759bd46441aa357f5a6e1db04a7f7767d6316 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Wed, 5 Aug 2026 12:28:51 -0700
Subject: [PATCH] [AMDGPU][GISel] RegBankLegalize rule for amdgcn_cvt_pk_u8_f32
llvm.amdgcn.cvt.pk.u8.f32 reached AMDGPURegBankLegalize without a rule and
failed with "No AMDGPU RegBankLegalize rules defined for opcode". It has the
same reg-bank shape as the neighbouring cvt_pk_*_f32 intrinsics - an i32
result from three VGPR sources - so add it to that rule set.
Convert the lit test to autogenerated checks and run it through both
SelectionDAG and GlobalISel. The byte-index inline constants still fold into
src1, and the gfx803 output is identical between the two paths.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 3 +-
llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll | 254 ++++++++++++++++--
2 files changed, 239 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 499a018828957..a93d491919323 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2016,7 +2016,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_cvt_sr_bf8_f32, amdgcn_cvt_sr_fp8_f32,
amdgcn_cvt_sr_fp8_f32_e5m3, amdgcn_cvt_pk_bf8_f32,
- amdgcn_cvt_pk_fp8_f32, amdgcn_cvt_pk_fp8_f32_e5m3},
+ amdgcn_cvt_pk_fp8_f32, amdgcn_cvt_pk_fp8_f32_e5m3,
+ amdgcn_cvt_pk_u8_f32},
Standard)
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
diff --git a/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll b/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
index 173c31e05f2eb..86afb4f33f773 100644
--- a/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
@@ -1,46 +1,215 @@
-; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,VI-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,VI-GISEL %s
declare i32 @llvm.amdgcn.cvt.pk.u8.f32(float, i32, i32) #0
-; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx_0:
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 0, v{{[0-9]+}}
define amdgpu_kernel void @v_cvt_pk_u8_f32_idx_0(ptr addrspace(1) %out, float %src, i32 %reg) {
+; SI-SDAG-LABEL: v_cvt_pk_u8_f32_idx_0:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s3
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s2, 0, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_cvt_pk_u8_f32_idx_0:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, 0, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-LABEL: v_cvt_pk_u8_f32_idx_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s3
+; VI-NEXT: v_cvt_pk_u8_f32 v2, s2, 0, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 0, i32 %reg) #0
store i32 %result, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx_1:
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 1, v{{[0-9]+}}
define amdgpu_kernel void @v_cvt_pk_u8_f32_idx_1(ptr addrspace(1) %out, float %src, i32 %reg) {
+; SI-SDAG-LABEL: v_cvt_pk_u8_f32_idx_1:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s3
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s2, 1, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_cvt_pk_u8_f32_idx_1:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, 1, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-LABEL: v_cvt_pk_u8_f32_idx_1:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s3
+; VI-NEXT: v_cvt_pk_u8_f32 v2, s2, 1, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 1, i32 %reg) #0
store i32 %result, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx_2:
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 2, v{{[0-9]+}}
define amdgpu_kernel void @v_cvt_pk_u8_f32_idx_2(ptr addrspace(1) %out, float %src, i32 %reg) {
+; SI-SDAG-LABEL: v_cvt_pk_u8_f32_idx_2:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s3
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s2, 2, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_cvt_pk_u8_f32_idx_2:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, 2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-LABEL: v_cvt_pk_u8_f32_idx_2:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s3
+; VI-NEXT: v_cvt_pk_u8_f32 v2, s2, 2, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 2, i32 %reg) #0
store i32 %result, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx_3:
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 3, v{{[0-9]+}}
define amdgpu_kernel void @v_cvt_pk_u8_f32_idx_3(ptr addrspace(1) %out, float %src, i32 %reg) {
+; SI-SDAG-LABEL: v_cvt_pk_u8_f32_idx_3:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s3
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s2, 3, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_cvt_pk_u8_f32_idx_3:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, 3, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-LABEL: v_cvt_pk_u8_f32_idx_3:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s3
+; VI-NEXT: v_cvt_pk_u8_f32 v2, s2, 3, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 3, i32 %reg) #0
store i32 %result, ptr addrspace(1) %out, align 4
ret void
}
-; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_combine:
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 0, v{{[0-9]+}}
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 1, v{{[0-9]+}}
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 2, v{{[0-9]+}}
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, 3, v{{[0-9]+}}
define amdgpu_kernel void @v_cvt_pk_u8_f32_combine(ptr addrspace(1) %out, float %src, i32 %reg) {
+; SI-SDAG-LABEL: v_cvt_pk_u8_f32_combine:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s3
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s2, 0, v0
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s2, 1, v0
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s2, 2, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, s0
+; SI-SDAG-NEXT: s_mov_b32 s5, s1
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s2, 3, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_cvt_pk_u8_f32_combine:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, 0, v0
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, 1, v0
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, 2, v0
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, 3, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-LABEL: v_cvt_pk_u8_f32_combine:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s3
+; VI-NEXT: v_cvt_pk_u8_f32 v0, s2, 0, v0
+; VI-NEXT: v_cvt_pk_u8_f32 v0, s2, 1, v0
+; VI-NEXT: v_cvt_pk_u8_f32 v0, s2, 2, v0
+; VI-NEXT: v_cvt_pk_u8_f32 v2, s2, 3, v0
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%result0 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 0, i32 %reg) #0
%result1 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 1, i32 %result0) #0
%result2 = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 2, i32 %result1) #0
@@ -49,12 +218,63 @@ define amdgpu_kernel void @v_cvt_pk_u8_f32_combine(ptr addrspace(1) %out, float
ret void
}
-; GCN-LABEL: {{^}}v_cvt_pk_u8_f32_idx:
-; GCN: v_cvt_pk_u8_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_cvt_pk_u8_f32_idx(ptr addrspace(1) %out, float %src, i32 %idx, i32 %reg) {
+; SI-SDAG-LABEL: v_cvt_pk_u8_f32_idx:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
+; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; SI-SDAG-NEXT: v_cvt_pk_u8_f32 v0, s0, v0, v1
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: v_cvt_pk_u8_f32_idx:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; SI-GISEL-NEXT: v_cvt_pk_u8_f32 v0, s2, v0, v1
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: v_cvt_pk_u8_f32_idx:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; VI-SDAG-NEXT: v_cvt_pk_u8_f32 v2, s0, v0, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: v_cvt_pk_u8_f32_idx:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: s_load_dword s4, s[4:5], 0x34
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_cvt_pk_u8_f32 v2, s2, v0, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src, i32 %idx, i32 %reg) #0
store i32 %result, ptr addrspace(1) %out, align 4
ret void
}
attributes #0 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SI: {{.*}}
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