[llvm] [AArch64][GlobalISel] Pack i1 vector to scalar bitcasts in vector registers (PR #213946)

[Ömer Sinan Ağacan via llvm-commits]

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osa1 wrote:

This block of code is not taken without the other legalizer changes in your other PR. Remove please.

https://github.com/llvm/llvm-project/pull/213946