[llvm] [AArch64][GlobalISel] Pack i1 vector to scalar bitcasts in vector registers (PR #213946)

[Ömer Sinan Ağacan via llvm-commits]

https://github.com/osa1 commented:

@Joel-Wwalker please make sure you fully understand the changes before sending for reviews.

https://github.com/llvm/llvm-project/pull/213946