[llvm] [AArch64][CodeGen] Fold tbx(splat(0), table, idxs) to tbl(table, idxs) (PR #214146)

[Durgesh Nandan Mohanty via llvm-commits]

https://github.com/dnmohanty updated https://github.com/llvm/llvm-project/pull/214146

>From ed834f4ba06bade06a50c9c0cb00fbf881d6ca56 Mon Sep 17 00:00:00 2001
From: Durgesh Nandan Mohanty <durgeshnandanmohanty at gmail.com>
Date: Wed, 5 Aug 2026 06:16:47 +0000
Subject: [PATCH 1/3] [AArch64] Optimize tbx with zero-splat to tbl (Fixes
 #214077)

---
 .../Target/AArch64/AArch64ISelLowering.cpp    | 20 +++++++++++++++++++
 llvm/test/CodeGen/AArch64/test_tbx.ll         | 11 ++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/test_tbx.ll

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 51be0e66b19b0..f41c0cae79043 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -25035,6 +25035,26 @@ static SDValue performIntrinsicCombine(SDNode *N,
   switch (IID) {
   default:
     break;
+    case Intrinsic::aarch64_neon_tbx1:
+  case Intrinsic::aarch64_neon_tbx2:
+  case Intrinsic::aarch64_neon_tbx3:
+  case Intrinsic::aarch64_neon_tbx4: {
+    if (ISD::isBuildVectorAllZeros(N->getOperand(1).getNode())) {
+      unsigned TblIID = 0;
+      if (IID == Intrinsic::aarch64_neon_tbx1) TblIID = Intrinsic::aarch64_neon_tbl1;
+      else if (IID == Intrinsic::aarch64_neon_tbx2) TblIID = Intrinsic::aarch64_neon_tbl2;
+      else if (IID == Intrinsic::aarch64_neon_tbx3) TblIID = Intrinsic::aarch64_neon_tbl3;
+      else if (IID == Intrinsic::aarch64_neon_tbx4) TblIID = Intrinsic::aarch64_neon_tbl4;
+
+      SmallVector<SDValue, 4> Ops;
+      Ops.push_back(DAG.getTargetConstant(TblIID, SDLoc(N), MVT::i32));
+      for (unsigned i = 2; i < N->getNumOperands(); ++i)
+        Ops.push_back(N->getOperand(i));
+
+      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0), Ops);
+    }
+    break;
+  }
   case Intrinsic::aarch64_neon_vcvtfxs2fp:
   case Intrinsic::aarch64_neon_vcvtfxu2fp:
     return tryCombineFixedPointConvert(N, DCI, DAG);
diff --git a/llvm/test/CodeGen/AArch64/test_tbx.ll b/llvm/test/CodeGen/AArch64/test_tbx.ll
new file mode 100644
index 0000000000000..d7752e0d07494
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/test_tbx.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=aarch64 -mattr=+neon < %s | FileCheck %s
+
+define <16 x i8> @test_zero_splat(<16 x i8> %tbl, <16 x i8> %idx) {
+; CHECK-LABEL: test_zero_splat:
+; CHECK: tbl
+; CHECK: ret
+  %res = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> zeroinitializer, <16 x i8> %tbl, <16 x i8> %idx)
+  ret <16 x i8> %res
+}
+
+declare <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
\ No newline at end of file

>From 3f56a5ffaedba22f25ddc73263bc057b62396dc0 Mon Sep 17 00:00:00 2001
From: Durgesh Nandan Mohanty <durgeshnandanmohanty at gmail.com>
Date: Wed, 5 Aug 2026 06:39:06 +0000
Subject: [PATCH 2/3] Fix tbx optimization

---
 test_tbx.ll | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 test_tbx.ll

diff --git a/test_tbx.ll b/test_tbx.ll
new file mode 100644
index 0000000000000..d7752e0d07494
--- /dev/null
+++ b/test_tbx.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=aarch64 -mattr=+neon < %s | FileCheck %s
+
+define <16 x i8> @test_zero_splat(<16 x i8> %tbl, <16 x i8> %idx) {
+; CHECK-LABEL: test_zero_splat:
+; CHECK: tbl
+; CHECK: ret
+  %res = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> zeroinitializer, <16 x i8> %tbl, <16 x i8> %idx)
+  ret <16 x i8> %res
+}
+
+declare <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
\ No newline at end of file

>From d61f4b77f211178ed4a45f2e3ed8a4e147a90c61 Mon Sep 17 00:00:00 2001
From: Durgesh Nandan Mohanty <durgeshnandanmohanty at gmail.com>
Date: Wed, 5 Aug 2026 08:23:21 +0000
Subject: [PATCH 3/3] Fix clang-format issues

---
 .../Target/AArch64/AArch64ISelLowering.cpp    | 27 ++++++++++++-------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f41c0cae79043..851e2aba026ed 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -25040,16 +25040,23 @@ static SDValue performIntrinsicCombine(SDNode *N,
   case Intrinsic::aarch64_neon_tbx3:
   case Intrinsic::aarch64_neon_tbx4: {
     if (ISD::isBuildVectorAllZeros(N->getOperand(1).getNode())) {
-      unsigned TblIID = 0;
-      if (IID == Intrinsic::aarch64_neon_tbx1) TblIID = Intrinsic::aarch64_neon_tbl1;
-      else if (IID == Intrinsic::aarch64_neon_tbx2) TblIID = Intrinsic::aarch64_neon_tbl2;
-      else if (IID == Intrinsic::aarch64_neon_tbx3) TblIID = Intrinsic::aarch64_neon_tbl3;
-      else if (IID == Intrinsic::aarch64_neon_tbx4) TblIID = Intrinsic::aarch64_neon_tbl4;
-
-      SmallVector<SDValue, 4> Ops;
-      Ops.push_back(DAG.getTargetConstant(TblIID, SDLoc(N), MVT::i32));
-      for (unsigned i = 2; i < N->getNumOperands(); ++i)
-        Ops.push_back(N->getOperand(i));
+     unsigned TblIID = 0;
+        if (IID == Intrinsic::aarch64_neon_tbx1)
+          TblIID = Intrinsic::aarch64_neon_tbl1;
+        else if (IID == Intrinsic::aarch64_neon_tbx2)
+          TblIID = Intrinsic::aarch64_neon_tbl2;
+        else if (IID == Intrinsic::aarch64_neon_tbx3)
+          TblIID = Intrinsic::aarch64_neon_tbl3;
+        else if (IID == Intrinsic::aarch64_neon_tbx4)
+          TblIID = Intrinsic::aarch64_neon_tbl4;
+
+        SmallVector<SDValue, 4> Ops;
+        Ops.push_back(DAG.getTargetConstant(TblIID, SDLoc(N), MVT::i32));
+        for (unsigned i = 2; i < N->getNumOperands(); ++i)
+          Ops.push_back(N->getOperand(i));
+
+        return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
+                           Ops);
 
       return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0), Ops);
     }