[llvm] [X86] Replace custom AND/OR/XOR reduction pattern matching with ISD::VECREDUCE_AND/OR/XOR support (PR #199544)

[Phoebe Wang via llvm-commits]

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@@ -23673,16 +23676,14 @@ static SDValue MatchVectorAllEqualTest(SDValue OrigLHS, SDValue OrigRHS,
 
   // Match icmp(reduce_or(X),0) anyof reduction patterns.
   // Match icmp(reduce_and(X),-1) allof reduction patterns.
-  if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
-    ISD::NodeType BinOp;
-    if (SDValue Match =
-            DAG.matchBinOpReduction(Op.getNode(), BinOp, {LogicOp})) {
-      EVT MatchVT = Match.getValueType();
-      return LowerVectorAllEqual(DL, Match,
-                                 CmpNull ? DAG.getConstant(0, DL, MatchVT)
-                                         : DAG.getAllOnesConstant(DL, MatchVT),
-                                 CC, Mask, Subtarget, DAG, X86CC);
-    }
+  if ((LogicOp == ISD::AND && Op.getOpcode() == ISD::VECREDUCE_AND) ||
+      (LogicOp == ISD::OR && Op.getOpcode() == ISD::VECREDUCE_OR)) {
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phoebewang wrote:

Use `CmpNull`, `!CmpNull` instead?

https://github.com/llvm/llvm-project/pull/199544