[llvm] [X86] Replace custom AND/OR/XOR reduction pattern matching with ISD::VECREDUCE_AND/OR/XOR support (PR #199544)

[Phoebe Wang via llvm-commits]

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@@ -48174,6 +48179,12 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
   return SDValue();
 }
 
+static SDValue combineVECREDUCE_LOGIC(SDNode *N, SelectionDAG &DAG,
+                                      const X86Subtarget &Subtarget) {
+  // Attempt to replace an all_of/any_of horizontal reduction with a MOVMSK.
+  return combinePredicateReduction(N, DAG, Subtarget);
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phoebewang wrote:

Doesn't the function handle logic reduction only? Why wrap it again?

https://github.com/llvm/llvm-project/pull/199544