[llvm] [RISC-V][MC] Add a few more tests for invalid lw operands (PR #214070)

[Alexander Richardson via llvm-commits]

https://github.com/arichardson created https://github.com/llvm/llvm-project/pull/214070

To show the difference in diagnostic output as suggested in
https://github.com/llvm/llvm-project/pull/210901.


>From ced31fd689911d8c1408cd63b44160ccb104484d Mon Sep 17 00:00:00 2001
From: Alexander Richardson <mail at alexrichardson.me>
Date: Tue, 4 Aug 2026 13:58:42 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
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Created using spr 1.3.8-beta.1-arichardson
---
 llvm/test/MC/RISCV/rv32i-invalid.s | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s
index 6706596ca2c09..6d9f0ca18e232 100644
--- a/llvm/test/MC/RISCV/rv32i-invalid.s
+++ b/llvm/test/MC/RISCV/rv32i-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 | FileCheck %s --implicit-check-not="note:"
 
 # Out of range immediates
 ## fencearg
@@ -74,6 +74,16 @@ add a1, a2, (a3)
 # CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
 # CHECK: :[[@LINE-2]]:13: note: register must be a GPR
 # CHECK: :[[@LINE-3]]:13: note: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
+lw a0, -2049(a3)
+# CHECK: :[[@LINE-1]]:8: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
+lw a0, -2049(f0)
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:8: note: operand must be a bare symbol name
+# CHECK: :[[@LINE-3]]:8: note: expected '('
+# CHECK: :[[@LINE-4]]:8: note: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
+# CHECK: :[[@LINE-5]]:8: note: immediate must be an integer in the range [-2048, 2047]
+ld a0, (a3)
+# CHECK: :[[@LINE-1]]:1: error: instruction requires the following: 'Zilsd' (Load/Store pair instructions)
 
 add a1, a2, foo
 # CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
@@ -174,6 +184,10 @@ nandi t0, zero, 0 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemoni
 addi foo, sp, 10 # CHECK: :[[@LINE]]:6: error: register must be a GPR
 slti a10, a2, 0x20 # CHECK: :[[@LINE]]:6: error: register must be a GPR
 slt x32, s0, s0 # CHECK: :[[@LINE]]:5: error: register must be a GPR
+lw a0, 0(f0)
+# CHECK: :[[@LINE-1]]:10: error: register must be a GPR
+lw a0, (f0)
+# CHECK: :[[@LINE-1]]:9: error: register must be a GPR
 
 # RV64I mnemonics
 addiw a0, sp, 100 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}