[llvm] [AArch64] SME definitions for C1-Nano scheduling model (PR #207174)

[Asher Dobrescu via llvm-commits]

https://github.com/Asher8118 commented:

Thank you for addressing the comments. Most have been completed. There are only a couple that are remaining:
- Floating point divide, F64 form is showing the incorrect execution information, it should be L17 T1/17, but is currently showing as L22 T1/19.
- ASIMD FP conditional compares seem to show latency 3 when it should be 4.

https://github.com/llvm/llvm-project/pull/207174