[llvm] [AArch64] SME definitions for C1-Nano scheduling model (PR #207174)

[via llvm-commits]

walkerkd wrote:

> Thank you for the changes. They have added in a lot of fixes. Here are some leftovers from my previous reviews:
> 
> * Predicate counting vector (eg: DECB) and predicate counting vector saturating (eg: SQDECB) both show the wrong execution information. They should both show L4 T2.
> * LD3B and LD4B eg: ld3b	{ z0.b - z2.b }, p0/z, [x0, x0] should show throughput of 1/2 but it is currently showing as 2/1. To be clear, the Rthroughput should be 2, so `llvm-mca` should show an RThroughput of 2 to make it match the SWOG.

I missed both of these due to errors I had introduced into a local script I use for locally checking the SWOGs with the llvm-mca tests while trying to handle some special cases.

> Other discrepancies I've found:
> 
> * `CPP` instruction should have L1/2 T2, currently showing as L1 T1.|
> * Not a discrepancy, but I would like an example added to `C1Nano-streaming-sme-only-instructions` of add replicated single vector to multi-vector with multi-vector result, 4-reg ADD. eg: `add       { z0.s - z3.s }, { z0.s - z3.s }, z4.s`.
> * Similarly, I'd like to see an example of 4-reg `SCLAMP`, eg: `sclamp  { z0.s - z3.s }, z4.s, z5.s`
> * In general I think a few of the 4-reg cases are missing from `C1Nano-streaming-sme-only-instructions`.

Added a bunch of 4-reg variants (including the above ones you mentionted).

> * `LD1Q` currently shows as L7 T1 when it should have latency of 2.
> * `ST1Q` currently shows as L11 T1 when it should have latency of 2.
> * In general I think it'd be good to look over the SME loads and stores.

I fixed the load/store issues that I could find.



https://github.com/llvm/llvm-project/pull/207174