[llvm] [AArch64][DAG] Widen small types for Min/Max opertations (PR #212966)

[Jack Styles via llvm-commits]

Stylie777 wrote:

> An alternative approach here would be, instead of using INSERT_SUBVECTOR+SMIN+EXTRACT_SUBVECTOR, use ANY_EXTEND to v2i32+BITCAST to v416+SMIN+BITCAST to v2i32+TRUNCATE to v2i16. (The ANY_EXTEND and TRUNCATE go away after type legalization.) This doesn't fight the type legalizer: the operation happens in the type legalizer's preferred layout for the vector register. And the costs are more likely to match what we predict. (In isolation, smin should be one instruction, and we should attribute the pack/unpack ops to the load/store instructions.)
It might be a little harder to remove extra pack/unpack operations in this form, though.

I gave this a go and it does improve CodeGen, but still keeps a `usshl` pattern for `v2i8` which I was trying to eradicate completely.



https://github.com/llvm/llvm-project/pull/212966