[llvm] [RISCV] Reduce spill/reload pairs when Xqcilo extension is enabled (PR #212807)

[Garvit Gupta via llvm-commits]

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@@ -615,6 +640,18 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
       // instruction will add 4 to the immediate. If that would overflow 12
       // bits, we can't fold the offset.
       MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
+    } else if (!isInt<12>(Val) && ST.hasVendorXqcilo() &&
+               getXqciloWideOpcode(Opc)) {
+      // The resolved frame offset exceeds simm12 but the instruction is a
+      // standard load/store (LW/SW/etc). Promote to the wide Xqcilo equivalent
+      // so the full 26-bit offset folds directly, avoiding a separate
+      // base-adjust instruction. This runs post-RA and does not affect
+      // register allocation decisions.
+      unsigned WideOpc = getXqciloWideOpcode(Opc);
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quic-garvgupt wrote:

Fixed

https://github.com/llvm/llvm-project/pull/212807