[llvm] [GlobalISel][AArch64] Optimize shl, lshr, ashr (PR #213576)

[Yeongu Choe via llvm-commits]

YeonguChoe wrote:

First of all, I want to say I am not expert in ARM ISA as you. And I am fixing this problem based on your test suite (https://davemgreen.github.io/gisel.html).

Codewise,

Original authors of GlobalIsel designed it to have two parts. Which are target-independent part (generic Machine IR) and target-dependent part (each target backends, including ARM architecture). Target independent part should be common across the architectures.

For this problem, in the gMIR, `G_SHL`, `G_LSHR`, `G_ASHR` are grouped into a set (https://llvm.org/docs/GlobalISel/GenericOpcode.html#g-shl-g-lshr-g-ashr). So this is the right place to fix for this problem. All three generic MIR moves together.

We can also observe this pattern in yout test suite.

<img width="1954" height="986" alt="globalisel-test-suite" src="https://github.com/user-attachments/assets/34a82295-d01d-470e-956a-8aef32db1b7a" />

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If we change extension operation, it is likely to introduce a new regression.



https://github.com/llvm/llvm-project/pull/213576