[llvm] [AArch64][GlobalISel] Update extended scalar type to integer. (PR #213457)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 1 08:23:40 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/213457
This updates a number of scalar types in CallLowering to use integer.
>From e693953b668e22fd8def428b43778c9e1147d49b Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sat, 1 Aug 2026 16:09:54 +0100
Subject: [PATCH] [AArch64][GlobalISel] Update extended scalar type to integer.
This updates a number of scalar types in CallLowering to use integer.
---
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 8 +-
.../AArch64/GlobalISel/ret-vec-promote.ll | 16 ++--
.../CodeGen/AArch64/GlobalISel/vec-param.ll | 88 +++++++++----------
.../GlobalISel/function-returns.v2i65.ll | 4 +-
.../AMDGPU/GlobalISel/irtranslator-call.ll | 12 +--
.../irtranslator-function-args.v2i65.ll | 8 +-
6 files changed, 68 insertions(+), 68 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 46be2c0465fed..697a33d88d1da 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -518,7 +518,7 @@ void CallLowering::buildCopyFromRegs(MachineIRBuilder &B,
SmallVector<Register, 8> EltMerges;
int PartsPerElt =
divideCeil(DstEltTy.getSizeInBits(), PartLLT.getSizeInBits());
- LLT ExtendedPartTy = LLT::scalar(PartLLT.getSizeInBits() * PartsPerElt);
+ LLT ExtendedPartTy = LLT::integer(PartLLT.getSizeInBits() * PartsPerElt);
for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
auto Merge =
@@ -628,8 +628,8 @@ void CallLowering::buildCopyToRegs(MachineIRBuilder &B,
SrcTy.getScalarSizeInBits() > PartTy.getSizeInBits()) {
LLT ExtTy =
LLT::vector(SrcTy.getElementCount(),
- LLT::scalar(PartTy.getScalarSizeInBits() * DstRegs.size() /
- SrcTy.getNumElements()));
+ LLT::integer(PartTy.getScalarSizeInBits() * DstRegs.size() /
+ SrcTy.getNumElements()));
auto Ext = B.buildAnyExt(ExtTy, SrcReg);
B.buildUnmerge(DstRegs, Ext);
return;
@@ -667,7 +667,7 @@ void CallLowering::buildCopyToRegs(MachineIRBuilder &B,
// For scalars, it's common to be able to use a simple extension.
if (SrcTy.isScalar() && DstTy.isScalar()) {
CoveringSize = alignTo(SrcSize, DstSize);
- LLT CoverTy = LLT::scalar(CoveringSize);
+ LLT CoverTy = LLT::integer(CoveringSize);
UnmergeSrc = B.buildInstr(ExtendOp, {CoverTy}, {SrcReg}).getReg(0);
} else {
// Widen to the common type.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll b/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
index 3066e868c9504..3f8144c2c558e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
@@ -353,8 +353,8 @@ define <1 x i100> @ret_v1i100(i100 %v1, i100 %v2) {
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](i128)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](i100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i128) = G_ANYEXT [[TRUNC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](i128)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
@@ -380,8 +380,8 @@ define <2 x i100> @ret_v2i100(i100 %v1, i100 %v2) {
; CHECK-NEXT: [[C1:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x i100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i100), [[C]](i64)
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s128>) = G_ANYEXT [[IVEC1]](<2 x i100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<2 x s128>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i128>) = G_ANYEXT [[IVEC1]](<2 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<2 x i128>)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
@@ -412,8 +412,8 @@ define <3 x i100> @ret_v3i100(i100 %v1, i100 %v2) {
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](i100), [[C]](i64)
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x i100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC1]](i100), [[C2]](i64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<3 x s128>) = G_ANYEXT [[IVEC2]](<3 x i100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64), [[UV4:%[0-9]+]]:_(i64), [[UV5:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<3 x s128>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<3 x i128>) = G_ANYEXT [[IVEC2]](<3 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64), [[UV4:%[0-9]+]]:_(i64), [[UV5:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<3 x i128>)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
@@ -449,8 +449,8 @@ define <4 x i100> @ret_v4i100(i100 %v1, i100 %v2) {
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](i100), [[C1]](i64)
; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[TRUNC]](i100), [[C2]](i64)
; CHECK-NEXT: [[IVEC3:%[0-9]+]]:_(<4 x i100>) = G_INSERT_VECTOR_ELT [[IVEC2]], [[TRUNC1]](i100), [[C3]](i64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s128>) = G_ANYEXT [[IVEC3]](<4 x i100>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64), [[UV4:%[0-9]+]]:_(i64), [[UV5:%[0-9]+]]:_(i64), [[UV6:%[0-9]+]]:_(i64), [[UV7:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<4 x s128>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x i128>) = G_ANYEXT [[IVEC3]](<4 x i100>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64), [[UV2:%[0-9]+]]:_(i64), [[UV3:%[0-9]+]]:_(i64), [[UV4:%[0-9]+]]:_(i64), [[UV5:%[0-9]+]]:_(i64), [[UV6:%[0-9]+]]:_(i64), [[UV7:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](<4 x i128>)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: $x2 = COPY [[UV2]](i64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll b/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
index 1cea16f2782c0..84ffe3f9e0904 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll
@@ -190,8 +190,8 @@ define i100 @v1i100(<1 x i100> %v) {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](i128)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC]](i100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i128) = G_ANYEXT [[TRUNC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](i128)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
@@ -208,15 +208,15 @@ define i100 @v2i100(<2 x i100> %v) {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](i128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](i128)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x i100>), [[C]](i64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](i128)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
@@ -235,17 +235,17 @@ define i100 @v3i100(<3 x i100> %v) {
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i64) = COPY $x4
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](i128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](i128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](i128)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x i100>), [[C]](i64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](i128)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
@@ -266,19 +266,19 @@ define i100 @v4i100(<4 x i100> %v) {
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i64) = COPY $x5
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i64) = COPY $x6
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i64) = COPY $x7
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](i64), [[COPY7]](i64)
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i100) = G_TRUNC [[MV3]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](i128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](i128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](i128)
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY6]](i64), [[COPY7]](i64)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i100) = G_TRUNC [[MV3]](i128)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100), [[TRUNC3]](i100)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x i100>), [[C]](i64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](i128)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
@@ -315,27 +315,27 @@ define i100 @v8i100(<8 x i100> %v) {
; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load (i64) from %fixed-stack.1, align 16)
; CHECK-NEXT: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(i64) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load (i64) from %fixed-stack.0)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](s128)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](s128)
- ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](s128)
- ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](i64), [[COPY7]](i64)
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i100) = G_TRUNC [[MV3]](s128)
- ; CHECK-NEXT: [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD]](i64), [[LOAD1]](i64)
- ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i100) = G_TRUNC [[MV4]](s128)
- ; CHECK-NEXT: [[MV5:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD2]](i64), [[LOAD3]](i64)
- ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i100) = G_TRUNC [[MV5]](s128)
- ; CHECK-NEXT: [[MV6:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD4]](i64), [[LOAD5]](i64)
- ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(i100) = G_TRUNC [[MV6]](s128)
- ; CHECK-NEXT: [[MV7:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD6]](i64), [[LOAD7]](i64)
- ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(i100) = G_TRUNC [[MV7]](s128)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i100) = G_TRUNC [[MV]](i128)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY2]](i64), [[COPY3]](i64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i100) = G_TRUNC [[MV1]](i128)
+ ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY4]](i64), [[COPY5]](i64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i100) = G_TRUNC [[MV2]](i128)
+ ; CHECK-NEXT: [[MV3:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY6]](i64), [[COPY7]](i64)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i100) = G_TRUNC [[MV3]](i128)
+ ; CHECK-NEXT: [[MV4:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[LOAD]](i64), [[LOAD1]](i64)
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(i100) = G_TRUNC [[MV4]](i128)
+ ; CHECK-NEXT: [[MV5:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[LOAD2]](i64), [[LOAD3]](i64)
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(i100) = G_TRUNC [[MV5]](i128)
+ ; CHECK-NEXT: [[MV6:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[LOAD4]](i64), [[LOAD5]](i64)
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(i100) = G_TRUNC [[MV6]](i128)
+ ; CHECK-NEXT: [[MV7:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[LOAD6]](i64), [[LOAD7]](i64)
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(i100) = G_TRUNC [[MV7]](i128)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i100>) = G_BUILD_VECTOR [[TRUNC]](i100), [[TRUNC1]](i100), [[TRUNC2]](i100), [[TRUNC3]](i100), [[TRUNC4]](i100), [[TRUNC5]](i100), [[TRUNC6]](i100), [[TRUNC7]](i100)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(i100) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<8 x i100>), [[C]](i64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[EVEC]](i100)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i128) = G_ANYEXT [[EVEC]](i100)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[ANYEXT]](i128)
; CHECK-NEXT: $x0 = COPY [[UV]](i64)
; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
index 603d3145965a2..98b6d6f8da429 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
@@ -6,8 +6,8 @@ define <2 x i65> @v2i65_func_void() #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x i65>) = G_LOAD [[DEF]](p1) :: (load (<2 x i65>) from `ptr addrspace(1) poison`, align 32, addrspace 1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s96>) = G_ANYEXT [[LOAD]](<2 x i65>)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[ANYEXT]](<2 x s96>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x i96>) = G_ANYEXT [[LOAD]](<2 x i65>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[ANYEXT]](<2 x i96>)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](i32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
index baa245509e7aa..465e87d84a824 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
@@ -1187,8 +1187,8 @@ define amdgpu_kernel void @test_call_external_void_func_i48(i32) #0 {
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](i48)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[LOAD]](i48)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[ANYEXT]](i64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
@@ -1249,8 +1249,8 @@ define amdgpu_kernel void @test_call_external_void_func_i48_signext(i32) #0 {
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](i48)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[SEXT]](s64)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(i64) = G_SEXT [[LOAD]](i48)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[SEXT]](i64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
@@ -1311,8 +1311,8 @@ define amdgpu_kernel void @test_call_external_void_func_i48_zeroext(i32) #0 {
; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[COPY19]], [[C2]](i32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](i48)
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[ZEXT]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i64) = G_ZEXT [[LOAD]](i48)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[ZEXT]](i64)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](i32)
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
index 229f1e23050c2..c03392d5423e6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
@@ -12,10 +12,10 @@ define void @void_func_v2i65(<2 x i65> %arg0) #0 {
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $vgpr3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $vgpr4
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $vgpr5
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i65) = G_TRUNC [[MV]](s96)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i65) = G_TRUNC [[MV1]](s96)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i96) = G_MERGE_VALUES [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i65) = G_TRUNC [[MV]](i96)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(i96) = G_MERGE_VALUES [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i65) = G_TRUNC [[MV1]](i96)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i65>) = G_BUILD_VECTOR [[TRUNC]](i65), [[TRUNC1]](i65)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x i65>), [[DEF]](p1) :: (store (<2 x i65>) into `ptr addrspace(1) poison`, align 32, addrspace 1)
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