[llvm] AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs (part 4) (PR #213353)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 31 13:50:19 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: vangthao95
<details>
<summary>Changes</summary>
Migrate G_FFREXP, G_FMODF, rounding operations, and the LOG/EXP families to extended LLTs.
Remove f64 for G_FLOG and G_FLOG10 since there is no custom lowering for them. Adjust G_AND masking for LOG/EXP using extended LLTs.
Update the relevant MIR tests and *.ll tests.
---
Patch is 692.24 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213353.diff
13 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+41-44)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir (+198-196)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir (+893-560)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir (+210-208)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir (+163-161)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir (+163-161)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir (+52-52)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir (+1103-888)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir (+192-190)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp.ll (+1087-533)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp10.ll (+1087-533)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log.ll (+776-376)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log10.ll (+776-376)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 6bf05f9808d78..a7dd7cda693a2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -739,7 +739,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
const std::initializer_list<LLT> FPTypesPK16_64 = {S32, S64, S16, V2S16,
V2S64};
- const LLT MinScalarFPTy = ST.has16BitInsts() ? S16 : S32;
const LLT MinExtendedFPTy = ST.has16BitInsts() ? F16 : F32;
const LLT I1 = LLT::integer(1);
const LLT I16 = LLT::integer(16);
@@ -1104,12 +1103,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
getActionDefinitionsBuilder(G_FFREXP)
- .customFor({{S32, S32}, {S64, S32}, {S16, S16}, {S16, S32}})
- .scalarize(0)
- .lower();
+ .customFor({{F32, I32}, {F64, I32}, {F16, I16}, {F16, I32}})
+ .scalarize(0)
+ .lower();
getActionDefinitionsBuilder(G_FMODF)
- .lowerFor({S16, S32, S64})
+ .lowerFor({F16, F32, F64})
.scalarize(0)
.lower();
} else {
@@ -1140,14 +1139,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
getActionDefinitionsBuilder(G_FFREXP)
- .customFor({{S32, S32}, {S64, S32}})
- .scalarize(0)
- .minScalar(0, S32)
- .clampScalar(1, S32, S32)
- .lower();
+ .customFor({{F32, I32}, {F64, I32}})
+ .scalarize(0)
+ .minScalar(0, F32)
+ .clampScalar(1, I32, I32)
+ .lower();
getActionDefinitionsBuilder(G_FMODF)
- .lowerFor({S32, S64})
+ .lowerFor({F32, F64})
.scalarize(0)
.lower();
}
@@ -1292,26 +1291,18 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.scalarize(0)
.lower();
- if (ST.has16BitInsts()) {
- getActionDefinitionsBuilder(
- {G_INTRINSIC_TRUNC, G_FCEIL, G_INTRINSIC_ROUNDEVEN})
- .legalFor({S16, S32, S64})
- .clampScalar(0, S16, S64)
- .scalarize(0);
- } else if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
- getActionDefinitionsBuilder(
- {G_INTRINSIC_TRUNC, G_FCEIL, G_INTRINSIC_ROUNDEVEN})
- .legalFor({S32, S64})
- .clampScalar(0, S32, S64)
- .scalarize(0);
- } else {
- getActionDefinitionsBuilder(
- {G_INTRINSIC_TRUNC, G_FCEIL, G_INTRINSIC_ROUNDEVEN})
- .legalFor({S32})
- .customFor({S64})
- .clampScalar(0, S32, S64)
- .scalarize(0);
- }
+ auto &RoundingActions = getActionDefinitionsBuilder(
+ {G_INTRINSIC_TRUNC, G_FCEIL, G_INTRINSIC_ROUNDEVEN});
+ if (ST.has16BitInsts())
+ RoundingActions.legalFor({F16, F32, F64});
+ else if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
+ RoundingActions.legalFor({F32, F64});
+ else
+ RoundingActions.legalFor({F32}).customFor({F64});
+
+ RoundingActions.scalarize(0);
+ if (!ST.has16BitInsts())
+ RoundingActions.minScalar(0, F32);
getActionDefinitionsBuilder(G_PTR_ADD)
.unsupportedFor({BufferFatPtr, BufferStridedPtr, RsrcPtr})
@@ -1375,22 +1366,24 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
getActionDefinitionsBuilder(G_FLOG2)
- .legalFor(ST.has16BitInsts(), {S16})
- .customFor({S32, S16})
+ .legalFor(ST.has16BitInsts(), {F16})
+ .customFor({F32, F16})
.scalarize(0)
.lower();
getActionDefinitionsBuilder(G_FEXP2)
- .legalFor(ST.has16BitInsts(), {S16})
- .customFor({S32, S64, S16})
+ .legalFor(ST.has16BitInsts(), {F16})
+ .customFor({F32, F64, F16})
.scalarize(0)
.lower();
- auto &LogOps =
- getActionDefinitionsBuilder({G_FLOG, G_FLOG10, G_FEXP, G_FEXP10});
- LogOps.customFor({S32, S16, S64});
- LogOps.clampScalar(0, MinScalarFPTy, S32)
- .scalarize(0);
+ getActionDefinitionsBuilder({G_FLOG, G_FLOG10})
+ .customFor({F16, F32})
+ .scalarize(0);
+
+ getActionDefinitionsBuilder({G_FEXP, G_FEXP10})
+ .customFor({F16, F32, F64})
+ .scalarize(0);
// The 64-bit versions produce 32-bit results, but only on the SALU.
getActionDefinitionsBuilder(G_CTPOP)
@@ -3802,8 +3795,10 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI,
auto CH = B.buildFConstant(Ty, IsLog10 ? ch_log10 : ch_log);
auto CT = B.buildFConstant(Ty, IsLog10 ? ct_log10 : ct_log);
- auto MaskConst = B.buildConstant(Ty, 0xfffff000);
- auto YH = B.buildAnd(Ty, Y, MaskConst);
+ const LLT I32 = LLT::integer(32);
+ auto YInt = B.buildBitcast(I32, Y);
+ auto MaskConst = B.buildConstant(I32, 0xfffff000);
+ auto YH = B.buildBitcast(Ty, B.buildAnd(I32, YInt, MaskConst));
auto YT = B.buildFSub(Ty, Y, YH, Flags);
// This adds correction terms for which contraction may lead to an increase
// in the error of the approximation, so disable it.
@@ -4236,8 +4231,10 @@ bool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI,
const float ch_exp10 = 0x1.a92000p+1f;
const float cl_exp10 = 0x1.4f0978p-11f;
- auto MaskConst = B.buildConstant(Ty, 0xfffff000);
- auto XH = B.buildAnd(Ty, X, MaskConst);
+ const LLT I32 = LLT::integer(32);
+ auto XInt = B.buildBitcast(I32, X);
+ auto MaskConst = B.buildConstant(I32, 0xfffff000);
+ auto XH = B.buildBitcast(Ty, B.buildAnd(I32, XInt, MaskConst));
auto XL = B.buildFSub(Ty, X, XH, Flags);
auto CH = B.buildFConstant(Ty, IsExp10 ? ch_exp10 : ch_exp);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
index 826132d6e9010..70e9a4ff7a77c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
@@ -7,106 +7,108 @@
# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GFX9 %s
---
-name: test_fceil_s16
+name: test_fceil_f16
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_fceil_s16
+ ; SI-LABEL: name: test_fceil_f16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; CI-LABEL: name: test_fceil_s16
+ ; CI-LABEL: name: test_fceil_f16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
- ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
- ; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; CI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT]]
+ ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL]](f32)
+ ; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; CI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; VI-LABEL: name: test_fceil_s16
+ ; VI-LABEL: name: test_fceil_f16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f16) = G_FCEIL [[TRUNC]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FCEIL]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_fceil_s16
+ ; GFX9-LABEL: name: test_fceil_f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FCEIL %1
- %3:_(s32) = G_ANYEXT %2
- $vgpr0 = COPY %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f16) = G_FCEIL [[TRUNC]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FCEIL]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i16) = G_TRUNC %0
+ %2:_(f16) = G_BITCAST %1
+ %3:_(f16) = G_FCEIL %2
+ %4:_(i16) = G_BITCAST %3
+ %5:_(i32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
...
---
-name: test_fceil_s32
+name: test_fceil_f32
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_fceil_s32
+ ; SI-LABEL: name: test_fceil_f32
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
- ; SI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[COPY]]
+ ; SI-NEXT: $vgpr0 = COPY [[FCEIL]](f32)
;
- ; CI-LABEL: name: test_fceil_s32
+ ; CI-LABEL: name: test_fceil_f32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
- ; CI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[COPY]]
+ ; CI-NEXT: $vgpr0 = COPY [[FCEIL]](f32)
;
- ; VI-LABEL: name: test_fceil_s32
+ ; VI-LABEL: name: test_fceil_f32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
- ; VI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[COPY]]
+ ; VI-NEXT: $vgpr0 = COPY [[FCEIL]](f32)
;
- ; GFX9-LABEL: name: test_fceil_s32
+ ; GFX9-LABEL: name: test_fceil_f32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCEIL %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[COPY]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FCEIL]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCEIL %0
$vgpr0 = COPY %1
...
---
-name: test_fceil_s64
+name: test_fceil_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; SI-LABEL: name: test_fceil_s64
+ ; SI-LABEL: name: test_fceil_f64
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -130,186 +132,186 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
; SI-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; SI-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s64), [[C8]]
- ; SI-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[BITCAST1]]
+ ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](f64), [[C8]]
+ ; SI-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](f64), [[BITCAST1]]
; SI-NEXT: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[BITCAST1]], [[SELECT2]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[SELECT2]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](f64)
;
- ; CI-LABEL: name: test_fceil_s64
+ ; CI-LABEL: name: test_fceil_f64
; CI: liveins: $vgpr0_vgpr1
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
- ; CI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[COPY]]
+ ; CI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](f64)
;
- ; VI-LABEL: name: test_fceil_s64
+ ; VI-LABEL: name: test_fceil_f64
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[COPY]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](f64)
;
- ; GFX9-LABEL: name: test_fceil_s64
+ ; GFX9-LABEL: name: test_fceil_f64
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FCEIL %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[COPY]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_FCEIL %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_fceil_v2s16
+name: test_fceil_v2f16
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_fceil_v2s16
+ ; SI-LABEL: name: test_fceil_v2f16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL1]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FCEIL1:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL1]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; CI-LABEL: name: test_fceil_v2s16
+ ; CI-LABEL: name: test_fceil_v2f16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; CI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; CI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; CI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; CI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
- ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
- ; CI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; CI-NEXT: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT1]]
- ; CI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL1]](s32)
- ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; CI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; CI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT]]
+ ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL]](f32)
+ ; CI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; CI-NEXT: [[FCEIL1:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT1]]
+ ; CI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL1]](f32)
+ ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; CI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; CI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; CI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; CI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; CI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; VI-LABEL: name: test_fceil_v2s16
+ ; VI-LABEL: name: test_fceil_v2f16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[B...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213353
More information about the llvm-commits
mailing list