[llvm] AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs (part 4) (PR #213353)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 31 13:49:56 PDT 2026
https://github.com/vangthao95 created https://github.com/llvm/llvm-project/pull/213353
Migrate G_FFREXP, G_FMODF, rounding operations, and the LOG/EXP families to extended LLTs.
Remove f64 for G_FLOG and G_FLOG10 since there is no custom lowering for them. Adjust G_AND masking for LOG/EXP using extended LLTs.
Update the relevant MIR tests and *.ll tests.
>From 996191ca9b95b019e9f6f012556f36f44c012bb0 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Fri, 31 Jul 2026 15:57:59 -0400
Subject: [PATCH] AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs
(part 4)
Migrate G_FFREXP, G_FMODF, rounding operations, and the LOG/EXP
families to extended LLTs.
Remove f64 for G_FLOG and G_FLOG10 since there is no custom lowering
for them. Adjust G_AND masking for LOG/EXP using extended LLTs.
Update the relevant MIR tests and *.ll tests.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 85 +-
.../AMDGPU/GlobalISel/legalize-fceil.mir | 394 ++--
.../AMDGPU/GlobalISel/legalize-fexp.mir | 1453 +++++++-----
.../AMDGPU/GlobalISel/legalize-fexp2.mir | 418 ++--
.../AMDGPU/GlobalISel/legalize-flog.mir | 324 +--
.../AMDGPU/GlobalISel/legalize-flog10.mir | 324 +--
.../AMDGPU/GlobalISel/legalize-flog2.mir | 104 +-
.../GlobalISel/legalize-intrinsic-round.mir | 1991 +++++++++--------
.../GlobalISel/legalize-intrinsic-trunc.mir | 382 ++--
llvm/test/CodeGen/AMDGPU/llvm.exp.ll | 1620 +++++++++-----
llvm/test/CodeGen/AMDGPU/llvm.exp10.ll | 1620 +++++++++-----
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 1152 ++++++----
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 1152 ++++++----
13 files changed, 6741 insertions(+), 4278 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 6bf05f9808d78..a7dd7cda693a2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -739,7 +739,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
const std::initializer_list<LLT> FPTypesPK16_64 = {S32, S64, S16, V2S16,
V2S64};
- const LLT MinScalarFPTy = ST.has16BitInsts() ? S16 : S32;
const LLT MinExtendedFPTy = ST.has16BitInsts() ? F16 : F32;
const LLT I1 = LLT::integer(1);
const LLT I16 = LLT::integer(16);
@@ -1104,12 +1103,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
getActionDefinitionsBuilder(G_FFREXP)
- .customFor({{S32, S32}, {S64, S32}, {S16, S16}, {S16, S32}})
- .scalarize(0)
- .lower();
+ .customFor({{F32, I32}, {F64, I32}, {F16, I16}, {F16, I32}})
+ .scalarize(0)
+ .lower();
getActionDefinitionsBuilder(G_FMODF)
- .lowerFor({S16, S32, S64})
+ .lowerFor({F16, F32, F64})
.scalarize(0)
.lower();
} else {
@@ -1140,14 +1139,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
getActionDefinitionsBuilder(G_FFREXP)
- .customFor({{S32, S32}, {S64, S32}})
- .scalarize(0)
- .minScalar(0, S32)
- .clampScalar(1, S32, S32)
- .lower();
+ .customFor({{F32, I32}, {F64, I32}})
+ .scalarize(0)
+ .minScalar(0, F32)
+ .clampScalar(1, I32, I32)
+ .lower();
getActionDefinitionsBuilder(G_FMODF)
- .lowerFor({S32, S64})
+ .lowerFor({F32, F64})
.scalarize(0)
.lower();
}
@@ -1292,26 +1291,18 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.scalarize(0)
.lower();
- if (ST.has16BitInsts()) {
- getActionDefinitionsBuilder(
- {G_INTRINSIC_TRUNC, G_FCEIL, G_INTRINSIC_ROUNDEVEN})
- .legalFor({S16, S32, S64})
- .clampScalar(0, S16, S64)
- .scalarize(0);
- } else if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
- getActionDefinitionsBuilder(
- {G_INTRINSIC_TRUNC, G_FCEIL, G_INTRINSIC_ROUNDEVEN})
- .legalFor({S32, S64})
- .clampScalar(0, S32, S64)
- .scalarize(0);
- } else {
- getActionDefinitionsBuilder(
- {G_INTRINSIC_TRUNC, G_FCEIL, G_INTRINSIC_ROUNDEVEN})
- .legalFor({S32})
- .customFor({S64})
- .clampScalar(0, S32, S64)
- .scalarize(0);
- }
+ auto &RoundingActions = getActionDefinitionsBuilder(
+ {G_INTRINSIC_TRUNC, G_FCEIL, G_INTRINSIC_ROUNDEVEN});
+ if (ST.has16BitInsts())
+ RoundingActions.legalFor({F16, F32, F64});
+ else if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
+ RoundingActions.legalFor({F32, F64});
+ else
+ RoundingActions.legalFor({F32}).customFor({F64});
+
+ RoundingActions.scalarize(0);
+ if (!ST.has16BitInsts())
+ RoundingActions.minScalar(0, F32);
getActionDefinitionsBuilder(G_PTR_ADD)
.unsupportedFor({BufferFatPtr, BufferStridedPtr, RsrcPtr})
@@ -1375,22 +1366,24 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
getActionDefinitionsBuilder(G_FLOG2)
- .legalFor(ST.has16BitInsts(), {S16})
- .customFor({S32, S16})
+ .legalFor(ST.has16BitInsts(), {F16})
+ .customFor({F32, F16})
.scalarize(0)
.lower();
getActionDefinitionsBuilder(G_FEXP2)
- .legalFor(ST.has16BitInsts(), {S16})
- .customFor({S32, S64, S16})
+ .legalFor(ST.has16BitInsts(), {F16})
+ .customFor({F32, F64, F16})
.scalarize(0)
.lower();
- auto &LogOps =
- getActionDefinitionsBuilder({G_FLOG, G_FLOG10, G_FEXP, G_FEXP10});
- LogOps.customFor({S32, S16, S64});
- LogOps.clampScalar(0, MinScalarFPTy, S32)
- .scalarize(0);
+ getActionDefinitionsBuilder({G_FLOG, G_FLOG10})
+ .customFor({F16, F32})
+ .scalarize(0);
+
+ getActionDefinitionsBuilder({G_FEXP, G_FEXP10})
+ .customFor({F16, F32, F64})
+ .scalarize(0);
// The 64-bit versions produce 32-bit results, but only on the SALU.
getActionDefinitionsBuilder(G_CTPOP)
@@ -3802,8 +3795,10 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI,
auto CH = B.buildFConstant(Ty, IsLog10 ? ch_log10 : ch_log);
auto CT = B.buildFConstant(Ty, IsLog10 ? ct_log10 : ct_log);
- auto MaskConst = B.buildConstant(Ty, 0xfffff000);
- auto YH = B.buildAnd(Ty, Y, MaskConst);
+ const LLT I32 = LLT::integer(32);
+ auto YInt = B.buildBitcast(I32, Y);
+ auto MaskConst = B.buildConstant(I32, 0xfffff000);
+ auto YH = B.buildBitcast(Ty, B.buildAnd(I32, YInt, MaskConst));
auto YT = B.buildFSub(Ty, Y, YH, Flags);
// This adds correction terms for which contraction may lead to an increase
// in the error of the approximation, so disable it.
@@ -4236,8 +4231,10 @@ bool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI,
const float ch_exp10 = 0x1.a92000p+1f;
const float cl_exp10 = 0x1.4f0978p-11f;
- auto MaskConst = B.buildConstant(Ty, 0xfffff000);
- auto XH = B.buildAnd(Ty, X, MaskConst);
+ const LLT I32 = LLT::integer(32);
+ auto XInt = B.buildBitcast(I32, X);
+ auto MaskConst = B.buildConstant(I32, 0xfffff000);
+ auto XH = B.buildBitcast(Ty, B.buildAnd(I32, XInt, MaskConst));
auto XL = B.buildFSub(Ty, X, XH, Flags);
auto CH = B.buildFConstant(Ty, IsExp10 ? ch_exp10 : ch_exp);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
index 826132d6e9010..70e9a4ff7a77c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
@@ -7,106 +7,108 @@
# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GFX9 %s
---
-name: test_fceil_s16
+name: test_fceil_f16
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_fceil_s16
+ ; SI-LABEL: name: test_fceil_f16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; CI-LABEL: name: test_fceil_s16
+ ; CI-LABEL: name: test_fceil_f16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
- ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
- ; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; CI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT]]
+ ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL]](f32)
+ ; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; CI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; VI-LABEL: name: test_fceil_s16
+ ; VI-LABEL: name: test_fceil_f16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f16) = G_FCEIL [[TRUNC]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FCEIL]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_fceil_s16
+ ; GFX9-LABEL: name: test_fceil_f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FCEIL %1
- %3:_(s32) = G_ANYEXT %2
- $vgpr0 = COPY %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f16) = G_FCEIL [[TRUNC]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FCEIL]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i16) = G_TRUNC %0
+ %2:_(f16) = G_BITCAST %1
+ %3:_(f16) = G_FCEIL %2
+ %4:_(i16) = G_BITCAST %3
+ %5:_(i32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
...
---
-name: test_fceil_s32
+name: test_fceil_f32
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_fceil_s32
+ ; SI-LABEL: name: test_fceil_f32
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
- ; SI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[COPY]]
+ ; SI-NEXT: $vgpr0 = COPY [[FCEIL]](f32)
;
- ; CI-LABEL: name: test_fceil_s32
+ ; CI-LABEL: name: test_fceil_f32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
- ; CI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[COPY]]
+ ; CI-NEXT: $vgpr0 = COPY [[FCEIL]](f32)
;
- ; VI-LABEL: name: test_fceil_s32
+ ; VI-LABEL: name: test_fceil_f32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
- ; VI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[COPY]]
+ ; VI-NEXT: $vgpr0 = COPY [[FCEIL]](f32)
;
- ; GFX9-LABEL: name: test_fceil_s32
+ ; GFX9-LABEL: name: test_fceil_f32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCEIL %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[COPY]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FCEIL]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCEIL %0
$vgpr0 = COPY %1
...
---
-name: test_fceil_s64
+name: test_fceil_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; SI-LABEL: name: test_fceil_s64
+ ; SI-LABEL: name: test_fceil_f64
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -130,186 +132,186 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
; SI-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; SI-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s64), [[C8]]
- ; SI-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[BITCAST1]]
+ ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](f64), [[C8]]
+ ; SI-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](f64), [[BITCAST1]]
; SI-NEXT: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[BITCAST1]], [[SELECT2]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[SELECT2]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](f64)
;
- ; CI-LABEL: name: test_fceil_s64
+ ; CI-LABEL: name: test_fceil_f64
; CI: liveins: $vgpr0_vgpr1
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
- ; CI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[COPY]]
+ ; CI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](f64)
;
- ; VI-LABEL: name: test_fceil_s64
+ ; VI-LABEL: name: test_fceil_f64
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[COPY]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](f64)
;
- ; GFX9-LABEL: name: test_fceil_s64
+ ; GFX9-LABEL: name: test_fceil_f64
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FCEIL %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[COPY]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_FCEIL %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_fceil_v2s16
+name: test_fceil_v2f16
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_fceil_v2s16
+ ; SI-LABEL: name: test_fceil_v2f16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL1]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FCEIL1:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL1]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; CI-LABEL: name: test_fceil_v2s16
+ ; CI-LABEL: name: test_fceil_v2f16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; CI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; CI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; CI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; CI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
- ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
- ; CI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; CI-NEXT: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT1]]
- ; CI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL1]](s32)
- ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; CI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; CI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT]]
+ ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL]](f32)
+ ; CI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; CI-NEXT: [[FCEIL1:%[0-9]+]]:_(f32) = G_FCEIL [[FPEXT1]]
+ ; CI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FCEIL1]](f32)
+ ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; CI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; CI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; CI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; CI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; CI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; VI-LABEL: name: test_fceil_v2s16
+ ; VI-LABEL: name: test_fceil_v2f16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
- ; VI-NEXT: [[FCEIL1:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC1]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FCEIL]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FCEIL1]](s16)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f16) = G_FCEIL [[TRUNC]]
+ ; VI-NEXT: [[FCEIL1:%[0-9]+]]:_(f16) = G_FCEIL [[TRUNC1]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FCEIL]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FCEIL1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; GFX9-LABEL: name: test_fceil_v2s16
+ ; GFX9-LABEL: name: test_fceil_v2f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
- ; GFX9-NEXT: [[FCEIL1:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FCEIL]](s16), [[FCEIL1]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_FCEIL %0
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f16) = G_FCEIL [[TRUNC]]
+ ; GFX9-NEXT: [[FCEIL1:%[0-9]+]]:_(f16) = G_FCEIL [[TRUNC1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FCEIL]](f16), [[FCEIL1]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_FCEIL %0
$vgpr0 = COPY %1
...
---
-name: test_fceil_v2s32
+name: test_fceil_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; SI-LABEL: name: test_fceil_v2s32
+ ; SI-LABEL: name: test_fceil_v2f32
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
- ; SI-NEXT: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[UV]]
+ ; SI-NEXT: [[FCEIL1:%[0-9]+]]:_(f32) = G_FCEIL [[UV1]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FCEIL]](f32), [[FCEIL1]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; CI-LABEL: name: test_fceil_v2s32
+ ; CI-LABEL: name: test_fceil_v2f32
; CI: liveins: $vgpr0_vgpr1
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
- ; CI-NEXT: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
- ; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
- ; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; CI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[UV]]
+ ; CI-NEXT: [[FCEIL1:%[0-9]+]]:_(f32) = G_FCEIL [[UV1]]
+ ; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FCEIL]](f32), [[FCEIL1]](f32)
+ ; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; VI-LABEL: name: test_fceil_v2s32
+ ; VI-LABEL: name: test_fceil_v2f32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
- ; VI-NEXT: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[UV]]
+ ; VI-NEXT: [[FCEIL1:%[0-9]+]]:_(f32) = G_FCEIL [[UV1]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FCEIL]](f32), [[FCEIL1]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_fceil_v2s32
+ ; GFX9-LABEL: name: test_fceil_v2f32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
- ; GFX9-NEXT: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FCEIL %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f32) = G_FCEIL [[UV]]
+ ; GFX9-NEXT: [[FCEIL1:%[0-9]+]]:_(f32) = G_FCEIL [[UV1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FCEIL]](f32), [[FCEIL1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_FCEIL %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_fceil_v2s64
+name: test_fceil_v2f64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-LABEL: name: test_fceil_v2s64
+ ; SI-LABEL: name: test_fceil_v2f64
; SI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](f64)
; SI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -333,12 +335,12 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
; SI-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
; SI-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s64), [[C8]]
- ; SI-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s64), [[BITCAST1]]
+ ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](f64), [[C8]]
+ ; SI-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](f64), [[BITCAST1]]
; SI-NEXT: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[BITCAST1]], [[SELECT2]]
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](s64)
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[SELECT2]]
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
; SI-NEXT: [[INT1:%[0-9]+]]:_(i32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](i32), [[C]](i32), [[C1]](i32)
; SI-NEXT: [[SUB1:%[0-9]+]]:_(i32) = G_SUB [[INT1]], [[C2]]
@@ -352,44 +354,44 @@ body: |
; SI-NEXT: [[SELECT3:%[0-9]+]]:_(i64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND4]]
; SI-NEXT: [[SELECT4:%[0-9]+]]:_(i64) = G_SELECT [[ICMP3]](s1), [[BITCAST2]], [[SELECT3]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT4]](i64)
- ; SI-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s64), [[C8]]
- ; SI-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s64), [[BITCAST3]]
+ ; SI-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](f64), [[C8]]
+ ; SI-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](f64), [[BITCAST3]]
; SI-NEXT: [[AND5:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
; SI-NEXT: [[SELECT5:%[0-9]+]]:_(f64) = G_SELECT [[AND5]](s1), [[C9]], [[C8]]
- ; SI-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[BITCAST3]], [[SELECT5]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[BITCAST3]], [[SELECT5]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FADD]](f64), [[FADD1]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
- ; CI-LABEL: name: test_fceil_v2s64
+ ; CI-LABEL: name: test_fceil_v2f64
; CI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
- ; CI-NEXT: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
- ; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
- ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[UV]]
+ ; CI-NEXT: [[FCEIL1:%[0-9]+]]:_(f64) = G_FCEIL [[UV1]]
+ ; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FCEIL]](f64), [[FCEIL1]](f64)
+ ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
- ; VI-LABEL: name: test_fceil_v2s64
+ ; VI-LABEL: name: test_fceil_v2f64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
- ; VI-NEXT: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[UV]]
+ ; VI-NEXT: [[FCEIL1:%[0-9]+]]:_(f64) = G_FCEIL [[UV1]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FCEIL]](f64), [[FCEIL1]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
- ; GFX9-LABEL: name: test_fceil_v2s64
+ ; GFX9-LABEL: name: test_fceil_v2f64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
- ; GFX9-NEXT: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = G_FCEIL %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX9-NEXT: [[FCEIL:%[0-9]+]]:_(f64) = G_FCEIL [[UV]]
+ ; GFX9-NEXT: [[FCEIL1:%[0-9]+]]:_(f64) = G_FCEIL [[UV1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FCEIL]](f64), [[FCEIL1]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = G_FCEIL %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
index 67ba424d49b93..c1dbb3cc03f2d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
@@ -6,663 +6,996 @@
# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
---
-name: test_fexp_s32
+name: test_fexp_f32
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_fexp_s32
+ ; GFX6-LABEL: name: test_fexp_f32
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
- ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[C]], [[FNEG]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
- ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[C1]], [[FMA]]
- ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FSUB]], [[FMA1]]
- ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C2]]
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C4]]
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX6-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL]]
+ ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[COPY]], [[C]], [[FNEG]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x32A5705F
+ ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[COPY]], [[C1]], [[FMA]]
+ ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FSUB]], [[FMA1]]
+ ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C2]]
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](f32), [[C4]]
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[COPY1]](f32)
;
- ; GFX8-LABEL: name: test_fexp_s32
+ ; GFX8-LABEL: name: test_fexp_f32
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4096
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[AND]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8A000
- ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x39A3B295
- ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C2]]
- ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[FMUL1]]
- ; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C2]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FADD]]
- ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FSUB1]], [[FADD1]]
- ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
- ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C3]]
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C5]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
- ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX8-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -4096
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C]]
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[COPY]], [[BITCAST1]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8A000
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST1]], [[C1]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x39A3B295
+ ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FSUB]], [[C2]]
+ ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FSUB]], [[C1]]
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[FMUL1]]
+ ; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST1]], [[C2]]
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[FADD]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FSUB1]], [[FADD1]]
+ ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C3]]
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](f32), [[C5]]
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX8-NEXT: $vgpr0 = COPY [[COPY1]](f32)
;
- ; GFX9-LABEL: name: test_fexp_s32
+ ; GFX9-LABEL: name: test_fexp_f32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
- ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[C]], [[FNEG]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
- ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[C1]], [[FMA]]
- ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FSUB]], [[FMA1]]
- ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C2]]
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C4]]
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FEXP %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL]]
+ ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[COPY]], [[C]], [[FNEG]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x32A5705F
+ ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[COPY]], [[C1]], [[FMA]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FSUB]], [[FMA1]]
+ ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C2]]
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](f32), [[C4]]
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FEXP %0
$vgpr0 = COPY %1
...
---
-name: test_fexp_s32_nnan
+name: test_fexp_f32_nnan
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_fexp_s32_nnan
+ ; GFX6-LABEL: name: test_fexp_f32_nnan
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL]]
- ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[COPY]], [[C]], [[FNEG]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
- ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[COPY]], [[C1]], [[FMA]]
- ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = nnan G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FSUB]], [[FMA1]]
- ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C2]]
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C4]]
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX6-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[C]]
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[FMUL]]
+ ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[COPY]], [[C]], [[FNEG]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x32A5705F
+ ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(f32) = nnan G_FMA [[COPY]], [[C1]], [[FMA]]
+ ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = nnan G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FSUB]], [[FMA1]]
+ ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C2]]
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](f32), [[C4]]
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[COPY1]](f32)
;
- ; GFX8-LABEL: name: test_fexp_s32_nnan
+ ; GFX8-LABEL: name: test_fexp_f32_nnan
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4096
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[COPY]], [[AND]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8A000
- ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[AND]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x39A3B295
- ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[FSUB]], [[C2]]
- ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = nnan G_FMUL [[FSUB]], [[C1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL2]], [[FMUL1]]
- ; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = nnan G_FMUL [[AND]], [[C2]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL3]], [[FADD]]
- ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = nnan G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = nnan G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s32) = nnan G_FADD [[FSUB1]], [[FADD1]]
- ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
- ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C3]]
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C5]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
- ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX8-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -4096
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C]]
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[COPY]], [[BITCAST1]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8A000
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[BITCAST1]], [[C1]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x39A3B295
+ ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[FSUB]], [[C2]]
+ ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = nnan G_FMUL [[FSUB]], [[C1]]
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL2]], [[FMUL1]]
+ ; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = nnan G_FMUL [[BITCAST1]], [[C2]]
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL3]], [[FADD]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = nnan G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = nnan G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(f32) = nnan G_FADD [[FSUB1]], [[FADD1]]
+ ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C3]]
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](f32), [[C5]]
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX8-NEXT: $vgpr0 = COPY [[COPY1]](f32)
;
- ; GFX9-LABEL: name: test_fexp_s32_nnan
+ ; GFX9-LABEL: name: test_fexp_f32_nnan
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL]]
- ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[COPY]], [[C]], [[FNEG]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
- ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[COPY]], [[C1]], [[FMA]]
- ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = nnan G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FSUB]], [[FMA1]]
- ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C2]]
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C4]]
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = nnan G_FEXP %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[FMUL]]
+ ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[COPY]], [[C]], [[FNEG]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x32A5705F
+ ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f32) = nnan G_FMA [[COPY]], [[C1]], [[FMA]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = nnan G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FSUB]], [[FMA1]]
+ ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = nnan G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C2]]
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](f32), [[C4]]
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = nnan G_FEXP %0
$vgpr0 = COPY %1
...
---
-name: test_fexp_v2s32
+name: test_fexp_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GFX6-LABEL: name: test_fexp_v2s32
+ ; GFX6-LABEL: name: test_fexp_v2f32
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
- ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C]], [[FNEG]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
- ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C1]], [[FMA]]
- ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FSUB]], [[FMA1]]
- ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C2]]
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C4]]
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; GFX6-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[C]], [[FNEG1]]
- ; GFX6-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[C1]], [[FMA2]]
- ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL1]]
- ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[FMUL1]], [[INTRINSIC_ROUNDEVEN1]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FSUB1]], [[FMA3]]
- ; GFX6-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](s32)
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](s32)
- ; GFX6-NEXT: [[FLDEXP1:%[0-9]+]]:_(s32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
- ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C2]]
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[FLDEXP1]]
- ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s32), [[C4]]
- ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[C5]], [[SELECT2]]
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL]]
+ ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[UV]], [[C]], [[FNEG]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x32A5705F
+ ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[UV]], [[C1]], [[FMA]]
+ ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FSUB]], [[FMA1]]
+ ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C2]]
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](f32), [[C4]]
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; GFX6-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[UV1]], [[C]], [[FNEG1]]
+ ; GFX6-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[UV1]], [[C1]], [[FMA2]]
+ ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL1]]
+ ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[FMUL1]], [[INTRINSIC_ROUNDEVEN1]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FSUB1]], [[FMA3]]
+ ; GFX6-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX6-NEXT: [[FLDEXP1:%[0-9]+]]:_(f32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C2]]
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[FLDEXP1]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](f32), [[C4]]
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C5]], [[SELECT2]]
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT3]](f32)
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[COPY1]](f32), [[COPY2]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX8-LABEL: name: test_fexp_v2s32
+ ; GFX8-LABEL: name: test_fexp_v2f32
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4096
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[AND]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8A000
- ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x39A3B295
- ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C2]]
- ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[FMUL1]]
- ; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C2]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FADD]]
- ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FSUB1]], [[FADD1]]
- ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
- ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C3]]
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C5]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
- ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
- ; GFX8-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[AND1]]
- ; GFX8-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[AND1]], [[C1]]
- ; GFX8-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[FSUB2]], [[C2]]
- ; GFX8-NEXT: [[FMUL6:%[0-9]+]]:_(s32) = G_FMUL [[FSUB2]], [[C1]]
- ; GFX8-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FMUL6]], [[FMUL5]]
- ; GFX8-NEXT: [[FMUL7:%[0-9]+]]:_(s32) = G_FMUL [[AND1]], [[C2]]
- ; GFX8-NEXT: [[FADD4:%[0-9]+]]:_(s32) = G_FADD [[FMUL7]], [[FADD3]]
- ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL4]]
- ; GFX8-NEXT: [[FSUB3:%[0-9]+]]:_(s32) = G_FSUB [[FMUL4]], [[INTRINSIC_ROUNDEVEN1]]
- ; GFX8-NEXT: [[FADD5:%[0-9]+]]:_(s32) = G_FADD [[FSUB3]], [[FADD4]]
- ; GFX8-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](s32)
- ; GFX8-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD5]](s32)
- ; GFX8-NEXT: [[FLDEXP1:%[0-9]+]]:_(s32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
- ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C3]]
- ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C4]], [[FLDEXP1]]
- ; GFX8-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s32), [[C5]]
- ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[C6]], [[SELECT2]]
- ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
- ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX8-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -4096
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C]]
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[UV]], [[BITCAST1]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8A000
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST1]], [[C1]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x39A3B295
+ ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FSUB]], [[C2]]
+ ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FSUB]], [[C1]]
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[FMUL1]]
+ ; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST1]], [[C2]]
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[FADD]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FSUB1]], [[FADD1]]
+ ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C3]]
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](f32), [[C5]]
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C]]
+ ; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
+ ; GFX8-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[UV1]], [[BITCAST3]]
+ ; GFX8-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST3]], [[C1]]
+ ; GFX8-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FSUB2]], [[C2]]
+ ; GFX8-NEXT: [[FMUL6:%[0-9]+]]:_(f32) = G_FMUL [[FSUB2]], [[C1]]
+ ; GFX8-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FMUL6]], [[FMUL5]]
+ ; GFX8-NEXT: [[FMUL7:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST3]], [[C2]]
+ ; GFX8-NEXT: [[FADD4:%[0-9]+]]:_(f32) = G_FADD [[FMUL7]], [[FADD3]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL4]]
+ ; GFX8-NEXT: [[FSUB3:%[0-9]+]]:_(f32) = G_FSUB [[FMUL4]], [[INTRINSIC_ROUNDEVEN1]]
+ ; GFX8-NEXT: [[FADD5:%[0-9]+]]:_(f32) = G_FADD [[FSUB3]], [[FADD4]]
+ ; GFX8-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](f32)
+ ; GFX8-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD5]](f32)
+ ; GFX8-NEXT: [[FLDEXP1:%[0-9]+]]:_(f32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
+ ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C3]]
+ ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C4]], [[FLDEXP1]]
+ ; GFX8-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](f32), [[C5]]
+ ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C6]], [[SELECT2]]
+ ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT3]](f32)
+ ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[COPY1]](f32), [[COPY2]](f32)
+ ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_fexp_v2s32
+ ; GFX9-LABEL: name: test_fexp_v2f32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
- ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C]], [[FNEG]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
- ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C1]], [[FMA]]
- ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FSUB]], [[FMA1]]
- ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C2]]
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C4]]
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[C]], [[FNEG1]]
- ; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[C1]], [[FMA2]]
- ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL1]]
- ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[FMUL1]], [[INTRINSIC_ROUNDEVEN1]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FSUB1]], [[FMA3]]
- ; GFX9-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](s32)
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](s32)
- ; GFX9-NEXT: [[FLDEXP1:%[0-9]+]]:_(s32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
- ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C2]]
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[FLDEXP1]]
- ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s32), [[C4]]
- ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[C5]], [[SELECT2]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FEXP %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL]]
+ ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[UV]], [[C]], [[FNEG]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x32A5705F
+ ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[UV]], [[C1]], [[FMA]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FSUB]], [[FMA1]]
+ ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C2]]
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](f32), [[C4]]
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[UV1]], [[C]], [[FNEG1]]
+ ; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[UV1]], [[C1]], [[FMA2]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL1]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[FMUL1]], [[INTRINSIC_ROUNDEVEN1]]
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FSUB1]], [[FMA3]]
+ ; GFX9-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX9-NEXT: [[FLDEXP1:%[0-9]+]]:_(f32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C2]]
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[FLDEXP1]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](f32), [[C4]]
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C5]], [[SELECT2]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT3]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[COPY1]](f32), [[COPY2]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_FEXP %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_fexp_v3s32
+name: test_fexp_v3f32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
- ; GFX6-LABEL: name: test_fexp_v3s32
+ ; GFX6-LABEL: name: test_fexp_v3f32
; GFX6: liveins: $vgpr0_vgpr1_vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
- ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C]], [[FNEG]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
- ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C1]], [[FMA]]
- ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FSUB]], [[FMA1]]
- ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C2]]
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C4]]
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; GFX6-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[C]], [[FNEG1]]
- ; GFX6-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[C1]], [[FMA2]]
- ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL1]]
- ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[FMUL1]], [[INTRINSIC_ROUNDEVEN1]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FSUB1]], [[FMA3]]
- ; GFX6-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](s32)
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](s32)
- ; GFX6-NEXT: [[FLDEXP1:%[0-9]+]]:_(s32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
- ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C2]]
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[FLDEXP1]]
- ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s32), [[C4]]
- ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[C5]], [[SELECT2]]
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[C]]
- ; GFX6-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[FMUL2]]
- ; GFX6-NEXT: [[FMA4:%[0-9]+]]:_(s32) = G_FMA [[UV2]], [[C]], [[FNEG2]]
- ; GFX6-NEXT: [[FMA5:%[0-9]+]]:_(s32) = G_FMA [[UV2]], [[C1]], [[FMA4]]
- ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN2:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL2]]
- ; GFX6-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[FMUL2]], [[INTRINSIC_ROUNDEVEN2]]
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FSUB2]], [[FMA5]]
- ; GFX6-NEXT: [[FPTOSI2:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN2]](s32)
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
- ; GFX6-NEXT: [[FLDEXP2:%[0-9]+]]:_(s32) = G_FLDEXP [[INT2]], [[FPTOSI2]](i32)
- ; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C2]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP4]](s1), [[C3]], [[FLDEXP2]]
- ; GFX6-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV2]](s32), [[C4]]
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP5]](s1), [[C5]], [[SELECT4]]
- ; GFX6-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT5]](s32)
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL]]
+ ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[UV]], [[C]], [[FNEG]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x32A5705F
+ ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[UV]], [[C1]], [[FMA]]
+ ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FSUB]], [[FMA1]]
+ ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C2]]
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](f32), [[C4]]
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; GFX6-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[UV1]], [[C]], [[FNEG1]]
+ ; GFX6-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[UV1]], [[C1]], [[FMA2]]
+ ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL1]]
+ ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[FMUL1]], [[INTRINSIC_ROUNDEVEN1]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FSUB1]], [[FMA3]]
+ ; GFX6-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX6-NEXT: [[FLDEXP1:%[0-9]+]]:_(f32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C2]]
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[FLDEXP1]]
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](f32), [[C4]]
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C5]], [[SELECT2]]
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT3]](f32)
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C]]
+ ; GFX6-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FMUL2]]
+ ; GFX6-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[UV2]], [[C]], [[FNEG2]]
+ ; GFX6-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[UV2]], [[C1]], [[FMA4]]
+ ; GFX6-NEXT: [[INTRINSIC_ROUNDEVEN2:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL2]]
+ ; GFX6-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[FMUL2]], [[INTRINSIC_ROUNDEVEN2]]
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FSUB2]], [[FMA5]]
+ ; GFX6-NEXT: [[FPTOSI2:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN2]](f32)
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX6-NEXT: [[FLDEXP2:%[0-9]+]]:_(f32) = G_FLDEXP [[INT2]], [[FPTOSI2]](i32)
+ ; GFX6-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C2]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C3]], [[FLDEXP2]]
+ ; GFX6-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV2]](f32), [[C4]]
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C5]], [[SELECT4]]
+ ; GFX6-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY [[SELECT5]](f32)
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[COPY1]](f32), [[COPY2]](f32), [[COPY3]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
- ; GFX8-LABEL: name: test_fexp_v3s32
+ ; GFX8-LABEL: name: test_fexp_v3f32
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -4096
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[AND]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8A000
- ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x39A3B295
- ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C2]]
- ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FSUB]], [[C1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[FMUL1]]
- ; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[AND]], [[C2]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FADD]]
- ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FSUB1]], [[FADD1]]
- ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
- ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C3]]
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
- ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C5]]
- ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
- ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
- ; GFX8-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[AND1]]
- ; GFX8-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[AND1]], [[C1]]
- ; GFX8-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[FSUB2]], [[C2]]
- ; GFX8-NEXT: [[FMUL6:%[0-9]+]]:_(s32) = G_FMUL [[FSUB2]], [[C1]]
- ; GFX8-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FMUL6]], [[FMUL5]]
- ; GFX8-NEXT: [[FMUL7:%[0-9]+]]:_(s32) = G_FMUL [[AND1]], [[C2]]
- ; GFX8-NEXT: [[FADD4:%[0-9]+]]:_(s32) = G_FADD [[FMUL7]], [[FADD3]]
- ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL4]]
- ; GFX8-NEXT: [[FSUB3:%[0-9]+]]:_(s32) = G_FSUB [[FMUL4]], [[INTRINSIC_ROUNDEVEN1]]
- ; GFX8-NEXT: [[FADD5:%[0-9]+]]:_(s32) = G_FADD [[FSUB3]], [[FADD4]]
- ; GFX8-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](s32)
- ; GFX8-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD5]](s32)
- ; GFX8-NEXT: [[FLDEXP1:%[0-9]+]]:_(s32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
- ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C3]]
- ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C4]], [[FLDEXP1]]
- ; GFX8-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s32), [[C5]]
- ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[C6]], [[SELECT2]]
- ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
- ; GFX8-NEXT: [[FSUB4:%[0-9]+]]:_(s32) = G_FSUB [[UV2]], [[AND2]]
- ; GFX8-NEXT: [[FMUL8:%[0-9]+]]:_(s32) = G_FMUL [[AND2]], [[C1]]
- ; GFX8-NEXT: [[FMUL9:%[0-9]+]]:_(s32) = G_FMUL [[FSUB4]], [[C2]]
- ; GFX8-NEXT: [[FMUL10:%[0-9]+]]:_(s32) = G_FMUL [[FSUB4]], [[C1]]
- ; GFX8-NEXT: [[FADD6:%[0-9]+]]:_(s32) = G_FADD [[FMUL10]], [[FMUL9]]
- ; GFX8-NEXT: [[FMUL11:%[0-9]+]]:_(s32) = G_FMUL [[AND2]], [[C2]]
- ; GFX8-NEXT: [[FADD7:%[0-9]+]]:_(s32) = G_FADD [[FMUL11]], [[FADD6]]
- ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN2:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL8]]
- ; GFX8-NEXT: [[FSUB5:%[0-9]+]]:_(s32) = G_FSUB [[FMUL8]], [[INTRINSIC_ROUNDEVEN2]]
- ; GFX8-NEXT: [[FADD8:%[0-9]+]]:_(s32) = G_FADD [[FSUB5]], [[FADD7]]
- ; GFX8-NEXT: [[FPTOSI2:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN2]](s32)
- ; GFX8-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD8]](s32)
- ; GFX8-NEXT: [[FLDEXP2:%[0-9]+]]:_(s32) = G_FLDEXP [[INT2]], [[FPTOSI2]](i32)
- ; GFX8-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C3]]
- ; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP4]](s1), [[C4]], [[FLDEXP2]]
- ; GFX8-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV2]](s32), [[C5]]
- ; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP5]](s1), [[C6]], [[SELECT4]]
- ; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT5]](s32)
- ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
- ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX8-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -4096
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C]]
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[UV]], [[BITCAST1]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8A000
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST1]], [[C1]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x39A3B295
+ ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FSUB]], [[C2]]
+ ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FSUB]], [[C1]]
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[FMUL1]]
+ ; GFX8-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST1]], [[C2]]
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[FADD]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FSUB1]], [[FADD1]]
+ ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C3]]
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C4]], [[FLDEXP]]
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](f32), [[C5]]
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[SELECT]]
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST2]], [[C]]
+ ; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
+ ; GFX8-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[UV1]], [[BITCAST3]]
+ ; GFX8-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST3]], [[C1]]
+ ; GFX8-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FSUB2]], [[C2]]
+ ; GFX8-NEXT: [[FMUL6:%[0-9]+]]:_(f32) = G_FMUL [[FSUB2]], [[C1]]
+ ; GFX8-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FMUL6]], [[FMUL5]]
+ ; GFX8-NEXT: [[FMUL7:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST3]], [[C2]]
+ ; GFX8-NEXT: [[FADD4:%[0-9]+]]:_(f32) = G_FADD [[FMUL7]], [[FADD3]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL4]]
+ ; GFX8-NEXT: [[FSUB3:%[0-9]+]]:_(f32) = G_FSUB [[FMUL4]], [[INTRINSIC_ROUNDEVEN1]]
+ ; GFX8-NEXT: [[FADD5:%[0-9]+]]:_(f32) = G_FADD [[FSUB3]], [[FADD4]]
+ ; GFX8-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](f32)
+ ; GFX8-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD5]](f32)
+ ; GFX8-NEXT: [[FLDEXP1:%[0-9]+]]:_(f32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
+ ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C3]]
+ ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C4]], [[FLDEXP1]]
+ ; GFX8-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](f32), [[C5]]
+ ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C6]], [[SELECT2]]
+ ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT3]](f32)
+ ; GFX8-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](f32)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C]]
+ ; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
+ ; GFX8-NEXT: [[FSUB4:%[0-9]+]]:_(f32) = G_FSUB [[UV2]], [[BITCAST5]]
+ ; GFX8-NEXT: [[FMUL8:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST5]], [[C1]]
+ ; GFX8-NEXT: [[FMUL9:%[0-9]+]]:_(f32) = G_FMUL [[FSUB4]], [[C2]]
+ ; GFX8-NEXT: [[FMUL10:%[0-9]+]]:_(f32) = G_FMUL [[FSUB4]], [[C1]]
+ ; GFX8-NEXT: [[FADD6:%[0-9]+]]:_(f32) = G_FADD [[FMUL10]], [[FMUL9]]
+ ; GFX8-NEXT: [[FMUL11:%[0-9]+]]:_(f32) = G_FMUL [[BITCAST5]], [[C2]]
+ ; GFX8-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[FMUL11]], [[FADD6]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN2:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL8]]
+ ; GFX8-NEXT: [[FSUB5:%[0-9]+]]:_(f32) = G_FSUB [[FMUL8]], [[INTRINSIC_ROUNDEVEN2]]
+ ; GFX8-NEXT: [[FADD8:%[0-9]+]]:_(f32) = G_FADD [[FSUB5]], [[FADD7]]
+ ; GFX8-NEXT: [[FPTOSI2:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN2]](f32)
+ ; GFX8-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD8]](f32)
+ ; GFX8-NEXT: [[FLDEXP2:%[0-9]+]]:_(f32) = G_FLDEXP [[INT2]], [[FPTOSI2]](i32)
+ ; GFX8-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C3]]
+ ; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C4]], [[FLDEXP2]]
+ ; GFX8-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV2]](f32), [[C5]]
+ ; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C6]], [[SELECT4]]
+ ; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY [[SELECT5]](f32)
+ ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[COPY1]](f32), [[COPY2]](f32), [[COPY3]](f32)
+ ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
- ; GFX9-LABEL: name: test_fexp_v3s32
+ ; GFX9-LABEL: name: test_fexp_v3f32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]
- ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C]], [[FNEG]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x32A5705F
- ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV]], [[C1]], [[FMA]]
- ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FSUB]], [[FMA1]]
- ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](s32)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](s32)
- ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(s32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float f0xC2CE8ED0
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C2]]
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x42B17218
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s32), [[C4]]
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[C]], [[FNEG1]]
- ; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[C1]], [[FMA2]]
- ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL1]]
- ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[FMUL1]], [[INTRINSIC_ROUNDEVEN1]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FSUB1]], [[FMA3]]
- ; GFX9-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](s32)
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](s32)
- ; GFX9-NEXT: [[FLDEXP1:%[0-9]+]]:_(s32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
- ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C2]]
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[FLDEXP1]]
- ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s32), [[C4]]
- ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[C5]], [[SELECT2]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[C]]
- ; GFX9-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[FMUL2]]
- ; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(s32) = G_FMA [[UV2]], [[C]], [[FNEG2]]
- ; GFX9-NEXT: [[FMA5:%[0-9]+]]:_(s32) = G_FMA [[UV2]], [[C1]], [[FMA4]]
- ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN2:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FMUL2]]
- ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[FMUL2]], [[INTRINSIC_ROUNDEVEN2]]
- ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FSUB2]], [[FMA5]]
- ; GFX9-NEXT: [[FPTOSI2:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN2]](s32)
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](s32)
- ; GFX9-NEXT: [[FLDEXP2:%[0-9]+]]:_(s32) = G_FLDEXP [[INT2]], [[FPTOSI2]](i32)
- ; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C2]]
- ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP4]](s1), [[C3]], [[FLDEXP2]]
- ; GFX9-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV2]](s32), [[C4]]
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP5]](s1), [[C5]], [[SELECT4]]
- ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT5]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = G_FEXP %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL]]
+ ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[UV]], [[C]], [[FNEG]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x32A5705F
+ ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[UV]], [[C1]], [[FMA]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[FMUL]], [[INTRINSIC_ROUNDEVEN]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FSUB]], [[FMA1]]
+ ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f32)
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(f32) = G_FLDEXP [[INT]], [[FPTOSI]](i32)
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float f0xC2CE8ED0
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C2]]
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[FLDEXP]]
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x42B17218
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](f32), [[C4]]
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C5]], [[SELECT]]
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[UV1]], [[C]], [[FNEG1]]
+ ; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[UV1]], [[C1]], [[FMA2]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL1]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[FMUL1]], [[INTRINSIC_ROUNDEVEN1]]
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FSUB1]], [[FMA3]]
+ ; GFX9-NEXT: [[FPTOSI1:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN1]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX9-NEXT: [[FLDEXP1:%[0-9]+]]:_(f32) = G_FLDEXP [[INT1]], [[FPTOSI1]](i32)
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C2]]
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[FLDEXP1]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](f32), [[C4]]
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C5]], [[SELECT2]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT3]](f32)
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C]]
+ ; GFX9-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FMUL2]]
+ ; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[UV2]], [[C]], [[FNEG2]]
+ ; GFX9-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[UV2]], [[C1]], [[FMA4]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN2:%[0-9]+]]:_(f32) = G_INTRINSIC_ROUNDEVEN [[FMUL2]]
+ ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[FMUL2]], [[INTRINSIC_ROUNDEVEN2]]
+ ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FSUB2]], [[FMA5]]
+ ; GFX9-NEXT: [[FPTOSI2:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN2]](f32)
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX9-NEXT: [[FLDEXP2:%[0-9]+]]:_(f32) = G_FLDEXP [[INT2]], [[FPTOSI2]](i32)
+ ; GFX9-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C2]]
+ ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C3]], [[FLDEXP2]]
+ ; GFX9-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV2]](f32), [[C4]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[C5]], [[SELECT4]]
+ ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY [[SELECT5]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[COPY1]](f32), [[COPY2]](f32), [[COPY3]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = G_FEXP %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...
---
-name: test_fexp_s16
+name: test_fexp_f16
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_fexp_s16
+ ; GFX6-LABEL: name: test_fexp_f16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](f32)
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](f32)
- ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT]](f32)
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX8-LABEL: name: test_fexp_s16
+ ; GFX8-LABEL: name: test_fexp_f16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX8-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; GFX8-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](f32)
- ; GFX8-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](f32)
- ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
- ; GFX9-LABEL: name: test_fexp_s16
- ; GFX9: liveins: $vgpr0
- ; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](f32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](f32)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FEXP %1
- %3:_(s32) = G_ANYEXT %2
- $vgpr0 = COPY %3
+ ; GFX8-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT]](f32)
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i16) = G_TRUNC %0
+ %2:_(f16) = G_BITCAST %1
+ %3:_(f16) = G_FEXP %2
+ %4:_(i16) = G_BITCAST %3
+ %5:_(i32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
...
---
-name: test_fexp_v2s16
+name: test_fexp_v2f16
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_fexp_v2s16
+ ; GFX6-LABEL: name: test_fexp_v2f16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT %4(s16)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C1]]
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](f32)
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](f32)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT %5(s16)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT]](f32)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C1]]
; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL1]](f32)
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](f32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C1]](i32)
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; GFX8-LABEL: name: test_fexp_v2s16
+ ; GFX8-LABEL: name: test_fexp_v2f16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX8-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT %4(s16)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX8-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C1]]
; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](f32)
- ; GFX8-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](f32)
- ; GFX8-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT %5(s16)
- ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C]]
+ ; GFX8-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT]](f32)
+ ; GFX8-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C1]]
; GFX8-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL1]](f32)
- ; GFX8-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](f32)
- ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C1]](i32)
+ ; GFX8-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_FEXP %0
+ $vgpr0 = COPY %1
+...
+
+---
+name: test_fexp_f64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; GFX6-LABEL: name: test_fexp_f64
+ ; GFX6: liveins: $vgpr0_vgpr1
+ ; GFX6-NEXT: {{ $}}
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FF71547652B82FE
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x4330000000000000
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[C1]](f64)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[FMUL]](f64)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C3]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C2]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[FMUL]], [[BITCAST2]]
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[BITCAST2]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[FADD]], [[FNEG]]
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x432FFFFFFFFFFFFF
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f64) = G_FABS [[FMUL]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](f64), [[C4]]
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FADD1]]
+ ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[SELECT]]
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3C7ABC9E3B39803F
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE62E42FEFA39EF
+ ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[C6]], [[COPY]]
+ ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[C5]], [[FMA]]
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E5ADE156A5DCB37
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E928AF3FCA7AB0C
+ ; GFX6-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[C7]], [[C8]]
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EC71DEE623FDE64
+ ; GFX6-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[C9]]
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EFA01997C89E6B0
+ ; GFX6-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA3]], [[C10]]
+ ; GFX6-NEXT: [[C11:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F2A01A014761F6E
+ ; GFX6-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA4]], [[C11]]
+ ; GFX6-NEXT: [[C12:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F56C16C1852B7B0
+ ; GFX6-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA5]], [[C12]]
+ ; GFX6-NEXT: [[C13:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F81111111122322
+ ; GFX6-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA6]], [[C13]]
+ ; GFX6-NEXT: [[C14:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FA55555555502A1
+ ; GFX6-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA7]], [[C14]]
+ ; GFX6-NEXT: [[C15:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC5555555555511
+ ; GFX6-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA8]], [[C15]]
+ ; GFX6-NEXT: [[C16:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE000000000000B
+ ; GFX6-NEXT: [[FMA10:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA9]], [[C16]]
+ ; GFX6-NEXT: [[C17:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX6-NEXT: [[FMA11:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA10]], [[C17]]
+ ; GFX6-NEXT: [[FMA12:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA11]], [[C17]]
+ ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[SELECT]](f64)
+ ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(f64) = G_FLDEXP [[FMA12]], [[FPTOSI]](i32)
+ ; GFX6-NEXT: [[C18:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.024000e+03
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](f64), [[C18]]
+ ; GFX6-NEXT: [[C19:%[0-9]+]]:_(f64) = G_FCONSTANT double +inf
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](s1), [[FLDEXP]], [[C19]]
+ ; GFX6-NEXT: [[C20:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.075000e+03
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[COPY]](f64), [[C20]]
+ ; GFX6-NEXT: [[C21:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[FCMP2]](s1), [[SELECT1]], [[C21]]
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT2]](f64)
;
- ; GFX9-LABEL: name: test_fexp_v2s16
- ; GFX9: liveins: $vgpr0
+ ; GFX8-LABEL: name: test_fexp_f64
+ ; GFX8: liveins: $vgpr0_vgpr1
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FF71547652B82FE
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f64) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX8-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_ROUNDEVEN]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3C7ABC9E3B39803F
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE62E42FEFA39EF
+ ; GFX8-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[C2]], [[COPY]]
+ ; GFX8-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[C1]], [[FMA]]
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E5ADE156A5DCB37
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E928AF3FCA7AB0C
+ ; GFX8-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[C3]], [[C4]]
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EC71DEE623FDE64
+ ; GFX8-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[C5]]
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EFA01997C89E6B0
+ ; GFX8-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA3]], [[C6]]
+ ; GFX8-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F2A01A014761F6E
+ ; GFX8-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA4]], [[C7]]
+ ; GFX8-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F56C16C1852B7B0
+ ; GFX8-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA5]], [[C8]]
+ ; GFX8-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F81111111122322
+ ; GFX8-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA6]], [[C9]]
+ ; GFX8-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FA55555555502A1
+ ; GFX8-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA7]], [[C10]]
+ ; GFX8-NEXT: [[C11:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC5555555555511
+ ; GFX8-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA8]], [[C11]]
+ ; GFX8-NEXT: [[C12:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE000000000000B
+ ; GFX8-NEXT: [[FMA10:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA9]], [[C12]]
+ ; GFX8-NEXT: [[C13:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX8-NEXT: [[FMA11:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA10]], [[C13]]
+ ; GFX8-NEXT: [[FMA12:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA11]], [[C13]]
+ ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f64)
+ ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(f64) = G_FLDEXP [[FMA12]], [[FPTOSI]](i32)
+ ; GFX8-NEXT: [[C14:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.024000e+03
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](f64), [[C14]]
+ ; GFX8-NEXT: [[C15:%[0-9]+]]:_(f64) = G_FCONSTANT double +inf
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](s1), [[FLDEXP]], [[C15]]
+ ; GFX8-NEXT: [[C16:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.075000e+03
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[COPY]](f64), [[C16]]
+ ; GFX8-NEXT: [[C17:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](s1), [[SELECT]], [[C17]]
+ ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT1]](f64)
+ ;
+ ; GFX9-LABEL: name: test_fexp_f64
+ ; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT %4(s16)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3FB8AA3B
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL]](f32)
- ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](f32)
- ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT %5(s16)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FMUL1]](f32)
- ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](f32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_FEXP %1
- $vgpr0 = COPY %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FF71547652B82FE
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f64) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_ROUNDEVEN]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3C7ABC9E3B39803F
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE62E42FEFA39EF
+ ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[C2]], [[COPY]]
+ ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[C1]], [[FMA]]
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E5ADE156A5DCB37
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E928AF3FCA7AB0C
+ ; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[C3]], [[C4]]
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EC71DEE623FDE64
+ ; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[C5]]
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EFA01997C89E6B0
+ ; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA3]], [[C6]]
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F2A01A014761F6E
+ ; GFX9-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA4]], [[C7]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F56C16C1852B7B0
+ ; GFX9-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA5]], [[C8]]
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F81111111122322
+ ; GFX9-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA6]], [[C9]]
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FA55555555502A1
+ ; GFX9-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA7]], [[C10]]
+ ; GFX9-NEXT: [[C11:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC5555555555511
+ ; GFX9-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA8]], [[C11]]
+ ; GFX9-NEXT: [[C12:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE000000000000B
+ ; GFX9-NEXT: [[FMA10:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA9]], [[C12]]
+ ; GFX9-NEXT: [[C13:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX9-NEXT: [[FMA11:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA10]], [[C13]]
+ ; GFX9-NEXT: [[FMA12:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA11]], [[C13]]
+ ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f64)
+ ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(f64) = G_FLDEXP [[FMA12]], [[FPTOSI]](i32)
+ ; GFX9-NEXT: [[C14:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.024000e+03
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](f64), [[C14]]
+ ; GFX9-NEXT: [[C15:%[0-9]+]]:_(f64) = G_FCONSTANT double +inf
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](s1), [[FLDEXP]], [[C15]]
+ ; GFX9-NEXT: [[C16:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.075000e+03
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[COPY]](f64), [[C16]]
+ ; GFX9-NEXT: [[C17:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](s1), [[SELECT]], [[C17]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT1]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_FEXP %0
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_fexp10_f64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; GFX6-LABEL: name: test_fexp10_f64
+ ; GFX6: liveins: $vgpr0_vgpr1
+ ; GFX6-NEXT: {{ $}}
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x400A934F0979A371
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x4330000000000000
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[C1]](f64)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[FMUL]](f64)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C3]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C2]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[FMUL]], [[BITCAST2]]
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[BITCAST2]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[FADD]], [[FNEG]]
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x432FFFFFFFFFFFFF
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f64) = G_FABS [[FMUL]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](f64), [[C4]]
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FADD1]]
+ ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[SELECT]]
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xBC49DC1DA994FD21
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FD34413509F79FF
+ ; GFX6-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[C6]], [[COPY]]
+ ; GFX6-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[C5]], [[FMA]]
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x40026BB1BBB55516
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xBCAF48AD494EA3E9
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[FMA1]], [[C8]]
+ ; GFX6-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[C7]], [[FMUL1]]
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E5ADE156A5DCB37
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E928AF3FCA7AB0C
+ ; GFX6-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[C9]], [[C10]]
+ ; GFX6-NEXT: [[C11:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EC71DEE623FDE64
+ ; GFX6-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA3]], [[C11]]
+ ; GFX6-NEXT: [[C12:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EFA01997C89E6B0
+ ; GFX6-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA4]], [[C12]]
+ ; GFX6-NEXT: [[C13:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F2A01A014761F6E
+ ; GFX6-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA5]], [[C13]]
+ ; GFX6-NEXT: [[C14:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F56C16C1852B7B0
+ ; GFX6-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA6]], [[C14]]
+ ; GFX6-NEXT: [[C15:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F81111111122322
+ ; GFX6-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA7]], [[C15]]
+ ; GFX6-NEXT: [[C16:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FA55555555502A1
+ ; GFX6-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA8]], [[C16]]
+ ; GFX6-NEXT: [[C17:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC5555555555511
+ ; GFX6-NEXT: [[FMA10:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA9]], [[C17]]
+ ; GFX6-NEXT: [[C18:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE000000000000B
+ ; GFX6-NEXT: [[FMA11:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA10]], [[C18]]
+ ; GFX6-NEXT: [[C19:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX6-NEXT: [[FMA12:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA11]], [[C19]]
+ ; GFX6-NEXT: [[FMA13:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA12]], [[C19]]
+ ; GFX6-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[SELECT]](f64)
+ ; GFX6-NEXT: [[FLDEXP:%[0-9]+]]:_(f64) = G_FLDEXP [[FMA13]], [[FPTOSI]](i32)
+ ; GFX6-NEXT: [[C20:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.024000e+03
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](f64), [[C20]]
+ ; GFX6-NEXT: [[C21:%[0-9]+]]:_(f64) = G_FCONSTANT double +inf
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](s1), [[FLDEXP]], [[C21]]
+ ; GFX6-NEXT: [[C22:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.075000e+03
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[COPY]](f64), [[C22]]
+ ; GFX6-NEXT: [[C23:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[FCMP2]](s1), [[SELECT1]], [[C23]]
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT2]](f64)
+ ;
+ ; GFX8-LABEL: name: test_fexp10_f64
+ ; GFX8: liveins: $vgpr0_vgpr1
+ ; GFX8-NEXT: {{ $}}
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x400A934F0979A371
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX8-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f64) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX8-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_ROUNDEVEN]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xBC49DC1DA994FD21
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FD34413509F79FF
+ ; GFX8-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[C2]], [[COPY]]
+ ; GFX8-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[C1]], [[FMA]]
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x40026BB1BBB55516
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xBCAF48AD494EA3E9
+ ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[FMA1]], [[C4]]
+ ; GFX8-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[C3]], [[FMUL1]]
+ ; GFX8-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E5ADE156A5DCB37
+ ; GFX8-NEXT: [[C6:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E928AF3FCA7AB0C
+ ; GFX8-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[C5]], [[C6]]
+ ; GFX8-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EC71DEE623FDE64
+ ; GFX8-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA3]], [[C7]]
+ ; GFX8-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EFA01997C89E6B0
+ ; GFX8-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA4]], [[C8]]
+ ; GFX8-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F2A01A014761F6E
+ ; GFX8-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA5]], [[C9]]
+ ; GFX8-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F56C16C1852B7B0
+ ; GFX8-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA6]], [[C10]]
+ ; GFX8-NEXT: [[C11:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F81111111122322
+ ; GFX8-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA7]], [[C11]]
+ ; GFX8-NEXT: [[C12:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FA55555555502A1
+ ; GFX8-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA8]], [[C12]]
+ ; GFX8-NEXT: [[C13:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC5555555555511
+ ; GFX8-NEXT: [[FMA10:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA9]], [[C13]]
+ ; GFX8-NEXT: [[C14:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE000000000000B
+ ; GFX8-NEXT: [[FMA11:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA10]], [[C14]]
+ ; GFX8-NEXT: [[C15:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX8-NEXT: [[FMA12:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA11]], [[C15]]
+ ; GFX8-NEXT: [[FMA13:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA12]], [[C15]]
+ ; GFX8-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f64)
+ ; GFX8-NEXT: [[FLDEXP:%[0-9]+]]:_(f64) = G_FLDEXP [[FMA13]], [[FPTOSI]](i32)
+ ; GFX8-NEXT: [[C16:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.024000e+03
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](f64), [[C16]]
+ ; GFX8-NEXT: [[C17:%[0-9]+]]:_(f64) = G_FCONSTANT double +inf
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](s1), [[FLDEXP]], [[C17]]
+ ; GFX8-NEXT: [[C18:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.075000e+03
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[COPY]](f64), [[C18]]
+ ; GFX8-NEXT: [[C19:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](s1), [[SELECT]], [[C19]]
+ ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT1]](f64)
+ ;
+ ; GFX9-LABEL: name: test_fexp10_f64
+ ; GFX9: liveins: $vgpr0_vgpr1
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x400A934F0979A371
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(f64) = G_INTRINSIC_ROUNDEVEN [[FMUL]]
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_ROUNDEVEN]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xBC49DC1DA994FD21
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FD34413509F79FF
+ ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[C2]], [[COPY]]
+ ; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[C1]], [[FMA]]
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x40026BB1BBB55516
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f64) = G_FCONSTANT double f0xBCAF48AD494EA3E9
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[FMA1]], [[C4]]
+ ; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[C3]], [[FMUL1]]
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E5ADE156A5DCB37
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3E928AF3FCA7AB0C
+ ; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[C5]], [[C6]]
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EC71DEE623FDE64
+ ; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA3]], [[C7]]
+ ; GFX9-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3EFA01997C89E6B0
+ ; GFX9-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA4]], [[C8]]
+ ; GFX9-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F2A01A014761F6E
+ ; GFX9-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA5]], [[C9]]
+ ; GFX9-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F56C16C1852B7B0
+ ; GFX9-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA6]], [[C10]]
+ ; GFX9-NEXT: [[C11:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3F81111111122322
+ ; GFX9-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA7]], [[C11]]
+ ; GFX9-NEXT: [[C12:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FA55555555502A1
+ ; GFX9-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA8]], [[C12]]
+ ; GFX9-NEXT: [[C13:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC5555555555511
+ ; GFX9-NEXT: [[FMA10:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA9]], [[C13]]
+ ; GFX9-NEXT: [[C14:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FE000000000000B
+ ; GFX9-NEXT: [[FMA11:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA10]], [[C14]]
+ ; GFX9-NEXT: [[C15:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX9-NEXT: [[FMA12:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA11]], [[C15]]
+ ; GFX9-NEXT: [[FMA13:%[0-9]+]]:_(f64) = G_FMA [[FMA2]], [[FMA12]], [[C15]]
+ ; GFX9-NEXT: [[FPTOSI:%[0-9]+]]:_(i32) = G_FPTOSI [[INTRINSIC_ROUNDEVEN]](f64)
+ ; GFX9-NEXT: [[FLDEXP:%[0-9]+]]:_(f64) = G_FLDEXP [[FMA13]], [[FPTOSI]](i32)
+ ; GFX9-NEXT: [[C16:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.024000e+03
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](f64), [[C16]]
+ ; GFX9-NEXT: [[C17:%[0-9]+]]:_(f64) = G_FCONSTANT double +inf
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](s1), [[FLDEXP]], [[C17]]
+ ; GFX9-NEXT: [[C18:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.075000e+03
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[COPY]](f64), [[C18]]
+ ; GFX9-NEXT: [[C19:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](s1), [[SELECT]], [[C19]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT1]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_FEXP10 %0
+ $vgpr0_vgpr1 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
index 7fea8b2fd8f32..4094171b0a978 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
@@ -6,355 +6,357 @@
# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GFX9 %s
---
-name: test_fexp2_s32
+name: test_fexp2_f32
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_fexp2_s32
+ ; GFX6-LABEL: name: test_fexp2_f32
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[SELECT]]
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
- ; GFX8-LABEL: name: test_fexp2_s32
+ ; GFX8-LABEL: name: test_fexp2_f32
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[SELECT]]
- ; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX8-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX8-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
- ; GFX9-LABEL: name: test_fexp2_s32
+ ; GFX9-LABEL: name: test_fexp2_f32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[SELECT]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMUL]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FEXP2 %0
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMUL]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FEXP2 %0
$vgpr0 = COPY %1
...
---
-name: test_fexp2_v2s32
+name: test_fexp2_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GFX6-LABEL: name: test_fexp2_v2s32
+ ; GFX6-LABEL: name: test_fexp2_v2f32
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[SELECT]]
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[SELECT2]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[SELECT3]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[SELECT3]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMUL]](f32), [[FMUL1]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX8-LABEL: name: test_fexp2_v2s32
+ ; GFX8-LABEL: name: test_fexp2_v2f32
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX8-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[SELECT]]
- ; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[SELECT2]]
- ; GFX8-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX8-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
- ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[SELECT3]]
- ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
- ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[SELECT3]]
+ ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMUL]](f32), [[FMUL1]](f32)
+ ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_fexp2_v2s32
+ ; GFX9-LABEL: name: test_fexp2_v2f32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[SELECT]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[SELECT2]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[SELECT3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FEXP2 %0
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[SELECT3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMUL]](f32), [[FMUL1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_FEXP2 %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_fexp2_v3s32
+name: test_fexp2_v3f32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
- ; GFX6-LABEL: name: test_fexp2_v3s32
+ ; GFX6-LABEL: name: test_fexp2_v3f32
; GFX6: liveins: $vgpr0_vgpr1_vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[SELECT]]
- ; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[SELECT2]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[SELECT3]]
- ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[SELECT3]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C]]
; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[UV2]], [[SELECT4]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT5]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT5]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FMUL]](f32), [[FMUL1]](f32), [[FMUL2]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
- ; GFX8-LABEL: name: test_fexp2_v3s32
+ ; GFX8-LABEL: name: test_fexp2_v3f32
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX8-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[SELECT]]
- ; GFX8-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX8-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX8-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[SELECT2]]
- ; GFX8-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX8-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
- ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[SELECT3]]
- ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]]
+ ; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[SELECT3]]
+ ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C]]
; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[UV2]], [[SELECT4]]
- ; GFX8-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX8-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
- ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT5]]
- ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32)
- ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX8-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT5]]
+ ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FMUL]](f32), [[FMUL1]](f32), [[FMUL2]](f32)
+ ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
- ; GFX9-LABEL: name: test_fexp2_v3s32
+ ; GFX9-LABEL: name: test_fexp2_v3f32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[SELECT]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[SELECT1]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[SELECT2]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[SELECT3]]
- ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[SELECT3]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C]]
; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[UV2]], [[SELECT4]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD2]](f32)
; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT5]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = G_FEXP2 %0
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT5]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FMUL]](f32), [[FMUL1]](f32), [[FMUL2]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = G_FEXP2 %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...
---
-name: test_fexp2_s16
+name: test_fexp2_f16
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_fexp2_s16
+ ; GFX6-LABEL: name: test_fexp2_f16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FPEXT]](f32)
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](f32)
- ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT]](f32)
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX8-LABEL: name: test_fexp2_s16
+ ; GFX8-LABEL: name: test_fexp2_f16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[FEXP2_:%[0-9]+]]:_(s16) = G_FEXP2 [[TRUNC]]
- ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FEXP2_]](s16)
- ; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX8-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = G_FEXP2 [[TRUNC]]
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FEXP2_]](f16)
+ ; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_fexp2_s16
+ ; GFX9-LABEL: name: test_fexp2_f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s16) = G_FEXP2 [[TRUNC]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FEXP2_]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FEXP2 %1
- %3:_(s32) = G_ANYEXT %2
- $vgpr0 = COPY %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = G_FEXP2 [[TRUNC]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FEXP2_]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i16) = G_TRUNC %0
+ %2:_(f16) = G_BITCAST %1
+ %3:_(f16) = G_FEXP2 %2
+ %4:_(i16) = G_BITCAST %3
+ %5:_(i32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
...
---
-name: test_fexp2_v2s16
+name: test_fexp2_v2f16
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_fexp2_v2s16
+ ; GFX6-LABEL: name: test_fexp2_v2f16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; GFX6-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FPEXT]](f32)
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](f32)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT]](f32)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FPEXT1]](f32)
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](f32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; GFX8-LABEL: name: test_fexp2_v2s16
+ ; GFX8-LABEL: name: test_fexp2_v2f16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX8-NEXT: [[FEXP2_:%[0-9]+]]:_(s16) = G_FEXP2 [[TRUNC]]
- ; GFX8-NEXT: [[FEXP2_1:%[0-9]+]]:_(s16) = G_FEXP2 [[TRUNC1]]
- ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FEXP2_]](s16)
- ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FEXP2_1]](s16)
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX8-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = G_FEXP2 [[TRUNC]]
+ ; GFX8-NEXT: [[FEXP2_1:%[0-9]+]]:_(f16) = G_FEXP2 [[TRUNC1]]
+ ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FEXP2_]](f16)
+ ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FEXP2_1]](f16)
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; GFX9-LABEL: name: test_fexp2_v2s16
+ ; GFX9-LABEL: name: test_fexp2_v2f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s16) = G_FEXP2 [[TRUNC]]
- ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s16) = G_FEXP2 [[TRUNC1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FEXP2_]](s16), [[FEXP2_1]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_FEXP2 %0
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(f16) = G_FEXP2 [[TRUNC]]
+ ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(f16) = G_FEXP2 [[TRUNC1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FEXP2_]](f16), [[FEXP2_1]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_FEXP2 %0
$vgpr0 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
index c4e2431f4e2e5..9c5c243a76138 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
@@ -2,261 +2,263 @@
# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
---
-name: test_flog_s32
+name: test_flog_f32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog_s32
+ ; CHECK-LABEL: name: test_flog_f32
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317217
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3377D1CF
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
- ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x41B17218
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
- ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FLOG %0
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3F317217
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3377D1CF
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C3]]
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C3]], [[FNEG]]
+ ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C4]], [[FMA]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[FMA1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[INT]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x41B17218
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[SELECT1]], [[SELECT2]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FLOG %0
$vgpr0 = COPY %1
...
---
-name: test_flog_s32_flags
+name: test_flog_f32_flags
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog_s32_flags
+ ; CHECK-LABEL: name: test_flog_f32_flags
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317217
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3377D1CF
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[INT]], [[C3]]
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL1]]
- ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C3]], [[FNEG]]
- ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C4]], [[FMA]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x41B17218
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[SELECT1]], [[SELECT2]]
- ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = nnan G_FLOG %0
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3F317217
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3377D1CF
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT]], [[C3]]
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[FMUL1]]
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[INT]], [[C3]], [[FNEG]]
+ ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(f32) = nnan G_FMA [[INT]], [[C4]], [[FMA]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL1]], [[FMA1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[INT]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[FABS]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x41B17218
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[SELECT1]], [[SELECT2]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = nnan G_FLOG %0
$vgpr0 = COPY %1
...
---
-name: test_flog_v2s32
+name: test_flog_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_flog_v2s32
+ ; CHECK-LABEL: name: test_flog_v2f32
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317217
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3377D1CF
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
- ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x41B17218
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
- ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3F317217
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3377D1CF
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C3]]
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C3]], [[FNEG]]
+ ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C4]], [[FMA]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[FMA1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[INT]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x41B17218
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[SELECT1]], [[SELECT2]]
+ ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT3]]
- ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C3]]
- ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL3]]
- ; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
- ; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMA3]]
- ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[INT1]]
- ; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[SELECT4]], [[SELECT5]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FLOG %0
+ ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
+ ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[C3]]
+ ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FMUL3]]
+ ; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
+ ; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[FMA3]]
+ ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[INT1]]
+ ; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[SELECT4]], [[SELECT5]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FSUB]](f32), [[FSUB1]](f32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_FLOG %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_flog_v3s32
+name: test_flog_v3f32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
- ; CHECK-LABEL: name: test_flog_v3s32
+ ; CHECK-LABEL: name: test_flog_v3f32
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3F317217
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3377D1CF
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
- ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x41B17218
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
- ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3F317217
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3377D1CF
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C3]]
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C3]], [[FNEG]]
+ ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C4]], [[FMA]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[FMA1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[INT]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x41B17218
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[SELECT1]], [[SELECT2]]
+ ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT3]]
- ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C3]]
- ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL3]]
- ; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
- ; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMA3]]
- ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[INT1]]
- ; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[SELECT4]], [[SELECT5]]
- ; CHECK-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]]
+ ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
+ ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[C3]]
+ ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FMUL3]]
+ ; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
+ ; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[FMA3]]
+ ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[INT1]]
+ ; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[SELECT4]], [[SELECT5]]
+ ; CHECK-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C]]
; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[SELECT6]]
- ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](f32)
- ; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[C3]]
- ; CHECK-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[FMUL5]]
- ; CHECK-NEXT: [[FMA4:%[0-9]+]]:_(s32) = G_FMA [[INT2]], [[C3]], [[FNEG2]]
- ; CHECK-NEXT: [[FMA5:%[0-9]+]]:_(s32) = G_FMA [[INT2]], [[C4]], [[FMA4]]
- ; CHECK-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL5]], [[FMA5]]
- ; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[INT2]]
- ; CHECK-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[FCMP5]](s1), [[FADD2]], [[INT2]]
- ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[FCMP4]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[SELECT7]], [[SELECT8]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32), [[FSUB2]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = G_FLOG %0
+ ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](f32)
+ ; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[C3]]
+ ; CHECK-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FMUL5]]
+ ; CHECK-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[INT2]], [[C3]], [[FNEG2]]
+ ; CHECK-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[INT2]], [[C4]], [[FMA4]]
+ ; CHECK-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL5]], [[FMA5]]
+ ; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(f32) = G_FABS [[INT2]]
+ ; CHECK-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[FADD2]], [[INT2]]
+ ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[SELECT7]], [[SELECT8]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FSUB]](f32), [[FSUB1]](f32), [[FSUB2]](f32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = G_FLOG %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...
---
-name: test_flog_s16
+name: test_flog_f16
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog_s16
+ ; CHECK-LABEL: name: test_flog_f16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3F317218
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C]]
- ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](f32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FLOG %1
- %3:_(s32) = G_ANYEXT %2
- $vgpr0 = COPY %3
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i16) = G_TRUNC %0
+ %2:_(f16) = G_BITCAST %1
+ %3:_(f16) = G_FLOG %2
+ %4:_(i16) = G_BITCAST %3
+ %5:_(i32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
...
---
-name: test_flog_v2s16
+name: test_flog_v2f16
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog_v2s16
+ ; CHECK-LABEL: name: test_flog_v2f16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3F317218
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C1]]
- ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](f32)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT1]](f32)
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[C1]]
- ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](f32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL1]](f32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_FLOG %0
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_FLOG %0
$vgpr0 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
index f156ca856ec9b..bd5a8fea2b6c2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
@@ -2,261 +2,263 @@
# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
---
-name: test_flog10_s32
+name: test_flog10_f32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog10_s32
+ ; CHECK-LABEL: name: test_flog10_f32
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E9A209A
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3284FBCF
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
- ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.632960e+00
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
- ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FLOG10 %0
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E9A209A
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3284FBCF
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C3]]
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C3]], [[FNEG]]
+ ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C4]], [[FMA]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[FMA1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[INT]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float 9.632960e+00
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[SELECT1]], [[SELECT2]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FLOG10 %0
$vgpr0 = COPY %1
...
---
-name: test_flog10_s32_flags
+name: test_flog10_f32_flags
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog10_s32_flags
+ ; CHECK-LABEL: name: test_flog10_f32_flags
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E9A209A
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3284FBCF
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[INT]], [[C3]]
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan G_FNEG [[FMUL1]]
- ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C3]], [[FNEG]]
- ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = nnan G_FMA [[INT]], [[C4]], [[FMA]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.632960e+00
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = nnan G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[SELECT1]], [[SELECT2]]
- ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = nnan G_FLOG10 %0
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E9A209A
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3284FBCF
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[INT]], [[C3]]
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[FMUL1]]
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[INT]], [[C3]], [[FNEG]]
+ ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(f32) = nnan G_FMA [[INT]], [[C4]], [[FMA]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL1]], [[FMA1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[INT]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(olt), [[FABS]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float 9.632960e+00
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = nnan G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nnan G_FSUB [[SELECT1]], [[SELECT2]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = nnan G_FLOG10 %0
$vgpr0 = COPY %1
...
---
-name: test_flog10_v2s32
+name: test_flog10_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_flog10_v2s32
+ ; CHECK-LABEL: name: test_flog10_v2f32
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E9A209A
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3284FBCF
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
- ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.632960e+00
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
- ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E9A209A
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3284FBCF
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C3]]
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C3]], [[FNEG]]
+ ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C4]], [[FMA]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[FMA1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[INT]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float 9.632960e+00
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[SELECT1]], [[SELECT2]]
+ ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT3]]
- ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C3]]
- ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL3]]
- ; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
- ; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMA3]]
- ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[INT1]]
- ; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[SELECT4]], [[SELECT5]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FLOG10 %0
+ ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
+ ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[C3]]
+ ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FMUL3]]
+ ; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
+ ; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[FMA3]]
+ ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[INT1]]
+ ; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[SELECT4]], [[SELECT5]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FSUB]](f32), [[FSUB1]](f32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_FLOG10 %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_flog10_v3s32
+name: test_flog10_v3f32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
- ; CHECK-LABEL: name: test_flog10_v3s32
+ ; CHECK-LABEL: name: test_flog10_v3f32
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E9A209A
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3284FBCF
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT]], [[C3]]
- ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL1]]
- ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C3]], [[FNEG]]
- ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[INT]], [[C4]], [[FMA]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[FMA1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float +inf
- ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INT]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.632960e+00
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[SELECT1]], [[SELECT2]]
- ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E9A209A
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3284FBCF
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C3]]
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FMUL1]]
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C3]], [[FNEG]]
+ ; CHECK-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[INT]], [[C4]], [[FMA]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[FMA1]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float +inf
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[INT]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[FADD]], [[INT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float 9.632960e+00
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[SELECT1]], [[SELECT2]]
+ ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT3]]
- ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INT1]], [[C3]]
- ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL3]]
- ; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
- ; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[FMA3]]
- ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[INT1]]
- ; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[SELECT4]], [[SELECT5]]
- ; CHECK-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]]
+ ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
+ ; CHECK-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[C3]]
+ ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FMUL3]]
+ ; CHECK-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[INT1]], [[C3]], [[FNEG1]]
+ ; CHECK-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[INT1]], [[C4]], [[FMA2]]
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[FMA3]]
+ ; CHECK-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[INT1]]
+ ; CHECK-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS1]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[FADD1]], [[INT1]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[SELECT4]], [[SELECT5]]
+ ; CHECK-NEXT: [[FCMP4:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C]]
; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[SELECT6]]
- ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](f32)
- ; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[C3]]
- ; CHECK-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[FMUL5]]
- ; CHECK-NEXT: [[FMA4:%[0-9]+]]:_(s32) = G_FMA [[INT2]], [[C3]], [[FNEG2]]
- ; CHECK-NEXT: [[FMA5:%[0-9]+]]:_(s32) = G_FMA [[INT2]], [[C4]], [[FMA4]]
- ; CHECK-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL5]], [[FMA5]]
- ; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[INT2]]
- ; CHECK-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](s32), [[C5]]
- ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[FCMP5]](s1), [[FADD2]], [[INT2]]
- ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[FCMP4]](s1), [[C7]], [[C6]]
- ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[SELECT7]], [[SELECT8]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32), [[FSUB2]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = G_FLOG10 %0
+ ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL4]](f32)
+ ; CHECK-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[C3]]
+ ; CHECK-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FMUL5]]
+ ; CHECK-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[INT2]], [[C3]], [[FNEG2]]
+ ; CHECK-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[INT2]], [[C4]], [[FMA4]]
+ ; CHECK-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL5]], [[FMA5]]
+ ; CHECK-NEXT: [[FABS2:%[0-9]+]]:_(f32) = G_FABS [[INT2]]
+ ; CHECK-NEXT: [[FCMP5:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[FABS2]](f32), [[C5]]
+ ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP5]](s1), [[FADD2]], [[INT2]]
+ ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(f32) = G_SELECT [[FCMP4]](s1), [[C7]], [[C6]]
+ ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[SELECT7]], [[SELECT8]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FSUB]](f32), [[FSUB1]](f32), [[FSUB2]](f32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = G_FLOG10 %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...
---
-name: test_flog10_s16
+name: test_flog10_f16
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog10_s16
+ ; CHECK-LABEL: name: test_flog10_f16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.010300e-01
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C]]
- ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](f32)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FLOG10 %1
- %3:_(s32) = G_ANYEXT %2
- $vgpr0 = COPY %3
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i16) = G_TRUNC %0
+ %2:_(f16) = G_BITCAST %1
+ %3:_(f16) = G_FLOG10 %2
+ %4:_(i16) = G_BITCAST %3
+ %5:_(i32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
...
---
-name: test_flog10_v2s16
+name: test_flog10_v2f16
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog10_v2s16
+ ; CHECK-LABEL: name: test_flog10_v2f16
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT]](f32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.010300e-01
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT]], [[C1]]
- ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](f32)
- ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
+ ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FPEXT1]](f32)
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT1]], [[C1]]
- ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](f32)
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL1]](f32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_FLOG10 %0
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_FLOG10 %0
$vgpr0 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
index 13bbf137d7764..be4018fe95997 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
@@ -2,104 +2,104 @@
# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
---
-name: test_flog2_s32
+name: test_flog2_f32
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: test_flog2_s32
+ ; CHECK-LABEL: name: test_flog2_f32
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
- ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FLOG2 %0
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FLOG2 %0
$vgpr0 = COPY %1
...
---
-name: test_flog2_v2s32
+name: test_flog2_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_flog2_v2s32
+ ; CHECK-LABEL: name: test_flog2_v2f32
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT2]]
- ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](f32)
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
- ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FLOG2 %0
+ ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](f32)
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+ ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT1]], [[SELECT3]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FSUB]](f32), [[FSUB1]](f32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_FLOG2 %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_flog2_v3s32
+name: test_flog2_v3f32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
- ; CHECK-LABEL: name: test_flog2_v3s32
+ ; CHECK-LABEL: name: test_flog2_v3f32
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[INT]], [[SELECT1]]
- ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; CHECK-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_FCONSTANT float 3.200000e+01
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
+ ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT2]]
- ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](f32)
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
- ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[INT1]], [[SELECT3]]
- ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](s32), [[C]]
+ ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL1]](f32)
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C3]], [[C4]]
+ ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT1]], [[SELECT3]]
+ ; CHECK-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV2]](f32), [[C]]
; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[SELECT4]]
- ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
- ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[INT2]], [[SELECT5]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32), [[FSUB2]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = G_FLOG2 %0
+ ; CHECK-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
+ ; CHECK-NEXT: [[FSUB2:%[0-9]+]]:_(f32) = G_FSUB [[INT2]], [[SELECT5]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FSUB]](f32), [[FSUB1]](f32), [[FSUB2]](f32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = G_FLOG2 %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
index 0d02fadcb4c53..3272a08aadb75 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
@@ -6,156 +6,174 @@
# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GFX9 %s
---
-name: test_intrinsic_round_s32
+name: test_intrinsic_round_f32
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_intrinsic_round_s32
+ ; GFX6-LABEL: name: test_intrinsic_round_f32
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FSUB]]
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C3]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](f32)
;
- ; GFX8-LABEL: name: test_intrinsic_round_s32
+ ; GFX8-LABEL: name: test_intrinsic_round_f32
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FSUB]]
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C3]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX8-NEXT: $vgpr0 = COPY [[FADD]](f32)
;
- ; GFX9-LABEL: name: test_intrinsic_round_s32
+ ; GFX9-LABEL: name: test_intrinsic_round_f32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FSUB]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C3]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_INTRINSIC_ROUND %0
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_INTRINSIC_ROUND %0
$vgpr0 = COPY %1
...
---
-name: test_intrinsic_round_s32_flags
+name: test_intrinsic_round_f32_flags
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_intrinsic_round_s32_flags
+ ; GFX6-LABEL: name: test_intrinsic_round_f32_flags
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = nsz G_INTRINSIC_TRUNC [[COPY]]
- ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[FSUB]]
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = nsz G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = nsz G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = nsz G_FABS [[FSUB]]
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = nsz G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C3]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](f32)
;
- ; GFX8-LABEL: name: test_intrinsic_round_s32_flags
+ ; GFX8-LABEL: name: test_intrinsic_round_f32_flags
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = nsz G_INTRINSIC_TRUNC [[COPY]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = nsz G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = nsz G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f32) = nsz G_FABS [[FSUB]]
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = nsz G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C3]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX8-NEXT: $vgpr0 = COPY [[FADD]](f32)
;
- ; GFX9-LABEL: name: test_intrinsic_round_s32_flags
+ ; GFX9-LABEL: name: test_intrinsic_round_f32_flags
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = nsz G_INTRINSIC_TRUNC [[COPY]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = nsz G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = nsz G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = nsz G_FSUB [[COPY]], [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = nsz G_FABS [[FSUB]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = nsz G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY]], [[C3]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = nsz G_INTRINSIC_ROUND %0
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = nsz G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = nsz G_INTRINSIC_ROUND %0
$vgpr0 = COPY %1
...
---
-name: test_intrinsic_round_s64
+name: test_intrinsic_round_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GFX6-LABEL: name: test_intrinsic_round_s64
+ ; GFX6-LABEL: name: test_intrinsic_round_f64
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; GFX6-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; GFX6-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -176,184 +194,211 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](i32), [[C7]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[ICMP1]](s1), [[BITCAST]], [[SELECT]]
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[SELECT1]](i64)
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[BITCAST1]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
- ; GFX6-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C8]]
- ; GFX6-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX6-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](i1), [[C9]], [[C10]]
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[BITCAST1]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[COPY]], [[FNEG]]
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f64) = G_FABS [[FADD]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double 5.000000e-01
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f64), [[C8]]
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[C9]], [[C10]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT2]](f64)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; GFX6-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; GFX6-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SELECT2]], [[C12]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C11]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[BITCAST1]], [[OR]]
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[FADD1]](s64)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[BITCAST2]], [[C12]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[BITCAST3]], [[C11]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[BITCAST4]]
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[FADD1]](f64)
;
- ; GFX8-LABEL: name: test_intrinsic_round_s64
+ ; GFX8-LABEL: name: test_intrinsic_round_f64
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX8-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX8-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[COPY]], [[FNEG]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f64) = G_FABS [[FADD]]
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f64), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT]](f64)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SELECT]], [[C4]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C3]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[FADD1]](s64)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C4]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[FADD1]](f64)
;
- ; GFX9-LABEL: name: test_intrinsic_round_s64
+ ; GFX9-LABEL: name: test_intrinsic_round_f64
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[COPY]], [[FNEG]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f64) = G_FABS [[FADD]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f64), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT]](f64)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SELECT]], [[C4]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[COPY]], [[C3]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FADD1]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_INTRINSIC_ROUND %0
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C4]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FADD1]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_INTRINSIC_ROUND %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_intrinsic_round_v2s32
+name: test_intrinsic_round_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GFX6-LABEL: name: test_intrinsic_round_v2s32
+ ; GFX6-LABEL: name: test_intrinsic_round_v2f32
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV]]
+ ; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FSUB]]
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX6-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[UV]], [[C3]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
- ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
- ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[FSUB1]]
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s32), [[C]]
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SELECT1]], [[C4]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[UV1]], [[C3]]
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
+ ; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[FSUB1]]
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f32), [[C]]
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT1]](f32)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C4]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C3]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC1]], [[BITCAST5]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX8-LABEL: name: test_intrinsic_round_v2s32
+ ; GFX8-LABEL: name: test_intrinsic_round_v2f32
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX8-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV]]
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FSUB]]
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[UV]], [[C3]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
- ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
- ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[FSUB1]]
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s32), [[C]]
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SELECT1]], [[C4]]
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[UV1]], [[C3]]
- ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
+ ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
+ ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[FSUB1]]
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f32), [[C]]
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT1]](f32)
+ ; GFX8-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C4]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C3]]
+ ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC1]], [[BITCAST5]]
+ ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_intrinsic_round_v2s32
+ ; GFX9-LABEL: name: test_intrinsic_round_v2f32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[UV]], [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f32) = G_FABS [[FSUB]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f32), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT]](f32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](f32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 -2147483648
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 2147483647
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[SELECT]], [[C4]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[UV]], [[C3]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
- ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
- ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[FSUB1]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s32), [[C]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[SELECT1]], [[C4]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[UV1]], [[C3]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_INTRINSIC_ROUND %0
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i32) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[OR]](i32)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[UV1]], [[INTRINSIC_TRUNC1]]
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f32) = G_FABS [[FSUB1]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f32), [[C]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[SELECT1]](f32)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](f32)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[BITCAST3]], [[C4]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[BITCAST4]], [[C3]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i32) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[OR1]](i32)
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INTRINSIC_TRUNC1]], [[BITCAST5]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_INTRINSIC_ROUND %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_intrinsic_round_v2s64
+name: test_intrinsic_round_v2f64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX6-LABEL: name: test_intrinsic_round_v2s64
+ ; GFX6-LABEL: name: test_intrinsic_round_v2f64
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](s64)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](f64)
; GFX6-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; GFX6-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -374,811 +419,981 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](i32), [[C7]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[ICMP1]](s1), [[BITCAST]], [[SELECT]]
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[SELECT1]](i64)
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[BITCAST1]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
- ; GFX6-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C8]]
- ; GFX6-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX6-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](i1), [[C9]], [[C10]]
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[BITCAST1]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[UV]], [[FNEG]]
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f64) = G_FABS [[FADD]]
+ ; GFX6-NEXT: [[C8:%[0-9]+]]:_(f64) = G_FCONSTANT double 5.000000e-01
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f64), [[C8]]
+ ; GFX6-NEXT: [[C9:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX6-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[C9]], [[C10]]
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT2]](f64)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](f64)
; GFX6-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; GFX6-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SELECT2]], [[C12]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C11]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[BITCAST1]], [[OR]]
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](s64)
- ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[BITCAST2]], [[C12]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[BITCAST3]], [[C11]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[BITCAST4]]
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
+ ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST5]](i64)
; GFX6-NEXT: [[INT1:%[0-9]+]]:_(i32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](i32), [[C]](i32), [[C1]](i32)
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(i32) = G_SUB [[INT1]], [[C2]]
; GFX6-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[UV5]], [[C3]]
; GFX6-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[C5]](i32), [[AND4]](i32)
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(i64) = G_ASHR [[C4]], [[SUB1]](i32)
; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(i64) = G_XOR [[ASHR1]], [[C6]]
- ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i64) = G_AND [[BITCAST2]], [[XOR1]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i64) = G_AND [[BITCAST5]], [[XOR1]]
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](i32), [[C5]]
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](i32), [[C7]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(i64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND5]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(i64) = G_SELECT [[ICMP3]](s1), [[BITCAST2]], [[SELECT3]]
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(s64) = G_BITCAST [[SELECT4]](i64)
- ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[BITCAST3]]
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FNEG1]]
- ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[FADD2]]
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s64), [[C8]]
- ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](i1), [[C9]], [[C10]]
- ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i64) = G_AND [[SELECT5]], [[C12]]
- ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C11]]
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND6]], [[AND7]]
- ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[BITCAST3]], [[OR1]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD1]](s64), [[FADD3]](s64)
- ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(i64) = G_SELECT [[ICMP3]](s1), [[BITCAST5]], [[SELECT3]]
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT4]](i64)
+ ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[BITCAST6]]
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f64) = G_FADD [[UV1]], [[FNEG1]]
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f64) = G_FABS [[FADD2]]
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f64), [[C8]]
+ ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](i1), [[C9]], [[C10]]
+ ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT5]](f64)
+ ; GFX6-NEXT: [[BITCAST8:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i64) = G_AND [[BITCAST7]], [[C12]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(i64) = G_AND [[BITCAST8]], [[C11]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND6]], [[AND7]]
+ ; GFX6-NEXT: [[BITCAST9:%[0-9]+]]:_(f64) = G_BITCAST [[OR1]](i64)
+ ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f64) = G_FADD [[BITCAST6]], [[BITCAST9]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FADD1]](f64), [[FADD3]](f64)
+ ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
- ; GFX8-LABEL: name: test_intrinsic_round_v2s64
+ ; GFX8-LABEL: name: test_intrinsic_round_v2f64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX8-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
- ; GFX8-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX8-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV]]
+ ; GFX8-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[UV]], [[FNEG]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f64) = G_FABS [[FADD]]
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f64), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT]](f64)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](f64)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SELECT]], [[C4]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C3]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
- ; GFX8-NEXT: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC1]]
- ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FNEG1]]
- ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[FADD2]]
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s64), [[C]]
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SELECT1]], [[C4]]
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C3]]
- ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX8-NEXT: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD1]](s64), [[FADD3]](s64)
- ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C4]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV1]]
+ ; GFX8-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_TRUNC1]]
+ ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(f64) = G_FADD [[UV1]], [[FNEG1]]
+ ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(f64) = G_FABS [[FADD2]]
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f64), [[C]]
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT1]](f64)
+ ; GFX8-NEXT: [[BITCAST4:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[BITCAST3]], [[C4]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[BITCAST4]], [[C3]]
+ ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(f64) = G_BITCAST [[OR1]](i64)
+ ; GFX8-NEXT: [[FADD3:%[0-9]+]]:_(f64) = G_FADD [[INTRINSIC_TRUNC1]], [[BITCAST5]]
+ ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FADD1]](f64), [[FADD3]](f64)
+ ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
- ; GFX9-LABEL: name: test_intrinsic_round_v2s64
+ ; GFX9-LABEL: name: test_intrinsic_round_v2f64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
- ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s64), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV]]
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[UV]], [[FNEG]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f64) = G_FABS [[FADD]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f64), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT]](f64)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](f64)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[SELECT]], [[C4]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[UV]], [[C3]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
- ; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC1]]
- ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FNEG1]]
- ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[FADD2]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s64), [[C]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[SELECT1]], [[C4]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[UV1]], [[C3]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s64) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX9-NEXT: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD1]](s64), [[FADD3]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C4]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i64) = G_AND [[BITCAST1]], [[C3]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64)
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[INTRINSIC_TRUNC]], [[BITCAST2]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV1]]
+ ; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[INTRINSIC_TRUNC1]]
+ ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(f64) = G_FADD [[UV1]], [[FNEG1]]
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f64) = G_FABS [[FADD2]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f64), [[C]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT1]](f64)
+ ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[BITCAST3]], [[C4]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[BITCAST4]], [[C3]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f64) = G_BITCAST [[OR1]](i64)
+ ; GFX9-NEXT: [[FADD3:%[0-9]+]]:_(f64) = G_FADD [[INTRINSIC_TRUNC1]], [[BITCAST5]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FADD1]](f64), [[FADD3]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = G_INTRINSIC_ROUND %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
---
-name: test_intrinsic_round_s16
+name: test_intrinsic_round_f16
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_intrinsic_round_s16
+ ; GFX6-LABEL: name: test_intrinsic_round_f16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
- ; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC]](f32)
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC]]
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT1]], [[FPEXT2]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC1]]
+ ; GFX6-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[FABS]](f16)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[C]](f16)
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT3]](f32), [[FPEXT4]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX6-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C4]]
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C3]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[OR]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C3]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FPEXT5]], [[FPEXT6]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT2]](i32)
;
- ; GFX8-LABEL: name: test_intrinsic_round_s16
+ ; GFX8-LABEL: name: test_intrinsic_round_f16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FSUB]]
+ ; GFX8-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f16), [[C]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX8-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C4]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C3]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C3]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX8-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC]], [[TRUNC3]]
+ ; GFX8-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT2]](i32)
;
- ; GFX9-LABEL: name: test_intrinsic_round_s16
+ ; GFX9-LABEL: name: test_intrinsic_round_f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FSUB]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f16), [[C]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C1]], [[C2]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](i32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C4]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C3]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_INTRINSIC_ROUND %1
- %3:_(s32) = G_ANYEXT %2
- $vgpr0 = COPY %3
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C3]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC]], [[TRUNC3]]
+ ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT2]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i16) = G_TRUNC %0
+ %2:_(f16) = G_BITCAST %1
+ %3:_(f16) = G_INTRINSIC_ROUND %2
+ %4:_(i16) = G_BITCAST %3
+ %5:_(i32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
...
---
-name: test_intrinsic_round_v2s16
+name: test_intrinsic_round_v2f16
body: |
bb.0:
liveins: $vgpr0
- ; GFX6-LABEL: name: test_intrinsic_round_v2s16
+ ; GFX6-LABEL: name: test_intrinsic_round_v2f16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC]](f32)
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC]]
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT1]], [[FPEXT2]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC1]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[FABS]](f16)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT3]](f32), [[FPEXT4]]
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX6-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[OR]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
- ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC3]]
- ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG1]](s16)
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT8]], [[FPEXT9]]
- ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
- ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC4]]
- ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[FABS1]](s16)
- ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT10]](s32), [[FPEXT11]]
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC3]](s16)
- ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[OR1]](s16)
- ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
- ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](s16)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C5]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C4]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FPEXT5]], [[FPEXT6]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](f32)
+ ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC3]]
+ ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG1]](f16)
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FPEXT8]], [[FPEXT9]]
+ ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD2]](f32)
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC4]]
+ ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(f32) = G_FPEXT [[FABS1]](f16)
+ ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT10]](f32), [[FPEXT11]]
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC5]], [[C5]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC6]], [[C4]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX6-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC3]](f16)
+ ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
+ ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FPEXT12]], [[FPEXT13]]
+ ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; GFX8-LABEL: name: test_intrinsic_round_v2s16
+ ; GFX8-LABEL: name: test_intrinsic_round_v2f16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FSUB]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f16), [[C1]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX8-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX8-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX8-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
- ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
- ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FSUB1]]
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C1]]
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](s16)
- ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](s16)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C5]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C4]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX8-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC]], [[TRUNC4]]
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
+ ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FSUB1]]
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f16), [[C1]]
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX8-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX8-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC5]], [[C5]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC6]], [[C4]]
+ ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX8-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX8-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC1]], [[TRUNC7]]
+ ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](f16)
+ ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](f16)
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX8-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
- ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](i32)
+ ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; GFX9-LABEL: name: test_intrinsic_round_v2s16
+ ; GFX9-LABEL: name: test_intrinsic_round_v2f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FSUB]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f16), [[C1]]
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
- ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
- ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FSUB1]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C1]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_INTRINSIC_ROUND %0
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C5]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C4]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC]], [[TRUNC4]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FSUB1]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f16), [[C1]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC5]], [[C5]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC6]], [[C4]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX9-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX9-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC1]], [[TRUNC7]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_INTRINSIC_ROUND %0
$vgpr0 = COPY %1
...
---
-name: test_intrinsic_round_v3s16
+name: test_intrinsic_round_v3f16
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
- ; GFX6-LABEL: name: test_intrinsic_round_v3s16
+ ; GFX6-LABEL: name: test_intrinsic_round_v3f16
; GFX6: liveins: $vgpr0_vgpr1_vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC]](f32)
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC]]
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT1]], [[FPEXT2]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC1]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[FABS]](f16)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT3]](f32), [[FPEXT4]]
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX6-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[OR]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
- ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC3]]
- ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG1]](s16)
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT8]], [[FPEXT9]]
- ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
- ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC4]]
- ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[FABS1]](s16)
- ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT10]](s32), [[FPEXT11]]
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC3]](s16)
- ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[OR1]](s16)
- ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
- ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
- ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT14]]
- ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](s32)
- ; GFX6-NEXT: [[FNEG2:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC6]]
- ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT16:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG2]](s16)
- ; GFX6-NEXT: [[FADD4:%[0-9]+]]:_(s32) = G_FADD [[FPEXT15]], [[FPEXT16]]
- ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD4]](s32)
- ; GFX6-NEXT: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC7]]
- ; GFX6-NEXT: [[FPEXT17:%[0-9]+]]:_(s32) = G_FPEXT [[FABS2]](s16)
- ; GFX6-NEXT: [[FPEXT18:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT17]](s32), [[FPEXT18]]
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[SELECT2]], [[C5]]
- ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C4]]
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[AND4]], [[AND5]]
- ; GFX6-NEXT: [[FPEXT19:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC6]](s16)
- ; GFX6-NEXT: [[FPEXT20:%[0-9]+]]:_(s32) = G_FPEXT [[OR2]](s16)
- ; GFX6-NEXT: [[FADD5:%[0-9]+]]:_(s32) = G_FADD [[FPEXT19]], [[FPEXT20]]
- ; GFX6-NEXT: [[FPTRUNC8:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD5]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](s16)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C5]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC4]], [[C4]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FPEXT5]], [[FPEXT6]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](f32)
+ ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC3]]
+ ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG1]](f16)
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FPEXT8]], [[FPEXT9]]
+ ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD2]](f32)
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC4]]
+ ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(f32) = G_FPEXT [[FABS1]](f16)
+ ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT10]](f32), [[FPEXT11]]
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC6]], [[C5]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC7]], [[C4]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX6-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX6-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC3]](f16)
+ ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC8]](f16)
+ ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FPEXT12]], [[FPEXT13]]
+ ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
+ ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT14]]
+ ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](f32)
+ ; GFX6-NEXT: [[FNEG2:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC6]]
+ ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT16:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG2]](f16)
+ ; GFX6-NEXT: [[FADD4:%[0-9]+]]:_(f32) = G_FADD [[FPEXT15]], [[FPEXT16]]
+ ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD4]](f32)
+ ; GFX6-NEXT: [[FABS2:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC7]]
+ ; GFX6-NEXT: [[FPEXT17:%[0-9]+]]:_(f32) = G_FPEXT [[FABS2]](f16)
+ ; GFX6-NEXT: [[FPEXT18:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT17]](f32), [[FPEXT18]]
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT2]](f16)
+ ; GFX6-NEXT: [[TRUNC9:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT4]](i32)
+ ; GFX6-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[TRUNC9]], [[C5]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC10]], [[C4]]
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(i16) = disjoint G_OR [[AND4]], [[AND5]]
+ ; GFX6-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[OR2]](i16)
+ ; GFX6-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT5]](i32)
+ ; GFX6-NEXT: [[FPEXT19:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC6]](f16)
+ ; GFX6-NEXT: [[FPEXT20:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC11]](f16)
+ ; GFX6-NEXT: [[FADD5:%[0-9]+]]:_(f32) = G_FADD [[FPEXT19]], [[FPEXT20]]
+ ; GFX6-NEXT: [[FPTRUNC8:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD5]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](i32)
- ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC8]](s16)
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR3]](i32)
+ ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC8]](f16)
; GFX6-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C6]], [[C]](i32)
; GFX6-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](i32)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR4]](i32)
; GFX6-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[C6]], [[SHL1]]
- ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](i32)
- ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
- ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR5]](i32)
+ ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x f16>), [[BITCAST3]](<2 x f16>), [[BITCAST4]](<2 x f16>)
+ ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
;
- ; GFX8-LABEL: name: test_intrinsic_round_v3s16
+ ; GFX8-LABEL: name: test_intrinsic_round_v3f16
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX8-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX8-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX8-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX8-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FSUB]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f16), [[C1]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX8-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX8-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX8-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
- ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
- ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FSUB1]]
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C1]]
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX8-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC2]]
- ; GFX8-NEXT: [[FSUB2:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC2]], [[INTRINSIC_TRUNC2]]
- ; GFX8-NEXT: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FSUB2]]
- ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS2]](s16), [[C1]]
- ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
- ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[SELECT2]], [[C5]]
- ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C4]]
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[AND4]], [[AND5]]
- ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[OR2]]
- ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](s16)
- ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](s16)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C5]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC4]], [[C4]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX8-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC]], [[TRUNC5]]
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
+ ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FSUB1]]
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f16), [[C1]]
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX8-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX8-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC6]], [[C5]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC7]], [[C4]]
+ ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX8-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX8-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC1]], [[TRUNC8]]
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC2]]
+ ; GFX8-NEXT: [[FSUB2:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC2]], [[INTRINSIC_TRUNC2]]
+ ; GFX8-NEXT: [[FABS2:%[0-9]+]]:_(f16) = G_FABS [[FSUB2]]
+ ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS2]](f16), [[C1]]
+ ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(f16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT2]](f16)
+ ; GFX8-NEXT: [[TRUNC9:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT4]](i32)
+ ; GFX8-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[TRUNC9]], [[C5]]
+ ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC10]], [[C4]]
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(i16) = disjoint G_OR [[AND4]], [[AND5]]
+ ; GFX8-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[OR2]](i16)
+ ; GFX8-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT5]](i32)
+ ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC2]], [[TRUNC11]]
+ ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](f16)
+ ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](f16)
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX8-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](i32)
- ; GFX8-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FADD2]](s16)
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR3]](i32)
+ ; GFX8-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FADD2]](f16)
; GFX8-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C6]], [[C]](i32)
; GFX8-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](i32)
+ ; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR4]](i32)
; GFX8-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[C6]], [[SHL1]]
- ; GFX8-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](i32)
- ; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
- ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
+ ; GFX8-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR5]](i32)
+ ; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x f16>), [[BITCAST3]](<2 x f16>), [[BITCAST4]](<2 x f16>)
+ ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
;
- ; GFX9-LABEL: name: test_intrinsic_round_v3s16
+ ; GFX9-LABEL: name: test_intrinsic_round_v3f16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FSUB]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f16), [[C1]]
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
- ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
- ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FSUB1]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C1]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC2]]
- ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC2]], [[INTRINSIC_TRUNC2]]
- ; GFX9-NEXT: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FSUB2]]
- ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS2]](s16), [[C1]]
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
- ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[SELECT2]], [[C5]]
- ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C4]]
- ; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[AND4]], [[AND5]]
- ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[OR2]]
- ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD2]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- %0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s16>), %2:_(<3 x s16>) = G_UNMERGE_VALUES %0
- %3:_(<3 x s16>) = G_INTRINSIC_ROUND %1
- %4:_(<3 x s16>) = G_IMPLICIT_DEF
- %5:_(<6 x s16>) = G_CONCAT_VECTORS %3, %4
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C5]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC4]], [[C4]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC]], [[TRUNC5]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FSUB1]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f16), [[C1]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX9-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC6]], [[C5]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC7]], [[C4]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX9-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX9-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC1]], [[TRUNC8]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC2]]
+ ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC2]], [[INTRINSIC_TRUNC2]]
+ ; GFX9-NEXT: [[FABS2:%[0-9]+]]:_(f16) = G_FABS [[FSUB2]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS2]](f16), [[C1]]
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT2]](f16)
+ ; GFX9-NEXT: [[TRUNC9:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT4]](i32)
+ ; GFX9-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[TRUNC9]], [[C5]]
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC10]], [[C4]]
+ ; GFX9-NEXT: [[OR2:%[0-9]+]]:_(i16) = disjoint G_OR [[AND4]], [[AND5]]
+ ; GFX9-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[OR2]](i16)
+ ; GFX9-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT5]](i32)
+ ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC2]], [[TRUNC11]]
+ ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD2]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[DEF]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>), [[BUILD_VECTOR2]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
+ %0:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f16>), %2:_(<3 x f16>) = G_UNMERGE_VALUES %0
+ %3:_(<3 x f16>) = G_INTRINSIC_ROUND %1
+ %4:_(<3 x f16>) = G_IMPLICIT_DEF
+ %5:_(<6 x f16>) = G_CONCAT_VECTORS %3, %4
$vgpr0_vgpr1_vgpr2 = COPY %5
...
---
-name: test_intrinsic_round_v4s16
+name: test_intrinsic_round_v4f16
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GFX6-LABEL: name: test_intrinsic_round_v4s16
+ ; GFX6-LABEL: name: test_intrinsic_round_v4f16
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
- ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT1]], [[FPEXT2]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC1]]
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[FABS]](s16)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT3]](s32), [[FPEXT4]]
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC]](f32)
+ ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC]]
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT1]], [[FPEXT2]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC1]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[FABS]](f16)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT3]](f32), [[FPEXT4]]
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX6-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[OR]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT5]], [[FPEXT6]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
- ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC3]]
- ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG1]](s16)
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT8]], [[FPEXT9]]
- ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
- ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC4]]
- ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[FABS1]](s16)
- ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT10]](s32), [[FPEXT11]]
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC3]](s16)
- ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[OR1]](s16)
- ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT12]], [[FPEXT13]]
- ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
- ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT14]]
- ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](s32)
- ; GFX6-NEXT: [[FNEG2:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC6]]
- ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT16:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG2]](s16)
- ; GFX6-NEXT: [[FADD4:%[0-9]+]]:_(s32) = G_FADD [[FPEXT15]], [[FPEXT16]]
- ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD4]](s32)
- ; GFX6-NEXT: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC7]]
- ; GFX6-NEXT: [[FPEXT17:%[0-9]+]]:_(s32) = G_FPEXT [[FABS2]](s16)
- ; GFX6-NEXT: [[FPEXT18:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT17]](s32), [[FPEXT18]]
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[SELECT2]], [[C5]]
- ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C4]]
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[AND4]], [[AND5]]
- ; GFX6-NEXT: [[FPEXT19:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC6]](s16)
- ; GFX6-NEXT: [[FPEXT20:%[0-9]+]]:_(s32) = G_FPEXT [[OR2]](s16)
- ; GFX6-NEXT: [[FADD5:%[0-9]+]]:_(s32) = G_FADD [[FPEXT19]], [[FPEXT20]]
- ; GFX6-NEXT: [[FPTRUNC8:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD5]](s32)
- ; GFX6-NEXT: [[FPEXT21:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT21]]
- ; GFX6-NEXT: [[FPTRUNC9:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC3]](s32)
- ; GFX6-NEXT: [[FNEG3:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC9]]
- ; GFX6-NEXT: [[FPEXT22:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; GFX6-NEXT: [[FPEXT23:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG3]](s16)
- ; GFX6-NEXT: [[FADD6:%[0-9]+]]:_(s32) = G_FADD [[FPEXT22]], [[FPEXT23]]
- ; GFX6-NEXT: [[FPTRUNC10:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD6]](s32)
- ; GFX6-NEXT: [[FABS3:%[0-9]+]]:_(s16) = G_FABS [[FPTRUNC10]]
- ; GFX6-NEXT: [[FPEXT24:%[0-9]+]]:_(s32) = G_FPEXT [[FABS3]](s16)
- ; GFX6-NEXT: [[FPEXT25:%[0-9]+]]:_(s32) = G_FPEXT [[C1]](s16)
- ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT24]](s32), [[FPEXT25]]
- ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[FCMP3]](i1), [[C2]], [[C3]]
- ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i16) = G_AND [[SELECT3]], [[C5]]
- ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C4]]
- ; GFX6-NEXT: [[OR3:%[0-9]+]]:_(s16) = disjoint G_OR [[AND6]], [[AND7]]
- ; GFX6-NEXT: [[FPEXT26:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC9]](s16)
- ; GFX6-NEXT: [[FPEXT27:%[0-9]+]]:_(s32) = G_FPEXT [[OR3]](s16)
- ; GFX6-NEXT: [[FADD7:%[0-9]+]]:_(s32) = G_FADD [[FPEXT26]], [[FPEXT27]]
- ; GFX6-NEXT: [[FPTRUNC11:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD7]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](s16)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC4]], [[C5]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC5]], [[C4]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX6-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FPEXT5]], [[FPEXT6]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](f32)
+ ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC3]]
+ ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG1]](f16)
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FPEXT8]], [[FPEXT9]]
+ ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD2]](f32)
+ ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC4]]
+ ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(f32) = G_FPEXT [[FABS1]](f16)
+ ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT10]](f32), [[FPEXT11]]
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX6-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC7]], [[C5]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC8]], [[C4]]
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX6-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX6-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC3]](f16)
+ ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC9]](f16)
+ ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FPEXT12]], [[FPEXT13]]
+ ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
+ ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT14]]
+ ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC2]](f32)
+ ; GFX6-NEXT: [[FNEG2:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC6]]
+ ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT16:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG2]](f16)
+ ; GFX6-NEXT: [[FADD4:%[0-9]+]]:_(f32) = G_FADD [[FPEXT15]], [[FPEXT16]]
+ ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD4]](f32)
+ ; GFX6-NEXT: [[FABS2:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC7]]
+ ; GFX6-NEXT: [[FPEXT17:%[0-9]+]]:_(f32) = G_FPEXT [[FABS2]](f16)
+ ; GFX6-NEXT: [[FPEXT18:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT17]](f32), [[FPEXT18]]
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT2]](f16)
+ ; GFX6-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT4]](i32)
+ ; GFX6-NEXT: [[TRUNC11:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[TRUNC10]], [[C5]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC11]], [[C4]]
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(i16) = disjoint G_OR [[AND4]], [[AND5]]
+ ; GFX6-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[OR2]](i16)
+ ; GFX6-NEXT: [[TRUNC12:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT5]](i32)
+ ; GFX6-NEXT: [[FPEXT19:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC6]](f16)
+ ; GFX6-NEXT: [[FPEXT20:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC12]](f16)
+ ; GFX6-NEXT: [[FADD5:%[0-9]+]]:_(f32) = G_FADD [[FPEXT19]], [[FPEXT20]]
+ ; GFX6-NEXT: [[FPTRUNC8:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD5]](f32)
+ ; GFX6-NEXT: [[FPEXT21:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT21]]
+ ; GFX6-NEXT: [[FPTRUNC9:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC3]](f32)
+ ; GFX6-NEXT: [[FNEG3:%[0-9]+]]:_(f16) = G_FNEG [[FPTRUNC9]]
+ ; GFX6-NEXT: [[FPEXT22:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[FPEXT23:%[0-9]+]]:_(f32) = G_FPEXT [[FNEG3]](f16)
+ ; GFX6-NEXT: [[FADD6:%[0-9]+]]:_(f32) = G_FADD [[FPEXT22]], [[FPEXT23]]
+ ; GFX6-NEXT: [[FPTRUNC10:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD6]](f32)
+ ; GFX6-NEXT: [[FABS3:%[0-9]+]]:_(f16) = G_FABS [[FPTRUNC10]]
+ ; GFX6-NEXT: [[FPEXT24:%[0-9]+]]:_(f32) = G_FPEXT [[FABS3]](f16)
+ ; GFX6-NEXT: [[FPEXT25:%[0-9]+]]:_(f32) = G_FPEXT [[C1]](f16)
+ ; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FPEXT24]](f32), [[FPEXT25]]
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f16) = G_SELECT [[FCMP3]](i1), [[C2]], [[C3]]
+ ; GFX6-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT3]](f16)
+ ; GFX6-NEXT: [[TRUNC13:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT6]](i32)
+ ; GFX6-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i16) = G_AND [[TRUNC13]], [[C5]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(i16) = G_AND [[TRUNC14]], [[C4]]
+ ; GFX6-NEXT: [[OR3:%[0-9]+]]:_(i16) = disjoint G_OR [[AND6]], [[AND7]]
+ ; GFX6-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[OR3]](i16)
+ ; GFX6-NEXT: [[TRUNC15:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT7]](i32)
+ ; GFX6-NEXT: [[FPEXT26:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC9]](f16)
+ ; GFX6-NEXT: [[FPEXT27:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC15]](f16)
+ ; GFX6-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[FPEXT26]], [[FPEXT27]]
+ ; GFX6-NEXT: [[FPTRUNC11:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](i32)
- ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC8]](s16)
- ; GFX6-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC11]](s16)
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR4]](i32)
+ ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC8]](f16)
+ ; GFX6-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC11]](f16)
; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; GFX6-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](i32)
- ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR5]](i32)
+ ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x f16>), [[BITCAST3]](<2 x f16>)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
- ; GFX8-LABEL: name: test_intrinsic_round_v4s16
+ ; GFX8-LABEL: name: test_intrinsic_round_v4f16
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
- ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX8-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX8-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX8-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX8-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX8-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
- ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX8-NEXT: [[FSUB:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
+ ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FSUB]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f16), [[C1]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX8-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX8-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX8-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX8-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX8-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
- ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
- ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FSUB1]]
- ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C1]]
- ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX8-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC2]]
- ; GFX8-NEXT: [[FSUB2:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC2]], [[INTRINSIC_TRUNC2]]
- ; GFX8-NEXT: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FSUB2]]
- ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS2]](s16), [[C1]]
- ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
- ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[SELECT2]], [[C5]]
- ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C4]]
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[AND4]], [[AND5]]
- ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[OR2]]
- ; GFX8-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC3]]
- ; GFX8-NEXT: [[FSUB3:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC3]], [[INTRINSIC_TRUNC3]]
- ; GFX8-NEXT: [[FABS3:%[0-9]+]]:_(s16) = G_FABS [[FSUB3]]
- ; GFX8-NEXT: [[FCMP3:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS3]](s16), [[C1]]
- ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[FCMP3]](i1), [[C2]], [[C3]]
- ; GFX8-NEXT: [[AND6:%[0-9]+]]:_(i16) = G_AND [[SELECT3]], [[C5]]
- ; GFX8-NEXT: [[AND7:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C4]]
- ; GFX8-NEXT: [[OR3:%[0-9]+]]:_(s16) = disjoint G_OR [[AND6]], [[AND7]]
- ; GFX8-NEXT: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC3]], [[OR3]]
- ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](s16)
- ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](s16)
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC4]], [[C5]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC5]], [[C4]]
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX8-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC]], [[TRUNC6]]
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; GFX8-NEXT: [[FSUB1:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
+ ; GFX8-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FSUB1]]
+ ; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f16), [[C1]]
+ ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX8-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX8-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC7]], [[C5]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC8]], [[C4]]
+ ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX8-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX8-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX8-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC1]], [[TRUNC9]]
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC2]]
+ ; GFX8-NEXT: [[FSUB2:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC2]], [[INTRINSIC_TRUNC2]]
+ ; GFX8-NEXT: [[FABS2:%[0-9]+]]:_(f16) = G_FABS [[FSUB2]]
+ ; GFX8-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS2]](f16), [[C1]]
+ ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(f16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT2]](f16)
+ ; GFX8-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT4]](i32)
+ ; GFX8-NEXT: [[TRUNC11:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[TRUNC10]], [[C5]]
+ ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC11]], [[C4]]
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(i16) = disjoint G_OR [[AND4]], [[AND5]]
+ ; GFX8-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[OR2]](i16)
+ ; GFX8-NEXT: [[TRUNC12:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT5]](i32)
+ ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC2]], [[TRUNC12]]
+ ; GFX8-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC3]]
+ ; GFX8-NEXT: [[FSUB3:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC3]], [[INTRINSIC_TRUNC3]]
+ ; GFX8-NEXT: [[FABS3:%[0-9]+]]:_(f16) = G_FABS [[FSUB3]]
+ ; GFX8-NEXT: [[FCMP3:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS3]](f16), [[C1]]
+ ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(f16) = G_SELECT [[FCMP3]](i1), [[C2]], [[C3]]
+ ; GFX8-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT3]](f16)
+ ; GFX8-NEXT: [[TRUNC13:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT6]](i32)
+ ; GFX8-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX8-NEXT: [[AND6:%[0-9]+]]:_(i16) = G_AND [[TRUNC13]], [[C5]]
+ ; GFX8-NEXT: [[AND7:%[0-9]+]]:_(i16) = G_AND [[TRUNC14]], [[C4]]
+ ; GFX8-NEXT: [[OR3:%[0-9]+]]:_(i16) = disjoint G_OR [[AND6]], [[AND7]]
+ ; GFX8-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[OR3]](i16)
+ ; GFX8-NEXT: [[TRUNC15:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT7]](i32)
+ ; GFX8-NEXT: [[FADD3:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC3]], [[TRUNC15]]
+ ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](f16)
+ ; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](f16)
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX8-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](i32)
- ; GFX8-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FADD2]](s16)
- ; GFX8-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FADD3]](s16)
+ ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR4]](i32)
+ ; GFX8-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FADD2]](f16)
+ ; GFX8-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FADD3]](f16)
; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; GFX8-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](i32)
- ; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR5]](i32)
+ ; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x f16>), [[BITCAST3]](<2 x f16>)
+ ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
- ; GFX9-LABEL: name: test_intrinsic_round_v4s16
+ ; GFX9-LABEL: name: test_intrinsic_round_v4f16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
- ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[FSUB]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 5.000000e-01
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](s16), [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC]], [[INTRINSIC_TRUNC]]
+ ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(f16) = G_FABS [[FSUB]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 5.000000e-01
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS]](f16), [[C1]]
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT]](f16)
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT]](i32)
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(i16) = G_CONSTANT i16 -32768
; GFX9-NEXT: [[C5:%[0-9]+]]:_(i16) = G_CONSTANT i16 32767
- ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[SELECT]], [[C5]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC]], [[C4]]
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = disjoint G_OR [[AND]], [[AND1]]
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC]], [[OR]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
- ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
- ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(s16) = G_FABS [[FSUB1]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](s16), [[C1]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[SELECT1]], [[C5]]
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s16) = disjoint G_OR [[AND2]], [[AND3]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC1]], [[OR1]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC2]]
- ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC2]], [[INTRINSIC_TRUNC2]]
- ; GFX9-NEXT: [[FABS2:%[0-9]+]]:_(s16) = G_FABS [[FSUB2]]
- ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS2]](s16), [[C1]]
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
- ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[SELECT2]], [[C5]]
- ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC2]], [[C4]]
- ; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s16) = disjoint G_OR [[AND4]], [[AND5]]
- ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC2]], [[OR2]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC3]]
- ; GFX9-NEXT: [[FSUB3:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC3]], [[INTRINSIC_TRUNC3]]
- ; GFX9-NEXT: [[FABS3:%[0-9]+]]:_(s16) = G_FABS [[FSUB3]]
- ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS3]](s16), [[C1]]
- ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[FCMP3]](i1), [[C2]], [[C3]]
- ; GFX9-NEXT: [[AND6:%[0-9]+]]:_(i16) = G_AND [[SELECT3]], [[C5]]
- ; GFX9-NEXT: [[AND7:%[0-9]+]]:_(i16) = G_AND [[TRUNC3]], [[C4]]
- ; GFX9-NEXT: [[OR3:%[0-9]+]]:_(s16) = disjoint G_OR [[AND6]], [[AND7]]
- ; GFX9-NEXT: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[INTRINSIC_TRUNC3]], [[OR3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD2]](s16), [[FADD3]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = G_INTRINSIC_ROUND %0
+ ; GFX9-NEXT: [[AND:%[0-9]+]]:_(i16) = G_AND [[TRUNC4]], [[C5]]
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(i16) = G_AND [[TRUNC5]], [[C4]]
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(i16) = disjoint G_OR [[AND]], [[AND1]]
+ ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[OR]](i16)
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT1]](i32)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC]], [[TRUNC6]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; GFX9-NEXT: [[FSUB1:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC1]], [[INTRINSIC_TRUNC1]]
+ ; GFX9-NEXT: [[FABS1:%[0-9]+]]:_(f16) = G_FABS [[FSUB1]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f16), [[C1]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT1]](f16)
+ ; GFX9-NEXT: [[TRUNC7:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT2]](i32)
+ ; GFX9-NEXT: [[TRUNC8:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(i16) = G_AND [[TRUNC7]], [[C5]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(i16) = G_AND [[TRUNC8]], [[C4]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(i16) = disjoint G_OR [[AND2]], [[AND3]]
+ ; GFX9-NEXT: [[ANYEXT3:%[0-9]+]]:_(i32) = G_ANYEXT [[OR1]](i16)
+ ; GFX9-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT3]](i32)
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC1]], [[TRUNC9]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC2:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC2]]
+ ; GFX9-NEXT: [[FSUB2:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC2]], [[INTRINSIC_TRUNC2]]
+ ; GFX9-NEXT: [[FABS2:%[0-9]+]]:_(f16) = G_FABS [[FSUB2]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS2]](f16), [[C1]]
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f16) = G_SELECT [[FCMP2]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT4:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT2]](f16)
+ ; GFX9-NEXT: [[TRUNC10:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT4]](i32)
+ ; GFX9-NEXT: [[TRUNC11:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(i16) = G_AND [[TRUNC10]], [[C5]]
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(i16) = G_AND [[TRUNC11]], [[C4]]
+ ; GFX9-NEXT: [[OR2:%[0-9]+]]:_(i16) = disjoint G_OR [[AND4]], [[AND5]]
+ ; GFX9-NEXT: [[ANYEXT5:%[0-9]+]]:_(i32) = G_ANYEXT [[OR2]](i16)
+ ; GFX9-NEXT: [[TRUNC12:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT5]](i32)
+ ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC2]], [[TRUNC12]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC3:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC3]]
+ ; GFX9-NEXT: [[FSUB3:%[0-9]+]]:_(f16) = G_FSUB [[TRUNC3]], [[INTRINSIC_TRUNC3]]
+ ; GFX9-NEXT: [[FABS3:%[0-9]+]]:_(f16) = G_FABS [[FSUB3]]
+ ; GFX9-NEXT: [[FCMP3:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS3]](f16), [[C1]]
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f16) = G_SELECT [[FCMP3]](i1), [[C2]], [[C3]]
+ ; GFX9-NEXT: [[ANYEXT6:%[0-9]+]]:_(i32) = G_ANYEXT [[SELECT3]](f16)
+ ; GFX9-NEXT: [[TRUNC13:%[0-9]+]]:_(i16) = G_TRUNC [[ANYEXT6]](i32)
+ ; GFX9-NEXT: [[TRUNC14:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX9-NEXT: [[AND6:%[0-9]+]]:_(i16) = G_AND [[TRUNC13]], [[C5]]
+ ; GFX9-NEXT: [[AND7:%[0-9]+]]:_(i16) = G_AND [[TRUNC14]], [[C4]]
+ ; GFX9-NEXT: [[OR3:%[0-9]+]]:_(i16) = disjoint G_OR [[AND6]], [[AND7]]
+ ; GFX9-NEXT: [[ANYEXT7:%[0-9]+]]:_(i32) = G_ANYEXT [[OR3]](i16)
+ ; GFX9-NEXT: [[TRUNC15:%[0-9]+]]:_(f16) = G_TRUNC [[ANYEXT7]](i32)
+ ; GFX9-NEXT: [[FADD3:%[0-9]+]]:_(f16) = G_FADD [[INTRINSIC_TRUNC3]], [[TRUNC15]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD2]](f16), [[FADD3]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = G_INTRINSIC_ROUND %0
$vgpr0_vgpr1 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
index 0219590946768..b50ae43334a1e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
@@ -7,106 +7,108 @@
# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GFX9 %s
---
-name: test_intrinsic_trunc_s16
+name: test_intrinsic_trunc_f16
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_intrinsic_trunc_s16
+ ; SI-LABEL: name: test_intrinsic_trunc_f16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; CI-LABEL: name: test_intrinsic_trunc_s16
+ ; CI-LABEL: name: test_intrinsic_trunc_f16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
- ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
- ; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; CI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC]](f32)
+ ; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; CI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; VI-LABEL: name: test_intrinsic_trunc_s16
+ ; VI-LABEL: name: test_intrinsic_trunc_f16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INTRINSIC_TRUNC]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INTRINSIC_TRUNC]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_intrinsic_trunc_s16
+ ; GFX9-LABEL: name: test_intrinsic_trunc_f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INTRINSIC_TRUNC]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_INTRINSIC_TRUNC %1
- %3:_(s32) = G_ANYEXT %2
- $vgpr0 = COPY %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INTRINSIC_TRUNC]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i16) = G_TRUNC %0
+ %2:_(f16) = G_BITCAST %1
+ %3:_(f16) = G_INTRINSIC_TRUNC %2
+ %4:_(i16) = G_BITCAST %3
+ %5:_(i32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
...
---
-name: test_intrinsic_trunc_s32
+name: test_intrinsic_trunc_f32
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_intrinsic_trunc_s32
+ ; SI-LABEL: name: test_intrinsic_trunc_f32
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; SI-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; SI-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](f32)
;
- ; CI-LABEL: name: test_intrinsic_trunc_s32
+ ; CI-LABEL: name: test_intrinsic_trunc_f32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; CI-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; CI-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](f32)
;
- ; VI-LABEL: name: test_intrinsic_trunc_s32
+ ; VI-LABEL: name: test_intrinsic_trunc_f32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; VI-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; VI-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](f32)
;
- ; GFX9-LABEL: name: test_intrinsic_trunc_s32
+ ; GFX9-LABEL: name: test_intrinsic_trunc_f32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX9-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_INTRINSIC_TRUNC %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_INTRINSIC_TRUNC %0
$vgpr0 = COPY %1
...
---
-name: test_intrinsic_trunc_s64
+name: test_intrinsic_trunc_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; SI-LABEL: name: test_intrinsic_trunc_s64
+ ; SI-LABEL: name: test_intrinsic_trunc_f64
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -127,182 +129,182 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](i32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[ICMP1]](s1), [[BITCAST]], [[SELECT]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[SELECT1]](i64)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST1]](s64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST1]](f64)
;
- ; CI-LABEL: name: test_intrinsic_trunc_s64
+ ; CI-LABEL: name: test_intrinsic_trunc_f64
; CI: liveins: $vgpr0_vgpr1
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
- ; CI-NEXT: $vgpr0_vgpr1 = COPY [[INTRINSIC_TRUNC]](s64)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[COPY]]
+ ; CI-NEXT: $vgpr0_vgpr1 = COPY [[INTRINSIC_TRUNC]](f64)
;
- ; VI-LABEL: name: test_intrinsic_trunc_s64
+ ; VI-LABEL: name: test_intrinsic_trunc_f64
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTRINSIC_TRUNC]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[COPY]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTRINSIC_TRUNC]](f64)
;
- ; GFX9-LABEL: name: test_intrinsic_trunc_s64
+ ; GFX9-LABEL: name: test_intrinsic_trunc_f64
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INTRINSIC_TRUNC]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_INTRINSIC_TRUNC %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INTRINSIC_TRUNC]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_INTRINSIC_TRUNC %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_intrinsic_trunc_v2s16
+name: test_intrinsic_trunc_v2f16
body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: test_intrinsic_trunc_v2s16
+ ; SI-LABEL: name: test_intrinsic_trunc_v2f16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; CI-LABEL: name: test_intrinsic_trunc_v2s16
+ ; CI-LABEL: name: test_intrinsic_trunc_v2f16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; CI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; CI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; CI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; CI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT]]
- ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC]](s32)
- ; CI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; CI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FPEXT1]]
- ; CI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](s32)
- ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; CI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; CI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; CI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT]]
+ ; CI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC]](f32)
+ ; CI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; CI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[FPEXT1]]
+ ; CI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INTRINSIC_TRUNC1]](f32)
+ ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; CI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; CI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; CI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; CI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; CI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; VI-LABEL: name: test_intrinsic_trunc_v2s16
+ ; VI-LABEL: name: test_intrinsic_trunc_v2f16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INTRINSIC_TRUNC]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INTRINSIC_TRUNC1]](s16)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INTRINSIC_TRUNC]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INTRINSIC_TRUNC1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
- ; GFX9-LABEL: name: test_intrinsic_trunc_v2s16
+ ; GFX9-LABEL: name: test_intrinsic_trunc_v2f16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s16) = G_INTRINSIC_TRUNC [[TRUNC1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s16), [[INTRINSIC_TRUNC1]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_INTRINSIC_TRUNC %0
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f16) = G_INTRINSIC_TRUNC [[TRUNC1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](f16), [[INTRINSIC_TRUNC1]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_INTRINSIC_TRUNC %0
$vgpr0 = COPY %1
...
---
-name: test_intrinsic_trunc_v2s32
+name: test_intrinsic_trunc_v2f32
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; SI-LABEL: name: test_intrinsic_trunc_v2s32
+ ; SI-LABEL: name: test_intrinsic_trunc_v2f32
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; SI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s32), [[INTRINSIC_TRUNC1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV]]
+ ; SI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](f32), [[INTRINSIC_TRUNC1]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; CI-LABEL: name: test_intrinsic_trunc_v2s32
+ ; CI-LABEL: name: test_intrinsic_trunc_v2f32
; CI: liveins: $vgpr0_vgpr1
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; CI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
- ; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s32), [[INTRINSIC_TRUNC1]](s32)
- ; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; CI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV]]
+ ; CI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
+ ; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](f32), [[INTRINSIC_TRUNC1]](f32)
+ ; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; VI-LABEL: name: test_intrinsic_trunc_v2s32
+ ; VI-LABEL: name: test_intrinsic_trunc_v2f32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s32), [[INTRINSIC_TRUNC1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV]]
+ ; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](f32), [[INTRINSIC_TRUNC1]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_intrinsic_trunc_v2s32
+ ; GFX9-LABEL: name: test_intrinsic_trunc_v2f32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[UV1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s32), [[INTRINSIC_TRUNC1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_INTRINSIC_TRUNC %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f32) = G_INTRINSIC_TRUNC [[UV1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](f32), [[INTRINSIC_TRUNC1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_INTRINSIC_TRUNC %0
$vgpr0_vgpr1 = COPY %1
...
---
-name: test_intrinsic_trunc_v2s64
+name: test_intrinsic_trunc_v2f64
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-LABEL: name: test_intrinsic_trunc_v2s64
+ ; SI-LABEL: name: test_intrinsic_trunc_v2f64
; SI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](f64)
; SI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
@@ -323,8 +325,8 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](i32), [[C7]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(i64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(i64) = G_SELECT [[ICMP1]](s1), [[BITCAST]], [[SELECT]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[SELECT1]](i64)
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](s64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT1]](i64)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
; SI-NEXT: [[INT1:%[0-9]+]]:_(i32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](i32), [[C]](i32), [[C1]](i32)
; SI-NEXT: [[SUB1:%[0-9]+]]:_(i32) = G_SUB [[INT1]], [[C2]]
@@ -337,40 +339,40 @@ body: |
; SI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](i32), [[C7]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(i64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND3]]
; SI-NEXT: [[SELECT3:%[0-9]+]]:_(i64) = G_SELECT [[ICMP3]](s1), [[BITCAST2]], [[SELECT2]]
- ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(s64) = G_BITCAST [[SELECT3]](i64)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[BITCAST1]](s64), [[BITCAST3]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT3]](i64)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[BITCAST1]](f64), [[BITCAST3]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
- ; CI-LABEL: name: test_intrinsic_trunc_v2s64
+ ; CI-LABEL: name: test_intrinsic_trunc_v2f64
; CI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CI-NEXT: {{ $}}
- ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
- ; CI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
- ; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s64), [[INTRINSIC_TRUNC1]](s64)
- ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; CI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; CI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV]]
+ ; CI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV1]]
+ ; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](f64), [[INTRINSIC_TRUNC1]](f64)
+ ; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
- ; VI-LABEL: name: test_intrinsic_trunc_v2s64
+ ; VI-LABEL: name: test_intrinsic_trunc_v2f64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
- ; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s64), [[INTRINSIC_TRUNC1]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; VI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV]]
+ ; VI-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV1]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](f64), [[INTRINSIC_TRUNC1]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
- ; GFX9-LABEL: name: test_intrinsic_trunc_v2s64
+ ; GFX9-LABEL: name: test_intrinsic_trunc_v2f64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
- ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](s64), [[INTRINSIC_TRUNC1]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = G_INTRINSIC_TRUNC %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV]]
+ ; GFX9-NEXT: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(f64) = G_INTRINSIC_TRUNC [[UV1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INTRINSIC_TRUNC]](f64), [[INTRINSIC_TRUNC1]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = G_INTRINSIC_TRUNC %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
index 51de1a3b434bc..a8559b404c646 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,VI,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GFX900,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -2624,31 +2624,57 @@ define amdgpu_kernel void @s_exp_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
}
define float @v_exp_f32(float %in) {
-; VI-LABEL: v_exp_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32:
; GFX900-SDAG: ; %bb.0:
@@ -2756,32 +2782,59 @@ define float @v_exp_f32(float %in) {
}
define float @v_exp_fabs_f32(float %in) {
-; VI-LABEL: v_exp_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
-; VI-NEXT: v_and_b32_e32 v1, 0x7ffff000, v1
-; VI-NEXT: v_sub_f32_e64 v4, |v0|, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7ffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e64 v4, |v0|, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-GISEL-NEXT: v_sub_f32_e64 v2, |v0|, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
+; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_fabs_f32:
; GFX900-SDAG: ; %bb.0:
@@ -2890,32 +2943,59 @@ define float @v_exp_fabs_f32(float %in) {
}
define float @v_exp_fneg_fabs_f32(float %in) {
-; VI-LABEL: v_exp_fneg_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_or_b32_e32 v1, 0x80000000, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
-; VI-NEXT: v_sub_f32_e64 v4, -|v0|, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0x42ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: s_mov_b32 s4, 0xc2b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_fneg_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_or_b32_e32 v1, 0x80000000, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e64 v4, -|v0|, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_fneg_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_or_b32_e32 v1, 0x80000000, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-GISEL-NEXT: v_sub_f32_e64 v2, -|v0|, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
+; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_fneg_fabs_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3025,32 +3105,59 @@ define float @v_exp_fneg_fabs_f32(float %in) {
}
define float @v_exp_fneg_f32(float %in) {
-; VI-LABEL: v_exp_fneg_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
-; VI-NEXT: v_sub_f32_e64 v4, -v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0x42ce8ed0
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0xc2b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_fneg_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e64 v4, -v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42ce8ed0
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_fneg_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-GISEL-NEXT: v_sub_f32_e64 v2, -v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
+; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_fneg_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3225,27 +3332,49 @@ define float @v_exp_f32_fast(float %in) {
}
define float @v_exp_f32_ninf(float %in) {
-; VI-LABEL: v_exp_f32_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -3568,31 +3697,57 @@ define float @v_fabs_exp_f32_afn(float %in) {
}
define float @v_exp_f32_daz(float %in) #0 {
-; VI-LABEL: v_exp_f32_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_daz:
; GFX900-SDAG: ; %bb.0:
@@ -3700,31 +3855,57 @@ define float @v_exp_f32_daz(float %in) #0 {
}
define float @v_exp_f32_nnan(float %in) {
-; VI-LABEL: v_exp_f32_nnan:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_nnan:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_nnan:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_nnan:
; GFX900-SDAG: ; %bb.0:
@@ -3832,31 +4013,57 @@ define float @v_exp_f32_nnan(float %in) {
}
define float @v_exp_f32_nnan_daz(float %in) #0 {
-; VI-LABEL: v_exp_f32_nnan_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_nnan_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_nnan_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_nnan_daz:
; GFX900-SDAG: ; %bb.0:
@@ -3964,31 +4171,57 @@ define float @v_exp_f32_nnan_daz(float %in) #0 {
}
define float @v_exp_f32_nnan_dynamic(float %in) #1 {
-; VI-LABEL: v_exp_f32_nnan_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_nnan_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_nnan_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_nnan_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -4096,27 +4329,49 @@ define float @v_exp_f32_nnan_dynamic(float %in) #1 {
}
define float @v_exp_f32_ninf_daz(float %in) #0 {
-; VI-LABEL: v_exp_f32_ninf_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_ninf_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_ninf_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_ninf_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4208,27 +4463,49 @@ define float @v_exp_f32_ninf_daz(float %in) #0 {
}
define float @v_exp_f32_ninf_dynamic(float %in) #1 {
-; VI-LABEL: v_exp_f32_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_ninf_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -4320,27 +4597,49 @@ define float @v_exp_f32_ninf_dynamic(float %in) #1 {
}
define float @v_exp_f32_nnan_ninf(float %in) {
-; VI-LABEL: v_exp_f32_nnan_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_nnan_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_nnan_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_nnan_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -4432,27 +4731,49 @@ define float @v_exp_f32_nnan_ninf(float %in) {
}
define float @v_exp_f32_nnan_ninf_daz(float %in) #0 {
-; VI-LABEL: v_exp_f32_nnan_ninf_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_nnan_ninf_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_nnan_ninf_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_nnan_ninf_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4544,27 +4865,49 @@ define float @v_exp_f32_nnan_ninf_daz(float %in) #0 {
}
define float @v_exp_f32_nnan_ninf_dynamic(float %in) #1 {
-; VI-LABEL: v_exp_f32_nnan_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_nnan_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_nnan_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_nnan_ninf_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -4684,31 +5027,57 @@ define float @v_exp_f32_fast_daz(float %in) #0 {
}
define float @v_exp_f32_dynamic_mode(float %in) #1 {
-; VI-LABEL: v_exp_f32_dynamic_mode:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_dynamic_mode:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_dynamic_mode:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_dynamic_mode:
; GFX900-SDAG: ; %bb.0:
@@ -4866,32 +5235,59 @@ define float @v_exp_f32_0() {
}
define float @v_exp_f32_from_fpext_f16(i16 %src.i) {
-; VI-LABEL: v_exp_f32_from_fpext_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v2
-; VI-NEXT: v_add_f32_e32 v3, v3, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v4
-; VI-NEXT: v_add_f32_e32 v1, v1, v3
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v4
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_from_fpext_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v3
+; VI-SDAG-NEXT: v_rndne_f32_e32 v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v4
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_from_fpext_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_f16:
; GFX900-SDAG: ; %bb.0:
@@ -5005,33 +5401,61 @@ define float @v_exp_f32_from_fpext_f16(i16 %src.i) {
}
define float @v_exp_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
-; VI-LABEL: v_exp_f32_from_fpext_math_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
-; VI-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v1
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_rndne_f32_e32 v3, v1
-; VI-NEXT: v_sub_f32_e32 v1, v1, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_math_f16:
; GFX900-SDAG: ; %bb.0:
@@ -5157,31 +5581,57 @@ define float @v_exp_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
}
define float @v_exp_f32_from_fpext_bf16(bfloat %src) {
-; VI-LABEL: v_exp_f32_from_fpext_bf16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v0
-; VI-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v0
-; VI-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v3
-; VI-NEXT: v_rndne_f32_e32 v2, v1
-; VI-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v0
-; VI-NEXT: v_sub_f32_e32 v1, v1, v2
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v3
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v2
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_from_fpext_bf16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v3
+; VI-SDAG-NEXT: v_rndne_f32_e32 v2, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_from_fpext_bf16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, v0, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_rndne_f32_e32 v3, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_bf16:
; GFX900-SDAG: ; %bb.0:
@@ -5345,33 +5795,61 @@ define float @v_exp_f32_from_fpext_math_f16_fast(i16 %src0.i, i16 %src1.i) {
}
define float @v_exp_f32_from_fpext_math_f16_daz(i16 %src0.i, i16 %src1.i) #0 {
-; VI-LABEL: v_exp_f32_from_fpext_math_f16_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
-; VI-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v1
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_rndne_f32_e32 v3, v1
-; VI-NEXT: v_sub_f32_e32 v1, v1, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_daz:
; GFX900-SDAG: ; %bb.0:
@@ -6469,31 +6947,57 @@ define <3 x half> @v_exp_v3f16_afn(<3 x half> %in) {
}
define float @v_exp_f32_contract(float %in) {
-; VI-LABEL: v_exp_f32_contract:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_contract:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_contract:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_contract:
; GFX900-SDAG: ; %bb.0:
@@ -6601,31 +7105,57 @@ define float @v_exp_f32_contract(float %in) {
}
define float @v_exp_f32_contract_daz(float %in) #0 {
-; VI-LABEL: v_exp_f32_contract_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x42b17218
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_contract_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_contract_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_contract_daz:
; GFX900-SDAG: ; %bb.0:
@@ -6733,27 +7263,49 @@ define float @v_exp_f32_contract_daz(float %in) #0 {
}
define float @v_exp_f32_contract_nnan_ninf(float %in) {
-; VI-LABEL: v_exp_f32_contract_nnan_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f32_contract_nnan_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f32_contract_nnan_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_contract_nnan_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -6858,3 +7410,5 @@ declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2
attributes #0 = { denormal_fpenv(float: ieee|preservesign) }
attributes #1 = { denormal_fpenv(float: dynamic|dynamic) }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
index f4819c9ae6910..5578dacc38dd9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,VI,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GFX900,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI,SI-GISEL %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -2626,31 +2626,57 @@ define amdgpu_kernel void @s_exp10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
}
define float @v_exp10_f32(float %in) {
-; VI-LABEL: v_exp10_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32:
; GFX900-SDAG: ; %bb.0:
@@ -2758,32 +2784,59 @@ define float @v_exp10_f32(float %in) {
}
define float @v_exp10_fabs_f32(float %in) {
-; VI-LABEL: v_exp10_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
-; VI-NEXT: v_and_b32_e32 v1, 0x7ffff000, v1
-; VI-NEXT: v_sub_f32_e64 v4, |v0|, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7ffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e64 v4, |v0|, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-GISEL-NEXT: v_sub_f32_e64 v2, |v0|, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
+; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_fabs_f32:
; GFX900-SDAG: ; %bb.0:
@@ -2892,32 +2945,59 @@ define float @v_exp10_fabs_f32(float %in) {
}
define float @v_exp10_fneg_fabs_f32(float %in) {
-; VI-LABEL: v_exp10_fneg_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_or_b32_e32 v1, 0x80000000, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
-; VI-NEXT: v_sub_f32_e64 v4, -|v0|, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0x423369f4
-; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: s_mov_b32 s4, 0xc21a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_fneg_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_or_b32_e32 v1, 0x80000000, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e64 v4, -|v0|, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x423369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_fneg_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_or_b32_e32 v1, 0x80000000, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-GISEL-NEXT: v_sub_f32_e64 v2, -|v0|, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
+; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_fneg_fabs_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3027,32 +3107,59 @@ define float @v_exp10_fneg_fabs_f32(float %in) {
}
define float @v_exp10_fneg_f32(float %in) {
-; VI-LABEL: v_exp10_fneg_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
-; VI-NEXT: v_sub_f32_e64 v4, -v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0x423369f4
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0xc21a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_fneg_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e64 v4, -v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x423369f4
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_fneg_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
+; VI-GISEL-NEXT: v_sub_f32_e64 v2, -v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
+; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_fneg_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3239,27 +3346,49 @@ define float @v_exp10_f32_fast(float %in) {
}
define float @v_exp10_f32_ninf(float %in) {
-; VI-LABEL: v_exp10_f32_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -3624,31 +3753,57 @@ define float @v_fabs_exp10_f32_afn(float %in) {
}
define float @v_exp10_f32_daz(float %in) #0 {
-; VI-LABEL: v_exp10_f32_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_daz:
; GFX900-SDAG: ; %bb.0:
@@ -3756,31 +3911,57 @@ define float @v_exp10_f32_daz(float %in) #0 {
}
define float @v_exp10_f32_nnan(float %in) {
-; VI-LABEL: v_exp10_f32_nnan:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_nnan:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_nnan:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_nnan:
; GFX900-SDAG: ; %bb.0:
@@ -3888,31 +4069,57 @@ define float @v_exp10_f32_nnan(float %in) {
}
define float @v_exp10_f32_nnan_daz(float %in) #0 {
-; VI-LABEL: v_exp10_f32_nnan_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_nnan_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_nnan_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_nnan_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4020,31 +4227,57 @@ define float @v_exp10_f32_nnan_daz(float %in) #0 {
}
define float @v_exp10_f32_nnan_dynamic(float %in) #1 {
-; VI-LABEL: v_exp10_f32_nnan_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_nnan_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_nnan_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_nnan_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -4152,27 +4385,49 @@ define float @v_exp10_f32_nnan_dynamic(float %in) #1 {
}
define float @v_exp10_f32_ninf_daz(float %in) #0 {
-; VI-LABEL: v_exp10_f32_ninf_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_ninf_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_ninf_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_ninf_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4264,27 +4519,49 @@ define float @v_exp10_f32_ninf_daz(float %in) #0 {
}
define float @v_exp10_f32_ninf_dynamic(float %in) #1 {
-; VI-LABEL: v_exp10_f32_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_ninf_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -4376,27 +4653,49 @@ define float @v_exp10_f32_ninf_dynamic(float %in) #1 {
}
define float @v_exp10_f32_nnan_ninf(float %in) {
-; VI-LABEL: v_exp10_f32_nnan_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -4488,27 +4787,49 @@ define float @v_exp10_f32_nnan_ninf(float %in) {
}
define float @v_exp10_f32_nnan_ninf_daz(float %in) #0 {
-; VI-LABEL: v_exp10_f32_nnan_ninf_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4600,27 +4921,49 @@ define float @v_exp10_f32_nnan_ninf_daz(float %in) #0 {
}
define float @v_exp10_f32_nnan_ninf_dynamic(float %in) #1 {
-; VI-LABEL: v_exp10_f32_nnan_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -4746,31 +5089,57 @@ define float @v_exp10_f32_fast_daz(float %in) #0 {
}
define float @v_exp10_f32_dynamic_mode(float %in) #1 {
-; VI-LABEL: v_exp10_f32_dynamic_mode:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_dynamic_mode:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_dynamic_mode:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_dynamic_mode:
; GFX900-SDAG: ; %bb.0:
@@ -4928,32 +5297,59 @@ define float @v_exp10_f32_0() {
}
define float @v_exp10_f32_from_fpext_f16(i16 %src.i) {
-; VI-LABEL: v_exp10_f32_from_fpext_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x40549000, v3
-; VI-NEXT: v_rndne_f32_e32 v4, v2
-; VI-NEXT: v_add_f32_e32 v3, v3, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v4
-; VI-NEXT: v_add_f32_e32 v1, v1, v3
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v4
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_from_fpext_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x40549000, v3
+; VI-SDAG-NEXT: v_rndne_f32_e32 v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v4
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_from_fpext_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_f16:
; GFX900-SDAG: ; %bb.0:
@@ -5067,33 +5463,61 @@ define float @v_exp10_f32_from_fpext_f16(i16 %src.i) {
}
define float @v_exp10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
-; VI-LABEL: v_exp10_f32_from_fpext_math_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
-; VI-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v1
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x40549000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_rndne_f32_e32 v3, v1
-; VI-NEXT: v_sub_f32_e32 v1, v1, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16:
; GFX900-SDAG: ; %bb.0:
@@ -5219,31 +5643,57 @@ define float @v_exp10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
}
define float @v_exp10_f32_from_fpext_bf16(bfloat %src) {
-; VI-LABEL: v_exp10_f32_from_fpext_bf16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v0
-; VI-NEXT: v_mul_f32_e32 v1, 0x40549000, v0
-; VI-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x40549000, v3
-; VI-NEXT: v_rndne_f32_e32 v2, v1
-; VI-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v0
-; VI-NEXT: v_sub_f32_e32 v1, v1, v2
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v3
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v2
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_from_fpext_bf16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x40549000, v3
+; VI-SDAG-NEXT: v_rndne_f32_e32 v2, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_from_fpext_bf16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, v0, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x40549000, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_rndne_f32_e32 v3, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_bf16:
; GFX900-SDAG: ; %bb.0:
@@ -5416,33 +5866,61 @@ define float @v_exp10_f32_from_fpext_math_f16_fast(i16 %src0.i, i16 %src1.i) {
}
define float @v_exp10_f32_from_fpext_math_f16_daz(i16 %src0.i, i16 %src1.i) #0 {
-; VI-LABEL: v_exp10_f32_from_fpext_math_f16_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
-; VI-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v1
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x40549000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_rndne_f32_e32 v3, v1
-; VI-NEXT: v_sub_f32_e32 v1, v1, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_daz:
; GFX900-SDAG: ; %bb.0:
@@ -6702,31 +7180,57 @@ define <3 x half> @v_exp10_v3f16_afn(<3 x half> %in) {
}
define float @v_exp10_f32_contract(float %in) {
-; VI-LABEL: v_exp10_f32_contract:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_contract:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_contract:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_contract:
; GFX900-SDAG: ; %bb.0:
@@ -6834,31 +7338,57 @@ define float @v_exp10_f32_contract(float %in) {
}
define float @v_exp10_f32_contract_daz(float %in) #0 {
-; VI-LABEL: v_exp10_f32_contract_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: s_mov_b32 s4, 0x421a209b
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_contract_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_contract_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_contract_daz:
; GFX900-SDAG: ; %bb.0:
@@ -6966,27 +7496,49 @@ define float @v_exp10_f32_contract_daz(float %in) #0 {
}
define float @v_exp10_f32_contract_nnan_ninf(float %in) {
-; VI-LABEL: v_exp10_f32_contract_nnan_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v4, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
-; VI-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
-; VI-NEXT: v_rndne_f32_e32 v3, v2
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
-; VI-NEXT: v_sub_f32_e32 v2, v2, v3
-; VI-NEXT: v_add_f32_e32 v1, v1, v4
-; VI-NEXT: v_add_f32_e32 v1, v2, v1
-; VI-NEXT: v_exp_f32_e32 v1, v1
-; VI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; VI-NEXT: s_mov_b32 s4, 0xc23369f4
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_ldexp_f32 v1, v1, v2
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp10_f32_contract_nnan_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4
+; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f32_contract_nnan_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_contract_nnan_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -7091,3 +7643,5 @@ declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2
attributes #0 = { denormal_fpenv(float: ieee|preservesign) }
attributes #1 = { denormal_fpenv(float: dynamic|dynamic) }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index 1784240376830..a5894a0761d49 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -2848,30 +2848,56 @@ define float @v_log_f32(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3022,30 +3048,56 @@ define float @v_log_fabs_f32(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, |v0|, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_fabs_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3198,30 +3250,56 @@ define float @v_log_fneg_fabs_f32(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_fneg_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x80800000
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, -|v0|, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_fneg_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_fneg_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_fneg_fabs_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3375,30 +3453,56 @@ define float @v_log_fneg_f32(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_fneg_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x80800000
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, -v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_fneg_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, -v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_fneg_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_fneg_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3666,30 +3770,56 @@ define float @v_log_f32_ninf(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -4202,23 +4332,41 @@ define float @v_log_f32_daz(float %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4339,30 +4487,56 @@ define float @v_log_f32_nnan(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_nnan:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_nnan:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_nnan:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_nnan:
; GFX900-SDAG: ; %bb.0:
@@ -4498,23 +4672,41 @@ define float @v_log_f32_nnan_daz(float %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_nnan_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_nnan_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_nnan_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_nnan_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4635,30 +4827,56 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_nnan_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_nnan_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_nnan_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_nnan_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -4794,23 +5012,41 @@ define float @v_log_f32_ninf_daz(float %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_ninf_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_ninf_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_ninf_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_ninf_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4931,30 +5167,56 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_ninf_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -5099,27 +5361,50 @@ define float @v_log_f32_nnan_ninf(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_nnan_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3f317000, v0
-; VI-NEXT: v_mul_f32_e32 v0, 0x3805fdf4, v0
-; VI-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v0, v3, v0
-; VI-NEXT: v_add_f32_e32 v0, v2, v0
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v0, v1, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_nnan_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317000, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3805fdf4, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v3, v0
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_nnan_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317000, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_nnan_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -5356,27 +5641,50 @@ define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_nnan_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3f317000, v0
-; VI-NEXT: v_mul_f32_e32 v0, 0x3805fdf4, v0
-; VI-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v0, v3, v0
-; VI-NEXT: v_add_f32_e32 v0, v2, v0
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v0, v1, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317000, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3805fdf4, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v3, v0
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317000, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -5545,30 +5853,56 @@ define float @v_log_f32_dynamic_mode(float %in) #1 {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_dynamic_mode:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_dynamic_mode:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_dynamic_mode:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_dynamic_mode:
; GFX900-SDAG: ; %bb.0:
@@ -5756,24 +6090,43 @@ define float @v_log_f32_from_fpext_f16(i16 %src.i) {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_from_fpext_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_from_fpext_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_from_fpext_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_from_fpext_f16:
; GFX900-SDAG: ; %bb.0:
@@ -5931,25 +6284,45 @@ define float @v_log_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_from_fpext_math_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_from_fpext_math_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_from_fpext_math_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_from_fpext_math_f16:
; GFX900-SDAG: ; %bb.0:
@@ -6122,31 +6495,58 @@ define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_f32_from_fpext_bf16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log_f32_from_fpext_bf16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log_f32_from_fpext_bf16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_from_fpext_bf16:
; GFX900-SDAG: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 98236bbcf9248..44ceab1728db2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -2848,30 +2848,56 @@ define float @v_log10_f32(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3022,30 +3048,56 @@ define float @v_log10_fabs_f32(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, |v0|, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_fabs_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3198,30 +3250,56 @@ define float @v_log10_fneg_fabs_f32(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_fneg_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x80800000
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, -|v0|, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_fneg_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_fneg_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_fneg_fabs_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3375,30 +3453,56 @@ define float @v_log10_fneg_f32(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_fneg_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x80800000
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, -v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_fneg_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, -v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_fneg_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_fneg_f32:
; GFX900-SDAG: ; %bb.0:
@@ -3666,30 +3770,56 @@ define float @v_log10_f32_ninf(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -4202,23 +4332,41 @@ define float @v_log10_f32_daz(float %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4339,30 +4487,56 @@ define float @v_log10_f32_nnan(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_nnan:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_nnan:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_nnan:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_nnan:
; GFX900-SDAG: ; %bb.0:
@@ -4498,23 +4672,41 @@ define float @v_log10_f32_nnan_daz(float %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_nnan_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_nnan_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_nnan_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_nnan_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4635,30 +4827,56 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_nnan_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_nnan_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_nnan_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_nnan_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -4794,23 +5012,41 @@ define float @v_log10_f32_ninf_daz(float %in) #0 {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_ninf_daz:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_ninf_daz:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_ninf_daz:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_ninf_daz:
; GFX900-SDAG: ; %bb.0:
@@ -4931,30 +5167,56 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_ninf_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -5099,27 +5361,50 @@ define float @v_log10_f32_nnan_ninf(float %in) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_nnan_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v0
-; VI-NEXT: v_mul_f32_e32 v0, 0x369a84fb, v0
-; VI-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v0, v3, v0
-; VI-NEXT: v_add_f32_e32 v0, v2, v0
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v0, v1, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_nnan_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x369a84fb, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v3, v0
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_nnan_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a2000, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_nnan_ninf:
; GFX900-SDAG: ; %bb.0:
@@ -5356,27 +5641,50 @@ define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_nnan_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v0
-; VI-NEXT: v_mul_f32_e32 v0, 0x369a84fb, v0
-; VI-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v0, v3, v0
-; VI-NEXT: v_add_f32_e32 v0, v2, v0
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v0, v1, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x369a84fb, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v3, v0
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a2000, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
; GFX900-SDAG: ; %bb.0:
@@ -5545,30 +5853,56 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_dynamic_mode:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_dynamic_mode:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_dynamic_mode:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_dynamic_mode:
; GFX900-SDAG: ; %bb.0:
@@ -5756,24 +6090,43 @@ define float @v_log10_f32_from_fpext_f16(i16 %src.i) {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_from_fpext_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v3, v0, v1
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_from_fpext_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_from_fpext_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_from_fpext_f16:
; GFX900-SDAG: ; %bb.0:
@@ -5931,25 +6284,45 @@ define float @v_log10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_from_fpext_math_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
-; VI-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_from_fpext_math_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_from_fpext_math_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_from_fpext_math_f16:
; GFX900-SDAG: ; %bb.0:
@@ -6122,31 +6495,58 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_f32_from_fpext_bf16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log10_f32_from_fpext_bf16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_log10_f32_from_fpext_bf16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_from_fpext_bf16:
; GFX900-SDAG: ; %bb.0:
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