[llvm] [TableGen][AMDGPU][AsmParser] Catch and fix ambiguous instructions (PR #211093)

[Ivan Kosarev via llvm-commits]

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@@ -2911,6 +2913,102 @@ def isWave32Strict : Predicate<"Subtarget->isWave32()">,
 def isWave64Strict : Predicate<"Subtarget->isWave64()">,
   AssemblerPredicate <(all_of FeatureWavefrontSize64)>;
 
+def : MutuallyExclusiveAssemblerPredicates<isGFX8GFX9NotGFX90A,
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kosarev wrote:

> IIf, after that, we still find compelling use cases for what this PR proposes, I'd be happy to see it.

There are already fixes in this patch that are not related to subtarget predicates, see https://github.com/llvm/llvm-project/pull/211093/changes#diff-bfd398f33980e2dad30c39c83b325066633fe6c107982e6d1207d070580940d3R60

https://github.com/llvm/llvm-project/pull/211093