[llvm] [TableGen][AMDGPU][AsmParser] Catch and fix ambiguous instructions (PR #211093)

[Ivan Kosarev via llvm-commits]

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@@ -2911,6 +2913,102 @@ def isWave32Strict : Predicate<"Subtarget->isWave32()">,
 def isWave64Strict : Predicate<"Subtarget->isWave64()">,
   AssemblerPredicate <(all_of FeatureWavefrontSize64)>;
 
+def : MutuallyExclusiveAssemblerPredicates<isGFX8GFX9NotGFX90A,
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kosarev wrote:

The patch is about catching instructions and aliases that look identical to the AsmParser. It is not about subtarget predicates specifically. Getting rid of the subtarget predicates will not resolve the problem this patch addresses.

https://github.com/llvm/llvm-project/pull/211093