[llvm] [AMDGPU] Improved register pressure estimates for rescheduling (PR #213116)

[Lucas Ramirez via llvm-commits]

================
@@ -1213,3 +1214,83 @@ LLVM_DUMP_METHOD void llvm::dumpMaxRegPressure(MachineFunction &MF,
   }
 }
 #endif
+
+unsigned llvm::estimateGreedyVGPRPressure(
+    MachineBasicBlock::const_iterator RegionBegin,
+    MachineBasicBlock::const_iterator RegionEnd,
+    const GCNRPTracker::LiveRegSet &LiveIns, LiveIntervals &LIS,
+    const MachineRegisterInfo &MRI, const SIRegisterInfo &TRI) {
+
+  SmallVector<LiveInterval *> RegionIntervals;
+  SmallPtrSet<LiveInterval *, 32> Seen;
+
+  auto IsVGPR = [&MRI, &TRI](Register VReg) {
+    const TargetRegisterClass *RC = MRI.getRegClass(VReg);
+    return TRI.isVGPRClass(RC) || TRI.isVectorSuperClass(RC);
+  };
+
+  // Collect live-ins
+  for (const auto &[RegNum, LaneMask] : LiveIns) {
+    Register VReg(RegNum);
+    if (!VReg.isVirtual() || !LIS.hasInterval(VReg) || !IsVGPR(VReg))
+      continue;
+    LiveInterval &LI = LIS.getInterval(VReg);
+    if (Seen.insert(&LI).second)
+      RegionIntervals.push_back(&LI);
+  }
+
+  // Collect defs in region
+  for (auto I = RegionBegin; I != RegionEnd; ++I) {
----------------
lucas-rami wrote:

```suggestion
  for (MachineBasicBlock::const_iterator I = RegionBegin; I != RegionEnd; ++I) {
```

https://github.com/llvm/llvm-project/pull/213116