[llvm] [AArch64] NFC: simplify isCopyInstrImpl expression (PR #212487)

[Sander de Smalen via llvm-commits]

https://github.com/sdesmalen-arm updated https://github.com/llvm/llvm-project/pull/212487

>From a1ba797b258d903247d6e9ebb3abe697d3cba475 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Mon, 27 Jul 2026 16:08:21 +0000
Subject: [PATCH 1/2] [AArch64] NFC: simplify isCopyInstrImpl expression

To something more intuitive, by applying the following logic:
* `!isVirtual()` -> `isPhysical()`
* `!isPhysical()` -> `isVirtual()`
* `(a || b) && (!a || c)` -> `(!a && b) || (a && c)`
---
 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 25 ++++++++++----------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 6b640727c82c9..11953879cafc7 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -11356,18 +11356,19 @@ AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
 
   // AArch64::ORRWrs and AArch64::ORRXrs with WZR/XZR reg
   // and zero immediate operands used as an alias for mov instruction.
-  if (((MI.getOpcode() == AArch64::ORRWrs &&
-        MI.getOperand(1).getReg() == AArch64::WZR &&
-        MI.getOperand(3).getImm() == 0x0) ||
-       (MI.getOpcode() == AArch64::ORRWrr &&
-        MI.getOperand(1).getReg() == AArch64::WZR)) &&
-      // Check that the w->w move is not a zero-extending w->x mov.
-      (!MI.getOperand(0).getReg().isVirtual() ||
-       MI.getOperand(0).getSubReg() == 0) &&
-      (!MI.getOperand(0).getReg().isPhysical() ||
-       MI.findRegisterDefOperandIdx(getXRegFromWReg(MI.getOperand(0).getReg()),
-                                    /*TRI=*/nullptr) == -1))
-    return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
+  if ((MI.getOpcode() == AArch64::ORRWrs &&
+       MI.getOperand(1).getReg() == AArch64::WZR &&
+       MI.getOperand(3).getImm() == 0x0) ||
+      (MI.getOpcode() == AArch64::ORRWrr &&
+       MI.getOperand(1).getReg() == AArch64::WZR))
+    // Check that the w->w move is not a zero-extending w->x mov.
+    if ((MI.getOperand(0).getReg().isPhysical() &&
+         MI.findRegisterDefOperandIdx(
+             getXRegFromWReg(MI.getOperand(0).getReg()),
+             /*TRI=*/nullptr) == -1) ||
+        (MI.getOperand(0).getReg().isVirtual() &&
+         !MI.getOperand(0).getSubReg()))
+      return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
 
   if (MI.getOpcode() == AArch64::ORRXrs &&
       MI.getOperand(1).getReg() == AArch64::XZR &&

>From f00ff79af0c41df0493e02e39520de442de76338 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Wed, 29 Jul 2026 08:46:34 +0000
Subject: [PATCH 2/2] Add curly braces around block

---
 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 11953879cafc7..ac827debe207c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -11360,7 +11360,7 @@ AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
        MI.getOperand(1).getReg() == AArch64::WZR &&
        MI.getOperand(3).getImm() == 0x0) ||
       (MI.getOpcode() == AArch64::ORRWrr &&
-       MI.getOperand(1).getReg() == AArch64::WZR))
+       MI.getOperand(1).getReg() == AArch64::WZR)) {
     // Check that the w->w move is not a zero-extending w->x mov.
     if ((MI.getOperand(0).getReg().isPhysical() &&
          MI.findRegisterDefOperandIdx(
@@ -11369,6 +11369,7 @@ AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
         (MI.getOperand(0).getReg().isVirtual() &&
          !MI.getOperand(0).getSubReg()))
       return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
+  }
 
   if (MI.getOpcode() == AArch64::ORRXrs &&
       MI.getOperand(1).getReg() == AArch64::XZR &&