[llvm] [AMDGPU][True16] Retain `hi16` subregisters through v2s copies (PR #211848)
Zach Goldthorpe via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 24 12:51:20 PDT 2026
https://github.com/zGoldthorpe updated https://github.com/llvm/llvm-project/pull/211848
>From 23a8e7095df69dfa8d125ff90089be0695c32cac Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Fri, 24 Jul 2026 10:00:12 -0500
Subject: [PATCH 1/5] [AMDGPU] Propagate `hi16` subregisters through widening
copies
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 23 +-
.../AMDGPU/fix-sgpr-copies-f16-true16.mir | 14 +
llvm/test/CodeGen/AMDGPU/fp_to_sint.ll | 6 +-
llvm/test/CodeGen/AMDGPU/fp_to_uint.ll | 6 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 2572 +++++++----------
.../AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll | 5 +-
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll | 60 +-
.../AMDGPU/llvm.amdgcn.interp.inreg.ll | 26 +-
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 485 ++--
.../AMDGPU/preload-implicit-kernargs.ll | 34 +-
llvm/test/CodeGen/AMDGPU/spillv16.ll | 89 +-
11 files changed, 1429 insertions(+), 1891 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 28914d598a72d..11f8ce34d981c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7894,18 +7894,27 @@ void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI, unsigned OpIdx,
int16_t RCID = getOpRegClassID(get(Opcode).operands()[OpIdx]);
const TargetRegisterClass *ExpectedRC = RI.getRegClass(RCID);
if (RI.getMatchingSuperRegClass(CurrRC, ExpectedRC, AMDGPU::lo16)) {
- Op.setSubReg(AMDGPU::lo16);
- } else if (RI.getMatchingSuperRegClass(ExpectedRC, CurrRC, AMDGPU::lo16)) {
+ // Default to the lo16 only if the subregister is not specified.
+ if (Op.getSubReg() == AMDGPU::NoSubRegister)
+ Op.setSubReg(AMDGPU::lo16);
+ return;
+ }
+
+ const TargetRegisterClass *CurrSRC =
+ RI.getSubRegisterClass(CurrRC, Op.getSubReg());
+ if (RI.getRegSizeInBits(*CurrSRC) == 16 &&
+ RI.getRegSizeInBits(*ExpectedRC) == 32) {
const DebugLoc &DL = MI.getDebugLoc();
Register NewDstReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
Register Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
BuildMI(*MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), Undef);
BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDstReg)
- .addReg(Op.getReg())
+ .addReg(Op.getReg(), {}, Op.getSubReg())
.addImm(AMDGPU::lo16)
.addReg(Undef)
.addImm(AMDGPU::hi16);
Op.setReg(NewDstReg);
+ Op.setSubReg(AMDGPU::NoSubRegister);
}
}
void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI,
@@ -8572,9 +8581,13 @@ void SIInstrInfo::moveToVALUImpl(
// that copies will end up as machine instructions and not be
// eliminated.
addUsersToMoveToVALUWorklist(DstReg, MRI, Worklist);
- MRI.replaceRegWith(DstReg, NewDstReg);
+ unsigned SrcSubReg = Inst.getOperand(1).getSubReg();
+ for (MachineOperand &Use :
+ make_early_inc_range(MRI.use_operands(DstReg))) {
+ Use.setSubReg(RI.composeSubRegIndices(SrcSubReg, Use.getSubReg()));
+ Use.setReg(NewDstReg);
+ }
MRI.clearKillFlags(NewDstReg);
- Inst.getOperand(0).setReg(DstReg);
if (!MRI.constrainRegClass(NewDstReg, CommonRC))
llvm_unreachable("failed to constrain register");
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
index 76bdfb57c9eb4..1b82911f60249 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
@@ -351,3 +351,17 @@ body: |
%1:sreg_32 = COPY %0:vgpr_32
%2:sreg_32 = S_PACK_LL_B32_B16 1, %1:sreg_32, implicit-def dead $scc
...
+
+---
+name: v_or_b16_t16_from_hi16
+body: |
+ bb.0:
+ ; GCN-LABEL: name: v_or_b16_t16_from_hi16
+ ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[V_OR_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_OR_B16_t16_e64 0, [[DEF]].lo16, 0, [[DEF1]].hi16, 0, implicit $exec
+ %0:vgpr_32 = IMPLICIT_DEF
+ %1:vgpr_32 = IMPLICIT_DEF
+ %2:sreg_32 = COPY %1.hi16
+ %3:vgpr_16 = V_OR_B16_t16_e64 0, %0.lo16, 0, killed %2, 0, implicit $exec
+...
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
index 95ada98691caa..2618c670b8c23 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
@@ -1282,10 +1282,10 @@ define amdgpu_kernel void @fp_to_sint_f32_i16(ptr addrspace(1) %out, float %in)
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, s2
-; GFX11-SDAG-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v1, s2
+; GFX11-SDAG-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_sint_f32_i16:
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
index 18adc5bf9f40f..2fb9e0b764391 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
@@ -1053,10 +1053,10 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i16(ptr addrspace(1) %out, float %i
; GFX11-SDAG-NEXT: s_clause 0x1
; GFX11-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, s2
-; GFX11-SDAG-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, s2
+; GFX11-SDAG-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: fp_to_uint_f32_to_i16:
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 8700059729501..aa4291060d539 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -529,24 +529,23 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[4:5] offset:8
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, |v1.l|
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] offset:8
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.h|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v2
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v2
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v2
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.l, v3.l, vcc_lo
; GFX11-TRUE16-NEXT: s_branch .LBB0_3
; GFX11-TRUE16-NEXT: .LBB0_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
@@ -556,43 +555,41 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v4
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v3, 11
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX11-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -600,49 +597,29 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v4, v3, v7
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: v_fma_f32 v1, -v4, v2, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v5, v3, v4
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v2, v3
-; GFX11-TRUE16-NEXT: .LBB0_9: ; %Flow19
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1.l|
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v3.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: frem_f16:
@@ -801,42 +778,41 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v2
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v5
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
-; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s1, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -844,46 +820,23 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, s0
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1150-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
-; GFX1150-TRUE16-NEXT: .LBB0_9: ; %Flow19
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1150-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1150-TRUE16-NEXT: .LBB0_8: ; %Flow19
; GFX1150-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
@@ -1059,42 +1012,41 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v2
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
-; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s1, s0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1102,49 +1054,26 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, s0
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1200-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
-; GFX1200-TRUE16-NEXT: .LBB0_9: ; %Flow19
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1200-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1200-TRUE16-NEXT: .LBB0_8: ; %Flow19
; GFX1200-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1200-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -6117,43 +6046,42 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v3
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v6, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v4
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v3
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v4, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -6161,42 +6089,22 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v4, v3, v7
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow55
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v5, v3, v4
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
-; GFX11-TRUE16-NEXT: .LBB9_9:
+; GFX11-TRUE16-NEXT: v_fma_f32 v2, -v5, v3, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX11-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: .LBB9_8:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6204,102 +6112,81 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v4.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_11
-; GFX11-TRUE16-NEXT: ; %bb.10: ; %frem.else
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_10
+; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB9_12
-; GFX11-TRUE16-NEXT: .LBB9_11:
+; GFX11-TRUE16-NEXT: s_branch .LBB9_11
+; GFX11-TRUE16-NEXT: .LBB9_10:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: .LBB9_12: ; %Flow53
+; GFX11-TRUE16-NEXT: .LBB9_11: ; %Flow53
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v7
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v6
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
+; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v5, 11
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v9, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v7
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v6
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, null, v6, v6, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v11, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v8
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v7, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, null, v6, v6, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v7, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v6, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v10, v11, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v9, v10, 1.0
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v11
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v12, v8, v11
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v7, v10
+; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v9, v11, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v10, v12, v8
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v12, v13, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v10, v12, v8
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v10
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v9, v11, v7
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v8, v8, v11, v12
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
-; GFX11-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v7, v7, v10, v11
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v7, v7, v6, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v5, v7
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v10, v8
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v7, v6, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, v7, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
-; GFX11-TRUE16-NEXT: ; %bb.16: ; %Flow
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v10
-; GFX11-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -10, v9
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v8, v6, v7
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v7, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v5.l, v5
-; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fff, v5, v6
-; GFX11-TRUE16-NEXT: .LBB9_18: ; %Flow54
+; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v8, v6, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, v5, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
+; GFX11-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
+; GFX11-TRUE16-NEXT: .LBB9_16: ; %Flow54
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
@@ -6578,42 +6465,41 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v0
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v0
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s5, s6, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -6621,154 +6507,107 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v2
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
; GFX1150-TRUE16-NEXT: s_add_i32 s5, s5, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s5, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; GFX1150-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow55
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, s5
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, v5
-; GFX1150-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
-; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX1150-TRUE16-NEXT: .LBB9_9:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1150-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1150-TRUE16-NEXT: .LBB9_8:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
+; GFX1150-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s8, s7
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
-; GFX1150-TRUE16-NEXT: ; %bb.10: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
+; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s9
-; GFX1150-TRUE16-NEXT: s_mov_b32 s9, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_12
-; GFX1150-TRUE16-NEXT: .LBB9_11:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s9, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
+; GFX1150-TRUE16-NEXT: s_mov_b32 s8, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_11
+; GFX1150-TRUE16-NEXT: .LBB9_10:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s8, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB9_12: ; %Flow53
+; GFX1150-TRUE16-NEXT: .LBB9_11: ; %Flow53
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
+; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v1
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v1
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v4
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
-; GFX1150-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s7, s8, s7
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s7, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s7, s7, 11
-; GFX1150-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
+; GFX1150-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1150-TRUE16-NEXT: s_add_i32 s7, s7, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s7, 11
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1150-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
-; GFX1150-TRUE16-NEXT: ; %bb.16: ; %Flow
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, s7
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v3, v6
-; GFX1150-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
+; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, s6
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
-; GFX1150-TRUE16-NEXT: .LBB9_18: ; %Flow54
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
+; GFX1150-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX1150-TRUE16-NEXT: .LBB9_16: ; %Flow54
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -7073,42 +6912,41 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v0
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v0
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s6, s5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7116,165 +6954,119 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v2
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s5, 11
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow55
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, s5
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, v5
-; GFX1200-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX1200-TRUE16-NEXT: .LBB9_9:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1200-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT: .LBB9_8:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
+; GFX1200-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s8, s7
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
-; GFX1200-TRUE16-NEXT: ; %bb.10: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
+; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s9
-; GFX1200-TRUE16-NEXT: s_mov_b32 s9, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_12
-; GFX1200-TRUE16-NEXT: .LBB9_11:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s9, -1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
+; GFX1200-TRUE16-NEXT: s_mov_b32 s8, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_11
+; GFX1200-TRUE16-NEXT: .LBB9_10:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s8, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB9_12: ; %Flow53
+; GFX1200-TRUE16-NEXT: .LBB9_11: ; %Flow53
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
+; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v1
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v1
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v4
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
-; GFX1200-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s7, s8, s7
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s7, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s7, s7, 11
-; GFX1200-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
+; GFX1200-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, v3
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s7, s7, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s7, 11
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
-; GFX1200-TRUE16-NEXT: ; %bb.16: ; %Flow
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, s7
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v3, v6
-; GFX1200-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v2.l, s6
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
-; GFX1200-TRUE16-NEXT: .LBB9_18: ; %Flow54
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
+; GFX1200-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX1200-TRUE16-NEXT: .LBB9_16: ; %Flow54
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -9429,43 +9221,42 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v5
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v4, 11
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v8, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v6
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v5
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, null, v5, v5, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v10, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v8, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v5
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, null, v5, v5, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v6, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v5, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v9, v10, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v10
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v7, v10
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v9, v11, v7
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v9, v11, v7
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
+; GFX11-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v7, v7, v10, v11
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v5, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -9473,42 +9264,22 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v6
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v4, v6
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, v9, v7
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v6, -v6, v5, v9
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, v6, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow133
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v9
-; GFX11-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -10, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v6, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v6, -v7, v5, v6
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v6, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v5, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v4.l, v4
-; GFX11-TRUE16-NEXT: v_bfi_b32 v4, 0x7fff, v4, v5
-; GFX11-TRUE16-NEXT: .LBB10_9:
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v7, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, v4, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX11-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: .LBB10_8:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9516,202 +9287,160 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |v6.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_11
-; GFX11-TRUE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_10
+; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else53
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v5.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_12
-; GFX11-TRUE16-NEXT: .LBB10_11:
+; GFX11-TRUE16-NEXT: s_branch .LBB10_11
+; GFX11-TRUE16-NEXT: .LBB10_10:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: .LBB10_12: ; %Flow131
+; GFX11-TRUE16-NEXT: .LBB10_11: ; %Flow131
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v9
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v8
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
+; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v7, 11
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v11, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v9
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v8
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v12, null, v8, v8, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, -1, v7
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v13, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v11, v7
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v10
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v8
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, null, v8, v8, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v9, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v12, v11
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, vcc_lo, 1.0, v8, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v12, v13, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v11, v12, 1.0
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v12, v13, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v13
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v10, v13
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v13, v9, v12
+; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v11, v13, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v12, v14, v10
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v12, v14, v10
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v12
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v11, v13, v9
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v10, v10, v13, v14
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX11-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v9, v9, v12, v13
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v9, v9, v8, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX11-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v7, v9
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v12, v10
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v9, v8, v12
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, v9, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX11-TRUE16-NEXT: ; %bb.16: ; %Flow129
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v12
-; GFX11-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -10, v11
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v9, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v9, v10
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v10, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v10, v8, v9
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v8, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v7.l, v7
-; GFX11-TRUE16-NEXT: v_bfi_b32 v7, 0x7fff, v7, v8
-; GFX11-TRUE16-NEXT: .LBB10_18:
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v10, v8, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, v7, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
+; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT: .LBB10_16:
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v10, |v1.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v3.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_20
-; GFX11-TRUE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_18
+; GFX11-TRUE16-NEXT: ; %bb.17: ; %frem.else20
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_21
-; GFX11-TRUE16-NEXT: .LBB10_20:
+; GFX11-TRUE16-NEXT: s_branch .LBB10_19
+; GFX11-TRUE16-NEXT: .LBB10_18:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: .LBB10_21: ; %Flow127
+; GFX11-TRUE16-NEXT: .LBB10_19: ; %Flow127
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX11-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v10
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX11-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v8, 11
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v9
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v12, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v10
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v13, null, v9, v9, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v8
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v14, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v12, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v12, v11
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v9
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v10, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v12, null, v9, v9, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v10, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v13, v12
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v9, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v13, v14, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v12, v13, 1.0
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v13
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v14
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v15, v11, v14
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v10, v13
+; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v12, v14, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v16, -v13, v15, v11
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v15, v16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v13, v15, v11
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v13
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v12, v14, v10
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v11, v11, v14, v15
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX11-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v10, v10, v13, v14
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v10, v10, v9, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX11-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v10
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v8, v10
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v13, v11
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v10, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v10, v9, v13
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, v10, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v10, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX11-TRUE16-NEXT: ; %bb.25: ; %Flow125
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v13
-; GFX11-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, -10, v12
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v10, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v11, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v11, v9, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, v10, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v8.l, v8
-; GFX11-TRUE16-NEXT: v_bfi_b32 v8, 0x7fff, v8, v9
-; GFX11-TRUE16-NEXT: .LBB10_27:
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v11, v9, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, v8, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
+; GFX11-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
+; GFX11-TRUE16-NEXT: .LBB10_24:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9719,102 +9448,81 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v12, |v10.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_29
-; GFX11-TRUE16-NEXT: ; %bb.28: ; %frem.else
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_26
+; GFX11-TRUE16-NEXT: ; %bb.25: ; %frem.else
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v9.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_30
-; GFX11-TRUE16-NEXT: .LBB10_29:
+; GFX11-TRUE16-NEXT: s_branch .LBB10_27
+; GFX11-TRUE16-NEXT: .LBB10_26:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: .LBB10_30: ; %Flow123
+; GFX11-TRUE16-NEXT: .LBB10_27: ; %Flow123
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
-; GFX11-TRUE16-NEXT: ; %bb.31: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v13
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v15, v12
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
+; GFX11-TRUE16-NEXT: ; %bb.28: ; %frem.compute
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v13, v11, 11
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v12
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v15, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v13
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v13, v12
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v12, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v16, null, v12, v12, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v11
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v17, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v15, v11
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, -1, v12
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v13, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v15, null, v12, v12, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v13, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v16, v15
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v13, vcc_lo, 1.0, v12, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v18, -v16, v17, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v17, -v15, v16, 1.0
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v16, v17, v16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v17, v18, v17
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v18, v14, v17
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v17, v13, v16
+; GFX11-TRUE16-NEXT: v_fma_f32 v18, -v15, v17, v13
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v19, -v16, v18, v14
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v18, v19, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v16, v18, v14
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v17, v18, v16
+; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v15, v17, v13
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v14, v14, v17, v18
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
-; GFX11-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v13, v13, v16, v17
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v14
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v13, v13, v12, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX11-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v16, v13
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v11, v13
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v13, v16, v14
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v13, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v13, v12, v16
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v13
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, v13, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v13, v13, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
-; GFX11-TRUE16-NEXT: ; %bb.34: ; %Flow
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v15, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v16
-; GFX11-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, -10, v15
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v13, v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v14, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v14, v12, v13
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v13
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, v13, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v12, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v11.l, v11
-; GFX11-TRUE16-NEXT: v_bfi_b32 v11, 0x7fff, v11, v12
-; GFX11-TRUE16-NEXT: .LBB10_36: ; %Flow124
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v14, v12, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, v11, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
+; GFX11-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
+; GFX11-TRUE16-NEXT: .LBB10_32: ; %Flow124
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
@@ -10313,42 +10021,41 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v0
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s8, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -10356,368 +10063,273 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v2
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; GFX1150-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow133
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, s6
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, v5
-; GFX1150-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
-; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v1.l, s5
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX1150-TRUE16-NEXT: .LBB10_9:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1150-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1150-TRUE16-NEXT: .LBB10_8:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1150-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
-; GFX1150-TRUE16-NEXT: ; %bb.10: ; %frem.else53
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
+; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s11
-; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_12
-; GFX1150-TRUE16-NEXT: .LBB10_11:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
+; GFX1150-TRUE16-NEXT: s_mov_b32 s10, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_11
+; GFX1150-TRUE16-NEXT: .LBB10_10:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s10, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB10_12: ; %Flow131
+; GFX1150-TRUE16-NEXT: .LBB10_11: ; %Flow131
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
+; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v1
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v4
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX1150-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s8, s9, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, 11
+; GFX1150-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
+; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s8, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1150-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX1150-TRUE16-NEXT: ; %bb.16: ; %Flow129
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, s9
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v3, v6
-; GFX1150-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, s8
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
-; GFX1150-TRUE16-NEXT: .LBB10_18:
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
+; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX1150-TRUE16-NEXT: .LBB10_16:
; GFX1150-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1150-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_20
-; GFX1150-TRUE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
+; GFX1150-TRUE16-NEXT: ; %bb.17: ; %frem.else20
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_21
-; GFX1150-TRUE16-NEXT: .LBB10_20:
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_19
+; GFX1150-TRUE16-NEXT: .LBB10_18:
; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB10_21: ; %Flow127
+; GFX1150-TRUE16-NEXT: .LBB10_19: ; %Flow127
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX1150-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1150-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v2
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v2
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v5
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
-; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX1150-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX1150-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1150-TRUE16-NEXT: ; %bb.25: ; %Flow125
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, s9
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1150-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, s7
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
-; GFX1150-TRUE16-NEXT: .LBB10_27:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
+; GFX1150-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1150-TRUE16-NEXT: .LBB10_24:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s12, s11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_29
-; GFX1150-TRUE16-NEXT: ; %bb.28: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
+; GFX1150-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s13
-; GFX1150-TRUE16-NEXT: s_mov_b32 s13, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_30
-; GFX1150-TRUE16-NEXT: .LBB10_29:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s13, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
+; GFX1150-TRUE16-NEXT: s_mov_b32 s12, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_27
+; GFX1150-TRUE16-NEXT: .LBB10_26:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s12, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: .LBB10_30: ; %Flow123
+; GFX1150-TRUE16-NEXT: .LBB10_27: ; %Flow123
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s13, s13, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s13, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
-; GFX1150-TRUE16-NEXT: ; %bb.31: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v3, 11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1150-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
+; GFX1150-TRUE16-NEXT: ; %bb.28: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s12, v6
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v3
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v7, v3
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v6
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v4, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
-; GFX1150-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
-; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
-; GFX1150-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s11, s12, s11
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX1150-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s10, s11, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s11, s11, 11
-; GFX1150-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, 11
+; GFX1150-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v8, v5
-; GFX1150-TRUE16-NEXT: s_add_i32 s11, s11, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s11, 11
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v8, v6
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1150-TRUE16-NEXT: v_fma_f32 v5, v5, v4, v8
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v7, v5, v4
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
-; GFX1150-TRUE16-NEXT: ; %bb.34: ; %Flow
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, s11
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v8
-; GFX1150-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
+; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s10, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
-; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v4.l, s10
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, v4
-; GFX1150-TRUE16-NEXT: .LBB10_36: ; %Flow124
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v6, v4
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v3, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
+; GFX1150-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX1150-TRUE16-NEXT: .LBB10_32: ; %Flow124
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -11270,42 +10882,41 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v0
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s8, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11313,165 +10924,119 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v2
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow133
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, s6
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, v5
-; GFX1200-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, s5
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX1200-TRUE16-NEXT: .LBB10_9:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1200-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT: .LBB10_8:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
+; GFX1200-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
-; GFX1200-TRUE16-NEXT: ; %bb.10: ; %frem.else53
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
+; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s11
-; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_12
-; GFX1200-TRUE16-NEXT: .LBB10_11:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
+; GFX1200-TRUE16-NEXT: s_mov_b32 s10, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_11
+; GFX1200-TRUE16-NEXT: .LBB10_10:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s10, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB10_12: ; %Flow131
+; GFX1200-TRUE16-NEXT: .LBB10_11: ; %Flow131
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
+; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v1
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v4
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX1200-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s8, s9, s8
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, 11
+; GFX1200-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, v3
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX1200-TRUE16-NEXT: ; %bb.16: ; %Flow129
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, s9
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v3, v6
-; GFX1200-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s8, 11
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v2.l, s8
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
-; GFX1200-TRUE16-NEXT: .LBB10_18:
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
+; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX1200-TRUE16-NEXT: .LBB10_16:
; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1200-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11480,8 +11045,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_20
-; GFX1200-TRUE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
+; GFX1200-TRUE16-NEXT: ; %bb.17: ; %frem.else20
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
@@ -11489,219 +11054,172 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_21
-; GFX1200-TRUE16-NEXT: .LBB10_20:
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_19
+; GFX1200-TRUE16-NEXT: .LBB10_18:
; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB10_21: ; %Flow127
+; GFX1200-TRUE16-NEXT: .LBB10_19: ; %Flow127
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX1200-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1200-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v2
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v2
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
-; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX1200-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX1200-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1200-TRUE16-NEXT: ; %bb.25: ; %Flow125
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, s9
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1200-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v3.l, s7
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
-; GFX1200-TRUE16-NEXT: .LBB10_27:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
+; GFX1200-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1200-TRUE16-NEXT: .LBB10_24:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s12, s11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_29
-; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
+; GFX1200-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s13
-; GFX1200-TRUE16-NEXT: s_mov_b32 s13, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_30
-; GFX1200-TRUE16-NEXT: .LBB10_29:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s13, -1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
+; GFX1200-TRUE16-NEXT: s_mov_b32 s12, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_27
+; GFX1200-TRUE16-NEXT: .LBB10_26:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s12, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: .LBB10_30: ; %Flow123
+; GFX1200-TRUE16-NEXT: .LBB10_27: ; %Flow123
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s13, s13, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s13, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
-; GFX1200-TRUE16-NEXT: ; %bb.31: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v3, 11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
+; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s12, v6
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v3
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v7, v3
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v6
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v4, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
-; GFX1200-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
-; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
-; GFX1200-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s11, s12, s11
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX1200-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s10, s11, s10
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s11, s11, 11
-; GFX1200-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, 11
+; GFX1200-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v8, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s11, s11, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s11, 11
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v8, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v5, v5, v4, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v7, v5, v4
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
-; GFX1200-TRUE16-NEXT: ; %bb.34: ; %Flow
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, s11
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v8
-; GFX1200-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v5, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v5, v6
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s10, 11
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v6, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v3, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v4.l, s10
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, v4
-; GFX1200-TRUE16-NEXT: .LBB10_36: ; %Flow124
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
+; GFX1200-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX1200-TRUE16-NEXT: .LBB10_32: ; %Flow124
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
index 1cbed44d60bcd..291cc9d43a07c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
@@ -251,9 +251,8 @@ define amdgpu_ps i32 @test_cvt_pk_fp8_f32_e5m3_word0_sss(float inreg %x, float i
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, s0, s1 clamp
; GFX1250-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
index 7f3dd04004da4..05d2f3d672cc4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
@@ -1571,9 +1571,8 @@ define amdgpu_ps i32 @test_cvt_pk_bf8_f32_word0_sss(float inreg %x, float inreg
;
; GFX1170-TRUE16-LABEL: test_cvt_pk_bf8_f32_word0_sss:
; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, s0, s1
; GFX1170-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1170-TRUE16-NEXT: ; return to shader part epilog
@@ -1596,9 +1595,8 @@ define amdgpu_ps i32 @test_cvt_pk_bf8_f32_word0_sss(float inreg %x, float inreg
;
; GFX12-TRUE16-LABEL: test_cvt_pk_bf8_f32_word0_sss:
; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, s0, s1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
@@ -1627,9 +1625,8 @@ define amdgpu_ps i32 @test_cvt_pk_bf8_f32_word0_sss(float inreg %x, float inreg
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.l, s0, s1
; GFX1250-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
@@ -1698,9 +1695,8 @@ define amdgpu_ps i32 @test_cvt_pk_bf8_f32_word1_sss(float inreg %x, float inreg
;
; GFX1170-TRUE16-LABEL: test_cvt_pk_bf8_f32_word1_sss:
; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.h, s0, s1
; GFX1170-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1170-TRUE16-NEXT: ; return to shader part epilog
@@ -1723,9 +1719,8 @@ define amdgpu_ps i32 @test_cvt_pk_bf8_f32_word1_sss(float inreg %x, float inreg
;
; GFX12-TRUE16-LABEL: test_cvt_pk_bf8_f32_word1_sss:
; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.h, s0, s1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
@@ -1754,9 +1749,8 @@ define amdgpu_ps i32 @test_cvt_pk_bf8_f32_word1_sss(float inreg %x, float inreg
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f32 v0.h, s0, s1
; GFX1250-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
@@ -1825,9 +1819,8 @@ define amdgpu_ps i32 @test_cvt_pk_fp8_f32_word0_sss(float inreg %x, float inreg
;
; GFX1170-TRUE16-LABEL: test_cvt_pk_fp8_f32_word0_sss:
; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, s0, s1
; GFX1170-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1170-TRUE16-NEXT: ; return to shader part epilog
@@ -1850,9 +1843,8 @@ define amdgpu_ps i32 @test_cvt_pk_fp8_f32_word0_sss(float inreg %x, float inreg
;
; GFX12-TRUE16-LABEL: test_cvt_pk_fp8_f32_word0_sss:
; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, s0, s1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
@@ -1881,9 +1873,8 @@ define amdgpu_ps i32 @test_cvt_pk_fp8_f32_word0_sss(float inreg %x, float inreg
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.l, s0, s1
; GFX1250-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
@@ -1952,9 +1943,8 @@ define amdgpu_ps i32 @test_cvt_pk_fp8_f32_word1_sss(float inreg %x, float inreg
;
; GFX1170-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1_sss:
; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.h, s0, s1
; GFX1170-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1170-TRUE16-NEXT: ; return to shader part epilog
@@ -1977,9 +1967,8 @@ define amdgpu_ps i32 @test_cvt_pk_fp8_f32_word1_sss(float inreg %x, float inreg
;
; GFX12-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1_sss:
; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.h, s0, s1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
@@ -2008,9 +1997,8 @@ define amdgpu_ps i32 @test_cvt_pk_fp8_f32_word1_sss(float inreg %x, float inreg
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f32 v0.h, s0, s1
; GFX1250-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
index c6c568d464956..8efa1133bc8c1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
@@ -362,15 +362,14 @@ main_body:
define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #0 {
; GFX11-TRUE16-SDAG-LABEL: v_interp_f16_imm_params:
; GFX11-TRUE16-SDAG: ; %bb.0: ; %main_body
-; GFX11-TRUE16-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.l, 0
+; GFX11-TRUE16-SDAG-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, 0
; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v2 wait_exp:7
; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.l, v1.l
-; GFX11-TRUE16-SDAG-NEXT: v_interp_p10_f16_f32 v2, v0.l, v2, v0.l wait_exp:7
-; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-SDAG-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v1 wait_exp:7
-; GFX11-TRUE16-SDAG-NEXT: v_cvt_f16_f32_e32 v0.h, v2
-; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-SDAG-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX11-TRUE16-SDAG-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l
; GFX11-TRUE16-SDAG-NEXT: ; return to shader part epilog
;
@@ -401,15 +400,14 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
;
; GFX12-TRUE16-SDAG-LABEL: v_interp_f16_imm_params:
; GFX12-TRUE16-SDAG: ; %bb.0: ; %main_body
-; GFX12-TRUE16-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0
+; GFX12-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.l, 0
+; GFX12-TRUE16-SDAG-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, 0
; GFX12-TRUE16-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v2 wait_exp:7
; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.l, v1.l
-; GFX12-TRUE16-SDAG-NEXT: v_interp_p10_f16_f32 v2, v0.l, v2, v0.l wait_exp:7
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-SDAG-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v1 wait_exp:7
-; GFX12-TRUE16-SDAG-NEXT: v_cvt_f16_f32_e32 v0.h, v2
-; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-SDAG-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX12-TRUE16-SDAG-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l
; GFX12-TRUE16-SDAG-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 11180eaa51b4f..0be76a1577f05 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -174,31 +174,18 @@ define amdgpu_kernel void @constant_load_v2i1(ptr addrspace(1) %out, ptr addrspa
; GFX12-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-TRUE16-LABEL: constant_load_v2i1:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1]
-; GFX1250-TRUE16-NEXT: s_endpgm
-;
-; GFX1250-FAKE16-LABEL: constant_load_v2i1:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: global_load_u8 v1, v0, s[2:3] nv
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]
-; GFX1250-FAKE16-NEXT: s_endpgm
+; GFX1250-LABEL: constant_load_v2i1:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: global_load_u8 v1, v0, s[2:3] nv
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
%load = load <2 x i1>, ptr addrspace(4) %in
store <2 x i1> %load, ptr addrspace(1) %out
ret void
@@ -280,31 +267,18 @@ define amdgpu_kernel void @constant_load_v3i1(ptr addrspace(1) %out, ptr addrspa
; GFX12-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-TRUE16-LABEL: constant_load_v3i1:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1]
-; GFX1250-TRUE16-NEXT: s_endpgm
-;
-; GFX1250-FAKE16-LABEL: constant_load_v3i1:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: global_load_u8 v1, v0, s[2:3] nv
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]
-; GFX1250-FAKE16-NEXT: s_endpgm
+; GFX1250-LABEL: constant_load_v3i1:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: global_load_u8 v1, v0, s[2:3] nv
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
%load = load <3 x i1>, ptr addrspace(4) %in
store <3 x i1> %load, ptr addrspace(1) %out
ret void
@@ -387,31 +361,18 @@ define amdgpu_kernel void @constant_load_v4i1(ptr addrspace(1) %out, ptr addrspa
; GFX12-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-TRUE16-LABEL: constant_load_v4i1:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1]
-; GFX1250-TRUE16-NEXT: s_endpgm
-;
-; GFX1250-FAKE16-LABEL: constant_load_v4i1:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: global_load_u8 v1, v0, s[2:3] nv
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]
-; GFX1250-FAKE16-NEXT: s_endpgm
+; GFX1250-LABEL: constant_load_v4i1:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: global_load_u8 v1, v0, s[2:3] nv
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
%load = load <4 x i1>, ptr addrspace(4) %in
store <4 x i1> %load, ptr addrspace(1) %out
ret void
@@ -494,31 +455,18 @@ define amdgpu_kernel void @constant_load_v8i1(ptr addrspace(1) %out, ptr addrspa
; GFX12-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-TRUE16-LABEL: constant_load_v8i1:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: global_load_u8 v0, v1, s[2:3] nv
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1]
-; GFX1250-TRUE16-NEXT: s_endpgm
-;
-; GFX1250-FAKE16-LABEL: constant_load_v8i1:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: global_load_u8 v1, v0, s[2:3] nv
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]
-; GFX1250-FAKE16-NEXT: s_endpgm
+; GFX1250-LABEL: constant_load_v8i1:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: global_load_u8 v1, v0, s[2:3] nv
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
%load = load <8 x i1>, ptr addrspace(4) %in
store <8 x i1> %load, ptr addrspace(1) %out
ret void
@@ -601,31 +549,18 @@ define amdgpu_kernel void @constant_load_v16i1(ptr addrspace(1) %out, ptr addrsp
; GFX12-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-TRUE16-LABEL: constant_load_v16i1:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3] nv
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1250-TRUE16-NEXT: s_endpgm
-;
-; GFX1250-FAKE16-LABEL: constant_load_v16i1:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] nv
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX1250-FAKE16-NEXT: s_endpgm
+; GFX1250-LABEL: constant_load_v16i1:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: global_load_u16 v1, v0, s[2:3] nv
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
store <16 x i1> %load, ptr addrspace(1) %out
ret void
@@ -5765,25 +5700,45 @@ define amdgpu_kernel void @constant_sextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX12-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-LABEL: constant_sextload_v2i1_to_v2i64:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v4, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u8 v0, v4, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_lshrrev_b32_e32 v2, 1, v0
-; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX1250-NEXT: v_bfe_i32 v2, v2, 0, 1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX1250-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-TRUE16-LABEL: constant_sextload_v2i1_to_v2i64:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-TRUE16-NEXT: v_nop
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: global_load_u8 v1, v4, s[2:3] nv
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX1250-TRUE16-NEXT: v_dual_lshrrev_b32 v2, 1, v1 :: v_dual_ashrrev_i32 v1, 31, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX1250-TRUE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1250-TRUE16-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-LABEL: constant_sextload_v2i1_to_v2i64:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-FAKE16-NEXT: v_nop
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: global_load_u8 v0, v4, s[2:3] nv
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1250-FAKE16-NEXT: s_endpgm
%load = load <2 x i1>, ptr addrspace(4) %in
%ext = sext <2 x i1> %load to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
@@ -6093,28 +6048,53 @@ define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX12-FAKE16-NEXT: global_store_b128 v6, v[0:3], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-LABEL: constant_sextload_v3i1_to_v3i64:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v5, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u8 v0, v5, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_dual_lshrrev_b32 v2, 2, v0 :: v_dual_lshrrev_b32 v4, 1, v0
-; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_bfe_i32 v6, v2, 0, 1
-; GFX1250-NEXT: v_bfe_i32 v2, v4, 0, 1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_dual_ashrrev_i32 v1, 31, v0 :: v_dual_ashrrev_i32 v7, 31, v6
-; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b64 v5, v[6:7], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v5, v[0:3], s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-TRUE16-LABEL: constant_sextload_v3i1_to_v3i64:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-TRUE16-NEXT: v_nop
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v5, 0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: global_load_u8 v1, v5, s[2:3] nv
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GFX1250-TRUE16-NEXT: v_dual_lshrrev_b32 v2, 2, v1 :: v_dual_lshrrev_b32 v4, 1, v1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v6, v2, 0, 1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v2, v4, 0, 1
+; GFX1250-TRUE16-NEXT: v_dual_ashrrev_i32 v1, 31, v0 :: v_dual_ashrrev_i32 v7, 31, v6
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-TRUE16-NEXT: s_clause 0x1
+; GFX1250-TRUE16-NEXT: global_store_b64 v5, v[6:7], s[0:1] offset:16
+; GFX1250-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[0:1]
+; GFX1250-TRUE16-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-LABEL: constant_sextload_v3i1_to_v3i64:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-FAKE16-NEXT: v_nop
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v5, 0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: global_load_u8 v0, v5, s[2:3] nv
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-FAKE16-NEXT: v_dual_lshrrev_b32 v2, 2, v0 :: v_dual_lshrrev_b32 v4, 1, v0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v6, v2, 0, 1
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v2, v4, 0, 1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_dual_ashrrev_i32 v1, 31, v0 :: v_dual_ashrrev_i32 v7, 31, v6
+; GFX1250-FAKE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-FAKE16-NEXT: s_clause 0x1
+; GFX1250-FAKE16-NEXT: global_store_b64 v5, v[6:7], s[0:1] offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v5, v[0:3], s[0:1]
+; GFX1250-FAKE16-NEXT: s_endpgm
%load = load <3 x i1>, ptr addrspace(4) %in
%ext = sext <3 x i1> %load to <3 x i64>
store <3 x i64> %ext, ptr addrspace(1) %out
@@ -6471,32 +6451,61 @@ define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX12-FAKE16-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-LABEL: constant_sextload_v4i1_to_v4i64:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v9, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u8 v0, v9, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_dual_lshrrev_b32 v2, 3, v0 :: v_dual_lshrrev_b32 v4, 2, v0
-; GFX1250-NEXT: v_lshrrev_b32_e32 v8, 1, v0
-; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250-NEXT: v_bfe_i32 v6, v2, 0, 1
-; GFX1250-NEXT: v_bfe_i32 v4, v4, 0, 1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX1250-NEXT: v_bfe_i32 v2, v8, 0, 1
-; GFX1250-NEXT: v_dual_ashrrev_i32 v7, 31, v6 :: v_dual_ashrrev_i32 v5, 31, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b128 v9, v[4:7], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v9, v[0:3], s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-TRUE16-LABEL: constant_sextload_v4i1_to_v4i64:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-TRUE16-NEXT: v_nop
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v9, 0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: global_load_u8 v1, v9, s[2:3] nv
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GFX1250-TRUE16-NEXT: v_dual_lshrrev_b32 v2, 3, v1 :: v_dual_lshrrev_b32 v4, 2, v1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 1, v1
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v6, v2, 0, 1
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX1250-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v2, v8, 0, 1
+; GFX1250-TRUE16-NEXT: v_dual_ashrrev_i32 v7, 31, v6 :: v_dual_ashrrev_i32 v5, 31, v4
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-TRUE16-NEXT: s_clause 0x1
+; GFX1250-TRUE16-NEXT: global_store_b128 v9, v[4:7], s[0:1] offset:16
+; GFX1250-TRUE16-NEXT: global_store_b128 v9, v[0:3], s[0:1]
+; GFX1250-TRUE16-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-LABEL: constant_sextload_v4i1_to_v4i64:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-FAKE16-NEXT: v_nop
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v9, 0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: global_load_u8 v0, v9, s[2:3] nv
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-FAKE16-NEXT: v_dual_lshrrev_b32 v2, 3, v0 :: v_dual_lshrrev_b32 v4, 2, v0
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 1, v0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v6, v2, 0, 1
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v2, v8, 0, 1
+; GFX1250-FAKE16-NEXT: v_dual_ashrrev_i32 v7, 31, v6 :: v_dual_ashrrev_i32 v5, 31, v4
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-FAKE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-FAKE16-NEXT: s_clause 0x1
+; GFX1250-FAKE16-NEXT: global_store_b128 v9, v[4:7], s[0:1] offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v9, v[0:3], s[0:1]
+; GFX1250-FAKE16-NEXT: s_endpgm
%load = load <4 x i1>, ptr addrspace(4) %in
%ext = sext <4 x i1> %load to <4 x i64>
store <4 x i64> %ext, ptr addrspace(1) %out
@@ -6688,36 +6697,68 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX12-FAKE16-NEXT: global_store_b128 v1, v[12:15], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-LABEL: constant_zextload_v8i1_to_v8i64:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v5, v1
-; GFX1250-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v9, v1
-; GFX1250-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v13, v1
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u8 v12, v1, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; GFX1250-NEXT: v_mov_b32_e32 v15, v1
-; GFX1250-NEXT: v_bfe_u32 v6, v12, 5, 1
-; GFX1250-NEXT: v_bfe_u32 v4, v12, 4, 1
-; GFX1250-NEXT: v_bfe_u32 v10, v12, 3, 1
-; GFX1250-NEXT: v_lshrrev_b32_e32 v2, 7, v0
-; GFX1250-NEXT: v_bfe_u32 v0, v0, 6, 1
-; GFX1250-NEXT: v_bfe_u32 v8, v12, 2, 1
-; GFX1250-NEXT: v_bfe_u32 v14, v12, 1, 1
-; GFX1250-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX1250-NEXT: s_clause 0x3
-; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
-; GFX1250-NEXT: global_store_b128 v1, v[4:7], s[0:1] offset:32
-; GFX1250-NEXT: global_store_b128 v1, v[8:11], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v1, v[12:15], s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-TRUE16-LABEL: constant_zextload_v8i1_to_v8i64:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-TRUE16-NEXT: v_nop
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v5, v1
+; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v9, v1
+; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v13, v1
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: global_load_u8 v8, v1, s[2:3] nv
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v8
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v15, v1
+; GFX1250-TRUE16-NEXT: v_bfe_u32 v6, v8, 5, 1
+; GFX1250-TRUE16-NEXT: v_bfe_u32 v4, v8, 4, 1
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 7, v0
+; GFX1250-TRUE16-NEXT: v_bfe_u32 v0, v0, 6, 1
+; GFX1250-TRUE16-NEXT: v_bfe_u32 v10, v8, 3, 1
+; GFX1250-TRUE16-NEXT: v_bfe_u32 v14, v8, 1, 1
+; GFX1250-TRUE16-NEXT: v_bfe_u32 v8, v8, 2, 1
+; GFX1250-TRUE16-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX1250-TRUE16-NEXT: s_clause 0x3
+; GFX1250-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
+; GFX1250-TRUE16-NEXT: global_store_b128 v1, v[4:7], s[0:1] offset:32
+; GFX1250-TRUE16-NEXT: global_store_b128 v1, v[8:11], s[0:1] offset:16
+; GFX1250-TRUE16-NEXT: global_store_b128 v1, v[12:15], s[0:1]
+; GFX1250-TRUE16-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-LABEL: constant_zextload_v8i1_to_v8i64:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-FAKE16-NEXT: v_nop
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v5, v1
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v9, v1
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v13, v1
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: global_load_u8 v12, v1, s[2:3] nv
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v12
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v15, v1
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v6, v12, 5, 1
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v4, v12, 4, 1
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v10, v12, 3, 1
+; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 7, v0
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v0, v0, 6, 1
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v8, v12, 2, 1
+; GFX1250-FAKE16-NEXT: v_bfe_u32 v14, v12, 1, 1
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX1250-FAKE16-NEXT: s_clause 0x3
+; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
+; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[4:7], s[0:1] offset:32
+; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[8:11], s[0:1] offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[12:15], s[0:1]
+; GFX1250-FAKE16-NEXT: s_endpgm
%load = load <8 x i1>, ptr addrspace(4) %in
%ext = zext <8 x i1> %load to <8 x i64>
store <8 x i64> %ext, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
index bf1d7d6f20fb0..db7f998270f16 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
@@ -294,27 +294,16 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr
; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
-; GFX1250-FAKE16-LABEL: incorrect_type_i16_block_count_x:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-FAKE16-NEXT: global_load_u16 v1, v0, s[0:1] offset:8 nv
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-FAKE16-NEXT: s_endpgm
-;
-; GFX1250-REAL16-LABEL: incorrect_type_i16_block_count_x:
-; GFX1250-REAL16: ; %bb.0:
-; GFX1250-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-REAL16-NEXT: v_nop
-; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT: global_load_u16 v0, v1, s[0:1] offset:8 nv
-; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: global_store_b16 v1, v0, s[2:3]
-; GFX1250-REAL16-NEXT: s_endpgm
+; GFX1250-LABEL: incorrect_type_i16_block_count_x:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1] offset:8 nv
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i16, ptr addrspace(4) %imp_arg_ptr
store i16 %load, ptr addrspace(1) %out
@@ -1164,3 +1153,6 @@ define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(pt
}
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1250-FAKE16: {{.*}}
+; GFX1250-REAL16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/spillv16.ll b/llvm/test/CodeGen/AMDGPU/spillv16.ll
index 8a5097372851d..99930a0cdb763 100644
--- a/llvm/test/CodeGen/AMDGPU/spillv16.ll
+++ b/llvm/test/CodeGen/AMDGPU/spillv16.ll
@@ -578,55 +578,30 @@ define void @spill_2xi16_from_v2i16() {
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-TRUE16-LABEL: spill_2xi16_from_v2i16:
-; GFX1250-TRUE16: ; %bb.0: ; %entry
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 offset:2 scope:SCOPE_SYS
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: s_clause 0x1 ; 4-byte Folded Spill
-; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:12 nv
-; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; 4-byte Folded Spill
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: ;;#ASMSTART
-; GFX1250-TRUE16-NEXT: ;;#ASMEND
-; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:12 th:TH_LOAD_LU nv ; 4-byte Folded Reload
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS
-; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS
-; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
-;
-; GFX1250-FAKE16-LABEL: spill_2xi16_from_v2i16:
-; GFX1250-FAKE16: ; %bb.0: ; %entry
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:2 scope:SCOPE_SYS
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: s_clause 0x1 ; 4-byte Folded Spill
-; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv
-; GFX1250-FAKE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:12 nv ; 4-byte Folded Spill
-; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-FAKE16-NEXT: ;;#ASMSTART
-; GFX1250-FAKE16-NEXT: ;;#ASMEND
-; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload
-; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS
-; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:12 th:TH_LOAD_LU nv ; 4-byte Folded Reload
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS
-; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0
-; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-LABEL: spill_2xi16_from_v2i16:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: scratch_load_u16 v0, off, s32 offset:2 scope:SCOPE_SYS
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: s_clause 0x1 ; 4-byte Folded Spill
+; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv
+; GFX1250-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:12 nv ; 4-byte Folded Spill
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: ;;#ASMSTART
+; GFX1250-NEXT: ;;#ASMEND
+; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS
+; GFX1250-NEXT: s_wait_storecnt 0x0
+; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:12 th:TH_LOAD_LU nv ; 4-byte Folded Reload
+; GFX1250-NEXT: s_wait_loadcnt 0x0
+; GFX1250-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS
+; GFX1250-NEXT: s_wait_storecnt 0x0
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
entry:
%alloca = alloca <2 x i16>, i32 2, align 1, addrspace(5)
@@ -716,21 +691,21 @@ define void @spill_2xi16_from_v2i16_one_free_reg() {
; GFX1250-TRUE16: ; %bb.0: ; %entry
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: scratch_load_u16 v7, off, s32 offset:2 scope:SCOPE_SYS
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 offset:2 scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; 4-byte Folded Spill
; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT: scratch_load_u16 v7, off, s32 scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: ;;#ASMSTART
; GFX1250-TRUE16-NEXT: ;;#ASMEND
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.l
-; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS
-; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload
+; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
+; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v7, s32 scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
>From d15765815999d0a8b13dcfeef396e1224121655d Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Fri, 24 Jul 2026 12:58:18 -0500
Subject: [PATCH 2/5] Variable rename, for consistency
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 11f8ce34d981c..e06e3b57236a9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8582,10 +8582,10 @@ void SIInstrInfo::moveToVALUImpl(
// eliminated.
addUsersToMoveToVALUWorklist(DstReg, MRI, Worklist);
unsigned SrcSubReg = Inst.getOperand(1).getSubReg();
- for (MachineOperand &Use :
+ for (MachineOperand &UseMO :
make_early_inc_range(MRI.use_operands(DstReg))) {
- Use.setSubReg(RI.composeSubRegIndices(SrcSubReg, Use.getSubReg()));
- Use.setReg(NewDstReg);
+ UseMO.setSubReg(RI.composeSubRegIndices(SrcSubReg, UseMO.getSubReg()));
+ UseMO.setReg(NewDstReg);
}
MRI.clearKillFlags(NewDstReg);
>From d100586060e303ab45aef8dbc175b31eb7f278f2 Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Fri, 24 Jul 2026 12:59:59 -0500
Subject: [PATCH 3/5] Legalise VALU true16 on all invocations of
legalizeOperands
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index e06e3b57236a9..5e40e0ecc6a05 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7513,6 +7513,10 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
MachineRegisterInfo &MRI = MF.getRegInfo();
MachineBasicBlock *CreatedBB = nullptr;
+ // Legalize True16
+ if (ST.useRealTrue16Insts())
+ legalizeOperandsVALUt16(MI, MRI);
+
// Legalize VOP2
if (isVOP2(MI) || isVOPC(MI)) {
legalizeOperandsVOP2(MRI, MI);
@@ -7902,8 +7906,7 @@ void SIInstrInfo::legalizeOperandsVALUt16(MachineInstr &MI, unsigned OpIdx,
const TargetRegisterClass *CurrSRC =
RI.getSubRegisterClass(CurrRC, Op.getSubReg());
- if (RI.getRegSizeInBits(*CurrSRC) == 16 &&
- RI.getRegSizeInBits(*ExpectedRC) == 32) {
+ if (RI.getMatchingSuperRegClass(ExpectedRC, CurrSRC, AMDGPU::lo16)) {
const DebugLoc &DL = MI.getDebugLoc();
Register NewDstReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
Register Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
@@ -8452,7 +8455,6 @@ void SIInstrInfo::moveToVALUImpl(
.add(Inst.getOperand(0))
.add(Inst.getOperand(1));
}
- legalizeOperandsVALUt16(*NewInstr, MRI);
legalizeOperands(*NewInstr, MDT);
int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC, /*TRI=*/nullptr);
const MachineOperand &SCCOp = Inst.getOperand(SCCIdx);
@@ -8519,7 +8521,6 @@ void SIInstrInfo::moveToVALUImpl(
.addImm(0) // omod
.addImm(0); // opsel0
MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);
- legalizeOperandsVALUt16(*NewInstr, MRI);
legalizeOperands(*NewInstr, MDT);
addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist);
Inst.eraseFromParent();
@@ -8542,7 +8543,6 @@ void SIInstrInfo::moveToVALUImpl(
if (AMDGPU::hasNamedOperand(NewOpcode, AMDGPU::OpName::op_sel))
NewInstr.addImm(0); // opsel0
MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);
- legalizeOperandsVALUt16(*NewInstr, MRI);
legalizeOperands(*NewInstr, MDT);
addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist);
Inst.eraseFromParent();
@@ -8736,8 +8736,6 @@ void SIInstrInfo::moveToVALUImpl(
}
fixImplicitOperands(*NewInstr);
- legalizeOperandsVALUt16(*NewInstr, MRI);
-
// Legalize the operands
legalizeOperands(*NewInstr, MDT);
if (NewDstReg)
>From 9165cfe942bf0c3077f82bebef4237cf7d4ee77f Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Fri, 24 Jul 2026 14:46:30 -0500
Subject: [PATCH 4/5] Added more tests
---
.../AMDGPU/fix-sgpr-copies-f16-true16.mir | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
index 1b82911f60249..b9f0a5fc2674e 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
@@ -157,6 +157,22 @@ body: |
%2:vgpr_16 = V_TRUNC_F16_t16_e64 0, %1:sreg_32, 0, 0, 0, implicit $mode, implicit $exec
...
+---
+name: copy_vgpr16_sreg32_usedby_valu32
+body: |
+ bb.0:
+ ; GCN-LABEL: name: copy_vgpr16_sreg32_usedby_valu32
+ ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF1]], %subreg.lo16, [[DEF2]], %subreg.hi16
+ ; GCN-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[DEF]], [[REG_SEQUENCE]], implicit $exec
+ %0:vgpr_32 = IMPLICIT_DEF
+ %1:vgpr_16 = IMPLICIT_DEF
+ %2:sreg_32 = COPY %1:vgpr_16
+ %3:vgpr_32 = V_XOR_B32_e64 %0:vgpr_32, %2:sreg_32, implicit $exec
+...
+
---
name: S_FMAC_F16
body: |
@@ -365,3 +381,35 @@ body: |
%2:sreg_32 = COPY %1.hi16
%3:vgpr_16 = V_OR_B16_t16_e64 0, %0.lo16, 0, killed %2, 0, implicit $exec
...
+
+---
+name: v_or_b16_compose_sub1_lo16
+body: |
+ bb.0:
+ ; GCN-LABEL: name: v_or_b16_compose_sub1_lo16
+ ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF1]].sub1_lo16
+ ; GCN-NEXT: [[V_OR_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_OR_B16_t16_e64 0, [[DEF]].lo16, 0, [[COPY]], 0, implicit $exec
+ %0:vgpr_32 = IMPLICIT_DEF
+ %1:vreg_64 = IMPLICIT_DEF
+ %2:sreg_64 = COPY %1.sub1
+ %3:vgpr_16 = COPY %2.lo16
+ %4:vgpr_16 = V_OR_B16_t16_e64 0, %0.lo16, 0, %3, 0, implicit $exec
+...
+
+---
+name: v_or_b32_compose_sub1_sub0
+body: |
+ bb.0:
+ ; GCN-LABEL: name: v_or_b32_compose_sub1_sub0
+ ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF1]].sub1
+ ; GCN-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[DEF]], [[COPY]], implicit $exec
+ %0:vgpr_32 = IMPLICIT_DEF
+ %1:vreg_64 = IMPLICIT_DEF
+ %2:sreg_64 = COPY %1.sub1
+ %3:sreg_32 = COPY %2.sub0
+ %4:vgpr_32 = V_OR_B32_e64 %0, %3, implicit $exec
+...
>From 9c74ddaf64cba22428fe96447fd1a8cca9e656c5 Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Fri, 24 Jul 2026 14:48:15 -0500
Subject: [PATCH 5/5] formatting
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 5e40e0ecc6a05..04dfba5ed7ca9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8584,7 +8584,8 @@ void SIInstrInfo::moveToVALUImpl(
unsigned SrcSubReg = Inst.getOperand(1).getSubReg();
for (MachineOperand &UseMO :
make_early_inc_range(MRI.use_operands(DstReg))) {
- UseMO.setSubReg(RI.composeSubRegIndices(SrcSubReg, UseMO.getSubReg()));
+ UseMO.setSubReg(
+ RI.composeSubRegIndices(SrcSubReg, UseMO.getSubReg()));
UseMO.setReg(NewDstReg);
}
MRI.clearKillFlags(NewDstReg);
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