[llvm] [mlir] [NVPTX] Add Rubin extensions to tcgen05.commit (PR #211577)

[Alex MacLean via llvm-commits]

================
@@ -2634,8 +2634,17 @@ For more information, refer to the [PTX ISA](https://docs.nvidia.com/cuda/parall
 ```llvm
 declare void @llvm.nvvm.tcgen05.commit.{cg1,cg2}(ptr %mbar)
 declare void @llvm.nvvm.tcgen05.commit.shared.{cg1,cg2}(ptr addrspace(3) %mbar)
-declare void @llvm.nvvm.tcgen05.commit.mc.{cg1,cg2}(ptr %mbar, i16 %mc)
-declare void @llvm.nvvm.tcgen05.commit.mc.shared.{cg1,cg2}(ptr addrspace(3) %mbar, i16 %mc)
+declare void @llvm.nvvm.tcgen05.commit.mc.{cg1,cg2}.i16(ptr %mbar, i16 %mc)
+declare void @llvm.nvvm.tcgen05.commit.mc.shared.{cg1,cg2}.i16(ptr addrspace(3) %mbar, i16 %mc)
----------------
AlexMaclean wrote:

Can we get rid of the shared/generic variants and use an overloaded intrinsic? This would half the number of intrinsics in this family. 

https://github.com/llvm/llvm-project/pull/211577