[llvm] [NFC][VPlan][Tests] Some CHECKs cleanup (PR #211425)
Andrei Elovikov via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 24 07:38:47 PDT 2026
https://github.com/eas updated https://github.com/llvm/llvm-project/pull/211425
>From ddb2de955fcaceec6da877682cd78857a30cfbf9 Mon Sep 17 00:00:00 2001
From: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: Wed, 22 Jul 2026 15:11:58 -0700
Subject: [PATCH 1/3] [NFC][VPlan][Tests] Some CHECKs cleanup
* Fix RUN-line in `VPlan/AArch64/call-decisions.ll` to work with UTC
"; -RUN" was resulting in
```
Error: Failed to update test <...>/call-decisions.ll
Traceback (most recent call last):
File "<...>/update_analyze_test_checks.py", line 228, in main
update_test(opt_basename, ti)
File "<...>/update_analyze_test_checks.py", line 131, in update_test
check_label_prefix = "VPlan for loop in " if regex == common.VPLAN_RE else ""
UnboundLocalError: local variable 'regex' referenced before assignment
```
* Regenerate CHECKs in VPlan/X86/vplan-vp-intrinsics.ll with UTC
* Split VPlan/interleave-and-scalarize-only.ll in two (VPlan/LLVM dumps) to be able to use UTC
* Remove stale `CHECK-NOT`
Probably missed in `-debug` -> `-vplan-print-after` transition.
---
.../VPlan/AArch64/call-decisions.ll | 10 +-
.../VPlan/X86/vplan-vp-intrinsics.ll | 119 ++--
.../LoopVectorize/VPlan/icmp-uniforms.ll | 2 -
.../VPlan/interleave-and-scalarize-only.ll | 661 +++++++++++-------
.../interleave-and-scalarize-only.ll | 479 +++++++++++++
5 files changed, 942 insertions(+), 329 deletions(-)
create mode 100644 llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/call-decisions.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/call-decisions.ll
index f61f64ab7d36b..05066c6a6d65a 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/call-decisions.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/call-decisions.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "middle.block:" --version 6
-; -RUN: opt -mattr=+neon -vector-library=LIBMVEC -passes=inject-tli-mappings,loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S -disable-output -vplan-print-after=makeCallWideningDecisions %s 2>&1 | FileCheck %s
+; RUN: opt -mattr=+neon -vector-library=LIBMVEC -passes=inject-tli-mappings,loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S -disable-output -vplan-print-after=makeCallWideningDecisions %s 2>&1 | FileCheck %s
target triple = "arm64-apple-macosx"
@@ -25,11 +25,11 @@ define void @pick_wide_call(ptr noalias %in.ptr, ptr noalias %out.ptr) {
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%in.gep> = getelementptr inbounds ir<%in.ptr>, ir<%iv>
-; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = vector-pointer inbounds ir<%in.gep>
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = vector-pointer inbounds ir<%in.gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%in> = load vp<[[VP4]]>
; CHECK-NEXT: WIDEN-CALL ir<%call> = call @acos(ir<%in>) (using library function: _ZGVnN2v_acos)
; CHECK-NEXT: CLONE ir<%out.gep> = getelementptr inbounds ir<%out.ptr>, ir<%iv>
-; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%out.gep>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%out.gep>, ir<1>
; CHECK-NEXT: WIDEN store vp<[[VP5]]>, ir<%call>
; CHECK-NEXT: EMIT ir<%iv.next> = add nuw nsw ir<%iv>, ir<1>
; CHECK-NEXT: CLONE ir<%exitcond> = icmp eq ir<%iv.next>, ir<1000>
@@ -79,11 +79,11 @@ define void @pick_intrinsic_call(ptr noalias %in.ptr, ptr noalias %out.ptr) {
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%in.gep> = getelementptr inbounds ir<%in.ptr>, ir<%iv>
-; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = vector-pointer inbounds ir<%in.gep>
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = vector-pointer inbounds ir<%in.gep>, ir<1>
; CHECK-NEXT: WIDEN ir<%in> = load vp<[[VP4]]>
; CHECK-NEXT: WIDEN-INTRINSIC ir<%call> = call llvm.umin(ir<100>, ir<%in>)
; CHECK-NEXT: CLONE ir<%out.gep> = getelementptr inbounds ir<%out.ptr>, ir<%iv>
-; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%out.gep>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%out.gep>, ir<1>
; CHECK-NEXT: WIDEN store vp<[[VP5]]>, ir<%call>
; CHECK-NEXT: EMIT ir<%iv.next> = add nuw nsw ir<%iv>, ir<1>
; CHECK-NEXT: CLONE ir<%exitcond> = icmp eq ir<%iv.next>, ir<1000>
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
index f1f6a2c1c80da..323f5e2b257c5 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "middle.block" --version 6
; RUN: opt -passes=loop-vectorize -vplan-print-after=printOptimizedVPlan -force-vector-width=4 \
; RUN: -force-tail-folding-style=data-with-evl \
; RUN: -tail-folding-policy=must-fold-tail \
@@ -9,65 +10,77 @@
; RUN: -mtriple=x86_64 -mattr=+avx512f -disable-output < %s 2>&1 | FileCheck --check-prefix=NO-VP %s
define void @foo(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) {
-; IF-EVL: VPlan 'Initial VPlan for VF={4},UF>=1' {
-; IF-EVL-NEXT: Live-in vp<[[VF:%[0-9]+]]> = VF
-; IF-EVL-NEXT: Live-in vp<[[VFUF:%[0-9]+]]> = VF * UF
-; IF-EVL-NEXT: Live-in vp<[[VTC:%[0-9]+]]> = vector-trip-count
-; IF-EVL-NEXT: Live-in vp<[[BETC:%[0-9]+]]> = backedge-taken count
+; IF-EVL-LABEL: VPlan for loop in 'foo'
+; IF-EVL: VPlan 'Initial VPlan for VF={4},UF>=1' {
+; IF-EVL-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; IF-EVL-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; IF-EVL-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; IF-EVL-NEXT: Live-in vp<[[VP3:%[0-9]+]]> = backedge-taken count
; IF-EVL-EMPTY:
-; IF-EVL: vector.ph:
-; IF-EVL-NEXT: Successor(s): vector loop
+; IF-EVL-NEXT: ir-bb<entry>:
+; IF-EVL-NEXT: Successor(s): scalar.ph, vector.ph
; IF-EVL-EMPTY:
-; IF-EVL-NEXT: <x1> vector loop: {
-; IF-EVL-NEXT: vp<[[IV:%[0-9]+]]> = CANONICAL-IV
+; IF-EVL-NEXT: vector.ph:
+; IF-EVL-NEXT: Successor(s): vector loop
; IF-EVL-EMPTY:
-; IF-EVL-NEXT: vector.body:
-; IF-EVL-NEXT: EMIT vp<[[VIV:%[0-9]+]]> = WIDEN-CANONICAL-INDUCTION nuw vp<[[IV]]>
-; IF-EVL-NEXT: EMIT vp<[[MASK:%[0-9]+]]> = icmp ule vp<[[VIV]]>, vp<[[BETC]]>
-; IF-EVL-NEXT: vp<[[ST:%[0-9]+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>, vp<[[VF]]>
-; IF-EVL-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%b>, vp<[[ST]]>
-; IF-EVL-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer inbounds ir<[[GEP1]]>
-; IF-EVL-NEXT: WIDEN ir<[[LD1:%.+]]> = load vp<[[PTR1]]>, vp<[[MASK]]>
-; IF-EVL-NEXT: CLONE ir<[[GEP2:%.+]]> = getelementptr inbounds ir<%c>, vp<[[ST]]>
-; IF-EVL-NEXT: vp<[[PTR2:%[0-9]+]]> = vector-pointer inbounds ir<[[GEP2]]>
-; IF-EVL-NEXT: WIDEN ir<[[LD2:%.+]]> = load vp<[[PTR2]]>, vp<[[MASK]]>
-; IF-EVL-NEXT: WIDEN ir<[[ADD:%.+]]> = add nsw ir<[[LD2]]>, ir<[[LD1]]>
-; IF-EVL-NEXT: CLONE ir<[[GEP3:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
-; IF-EVL-NEXT: vp<[[PTR3:%[0-9]+]]> = vector-pointer inbounds ir<[[GEP3]]>
-; IF-EVL-NEXT: WIDEN store vp<[[PTR3]]>, ir<[[ADD]]>, vp<[[MASK]]>
-; IF-EVL-NEXT: EMIT vp<[[IV_NEXT:%.+]]> = add vp<[[IV]]>, vp<[[VFUF]]>
-; IF-EVL-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>
-; IF-EVL-NEXT: No successors
-; IF-EVL-NEXT: }
-
-; NO-VP: VPlan 'Initial VPlan for VF={4},UF>=1' {
-; NO-VP-NEXT: Live-in vp<[[VF:%[0-9]+]]> = VF
-; NO-VP-NEXT: Live-in vp<[[VFUF:%[0-9]+]]> = VF * UF
-; NO-VP-NEXT: Live-in vp<[[VTC:%[0-9]+]]> = vector-trip-count
-; NO-VP-NEXT: Live-in ir<%N> = original trip-count
+; IF-EVL-NEXT: <x1> vector loop: {
+; IF-EVL-NEXT: vp<[[VP4:%[0-9]+]]> = CANONICAL-IV
+; IF-EVL-EMPTY:
+; IF-EVL-NEXT: vector.body:
+; IF-EVL-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = WIDEN-CANONICAL-INDUCTION nuw vp<[[VP4]]>
+; IF-EVL-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = icmp ule vp<[[VP6]]>, vp<[[VP3]]>
+; IF-EVL-NEXT: vp<[[VP8:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
+; IF-EVL-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%b>, vp<[[VP8]]>
+; IF-EVL-NEXT: vp<[[VP9:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
+; IF-EVL-NEXT: WIDEN ir<%0> = load vp<[[VP9]]>, vp<[[VP7]]>
+; IF-EVL-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%c>, vp<[[VP8]]>
+; IF-EVL-NEXT: vp<[[VP10:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx2>, ir<1>
+; IF-EVL-NEXT: WIDEN ir<%1> = load vp<[[VP10]]>, vp<[[VP7]]>
+; IF-EVL-NEXT: WIDEN ir<%add> = add nsw ir<%1>, ir<%0>
+; IF-EVL-NEXT: CLONE ir<%arrayidx4> = getelementptr inbounds ir<%a>, vp<[[VP8]]>
+; IF-EVL-NEXT: vp<[[VP11:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx4>, ir<1>
+; IF-EVL-NEXT: WIDEN store vp<[[VP11]]>, ir<%add>, vp<[[VP7]]>
+; IF-EVL-NEXT: EMIT vp<%index.next> = add vp<[[VP4]]>, vp<[[VP1]]>
+; IF-EVL-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; IF-EVL-NEXT: No successors
+; IF-EVL-NEXT: }
+; IF-EVL-NEXT: Successor(s): middle.block
+;
+; NO-VP-LABEL: VPlan for loop in 'foo'
+; NO-VP: VPlan 'Initial VPlan for VF={4},UF>=1' {
+; NO-VP-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; NO-VP-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; NO-VP-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; NO-VP-NEXT: Live-in ir<%N> = original trip-count
; NO-VP-EMPTY:
-; NO-VP: vector.ph:
-; NO-VP-NEXT: Successor(s): vector loop
+; NO-VP-NEXT: ir-bb<entry>:
+; NO-VP-NEXT: Successor(s): scalar.ph, vector.ph
; NO-VP-EMPTY:
-; NO-VP-NEXT: <x1> vector loop: {
-; NO-VP-NEXT: vp<[[IV:%[0-9]+]]> = CANONICAL-IV
+; NO-VP-NEXT: vector.ph:
+; NO-VP-NEXT: Successor(s): vector loop
; NO-VP-EMPTY:
-; NO-VP-NEXT: vector.body:
-; NO-VP-NEXT: vp<[[ST:%[0-9]+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>, vp<[[VF]]>
-; NO-VP-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%b>, vp<[[ST]]>
-; NO-VP-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer inbounds ir<[[GEP1]]>
-; NO-VP-NEXT: WIDEN ir<[[LD1:%.+]]> = load vp<[[PTR1]]>
-; NO-VP-NEXT: CLONE ir<[[GEP2:%.+]]> = getelementptr inbounds ir<%c>, vp<[[ST]]>
-; NO-VP-NEXT: vp<[[PTR2:%[0-9]+]]> = vector-pointer inbounds ir<[[GEP2]]>
-; NO-VP-NEXT: WIDEN ir<[[LD2:%.+]]> = load vp<[[PTR2]]>
-; NO-VP-NEXT: WIDEN ir<[[ADD:%.+]]> = add nsw ir<[[LD2]]>, ir<[[LD1]]>
-; NO-VP-NEXT: CLONE ir<[[GEP3:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
-; NO-VP-NEXT: vp<[[PTR3:%[0-9]+]]> = vector-pointer inbounds ir<[[GEP3]]>
-; NO-VP-NEXT: WIDEN store vp<[[PTR3]]>, ir<[[ADD]]>
-; NO-VP-NEXT: EMIT vp<[[IV_NEXT:%.+]]> = add nuw vp<[[IV]]>, vp<[[VFUF]]>
-; NO-VP-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]>
-; NO-VP-NEXT: No successors
-; NO-VP-NEXT: }
+; NO-VP-NEXT: <x1> vector loop: {
+; NO-VP-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
+; NO-VP-EMPTY:
+; NO-VP-NEXT: vector.body:
+; NO-VP-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
+; NO-VP-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%b>, vp<[[VP4]]>
+; NO-VP-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx>, ir<1>
+; NO-VP-NEXT: WIDEN ir<%0> = load vp<[[VP5]]>
+; NO-VP-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%c>, vp<[[VP4]]>
+; NO-VP-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx2>, ir<1>
+; NO-VP-NEXT: WIDEN ir<%1> = load vp<[[VP6]]>
+; NO-VP-NEXT: WIDEN ir<%add> = add nsw ir<%1>, ir<%0>
+; NO-VP-NEXT: CLONE ir<%arrayidx4> = getelementptr inbounds ir<%a>, vp<[[VP4]]>
+; NO-VP-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx4>, ir<1>
+; NO-VP-NEXT: WIDEN store vp<[[VP7]]>, ir<%add>
+; NO-VP-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; NO-VP-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; NO-VP-NEXT: No successors
+; NO-VP-NEXT: }
+; NO-VP-NEXT: Successor(s): middle.block
+;
+
entry:
br label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll b/llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
index 0ff23bb915cfd..57930dc37b36b 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
@@ -8,8 +8,6 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
; PR30627. Check that a compare instruction with more than one use is not
; recognized as uniform and is vectorized.
;
-; CHECK-NOT: Found uniform instruction: %cond = icmp slt i64 %i.next, %n
-;
define i32 @more_than_one_use(ptr %a, i64 %n) {
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
index a48360fe74124..4120311e552e2 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
@@ -1,51 +1,59 @@
-; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -vplan-print-after=printOptimizedVPlan -disable-output %s 2>&1 | FileCheck --check-prefix=DBG %s
-; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -vplan-print-after=printOptimizedVPlan -disable-output %s 2>&1 | FileCheck %s
-; DBG-LABEL: 'test_scalarize_call'
-; DBG: VPlan 'Initial VPlan for VF={1},UF>=1' {
-; DBG-NEXT: Live-in vp<[[VF:%.+]]> = VF
-; DBG-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
-; DBG-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
-; DBG-NEXT: vp<[[TC:%.+]]> = original trip-count
-; DBG-EMPTY:
-; DBG-NEXT: ir-bb<entry>:
-; DBG-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (1000 + (-1 * %start))
-; DBG-NEXT: Successor(s): scalar.ph, vector.ph
-; DBG-EMPTY:
-; DBG-NEXT: vector.ph:
-; DBG-NEXT: vp<[[END:%.+]]> = DERIVED-IV ir<%start> + vp<[[VEC_TC]]> * ir<1>
-; DBG-NEXT: Successor(s): vector loop
-; DBG-EMPTY:
-; DBG-NEXT: <x1> vector loop: {
-; DBG-NEXT: vp<[[CAN_IV:%.+]]> = CANONICAL-IV
-; DBG-EMPTY:
-; DBG-NEXT: vector.body:
-; DBG-NEXT: vp<[[DERIVED_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[CAN_IV]]> * ir<1>
-; DBG-NEXT: vp<[[IV_STEPS:%.]]> = SCALAR-STEPS vp<[[DERIVED_IV]]>, ir<1>, vp<[[VF]]>
-; DBG-NEXT: CLONE ir<%min> = call @llvm.smin.i32(vp<[[IV_STEPS]]>, ir<65535>)
-; DBG-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%dst>, vp<[[IV_STEPS]]>
-; DBG-NEXT: CLONE store ir<%min>, ir<%arrayidx>
-; DBG-NEXT: EMIT vp<[[INC:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
-; DBG-NEXT: EMIT branch-on-count vp<[[INC]]>, vp<[[VEC_TC]]>
-; DBG-NEXT: No successors
-; DBG-NEXT: }
;
define void @test_scalarize_call(i32 %start, ptr %dst) {
-; CHECK-LABEL: @test_scalarize_call(
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
-; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 %start, [[INDEX]]
-; CHECK-NEXT: [[INDUCTION1:%.*]] = add i32 [[OFFSET_IDX]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.smin.i32(i32 [[OFFSET_IDX]], i32 65535)
-; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[INDUCTION1]], i32 65535)
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[INDUCTION1]]
-; CHECK-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 8
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP4]], align 8
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], %n.vec
-; CHECK-NEXT: br i1 [[TMP5]], label %middle.block, label %vector.body
-; CHECK: middle.block:
+; CHECK-LABEL: VPlan for loop in 'test_scalarize_call'
+; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1000 + (-1 * %start))
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%start> + vp<[[VP2]]> * ir<1>
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = DERIVED-IV ir<%start> + vp<[[VP5]]> * ir<1>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: CLONE ir<%min> = call @llvm.smin.i32(vp<[[VP7]]>, ir<65535>)
+; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%dst>, vp<[[VP7]]>
+; CHECK-NEXT: CLONE store ir<%min>, ir<%arrayidx>
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]>
+; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
+; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<exit>:
+; CHECK-NEXT: No successors
+; CHECK-EMPTY:
+; CHECK-NEXT: scalar.ph:
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%start>, ir-bb<entry> ]
+; CHECK-NEXT: Successor(s): ir-bb<loop>
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<loop>:
+; CHECK-NEXT: IR %iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK-NEXT: IR %min = tail call i32 @llvm.smin.i32(i32 %iv, i32 65535)
+; CHECK-NEXT: IR %arrayidx = getelementptr inbounds i32, ptr %dst, i32 %iv
+; CHECK-NEXT: IR store i32 %min, ptr %arrayidx, align 8
+; CHECK-NEXT: IR %iv.next = add nsw i32 %iv, 1
+; CHECK-NEXT: IR %tobool.not = icmp eq i32 %iv.next, 1000
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
;
entry:
br label %loop
@@ -63,101 +71,73 @@ exit:
ret void
}
-
-
-; DBG-LABEL: 'test_scalarize_with_branch_cond'
-
-; DBG: Live-in vp<[[VFxUF:%.+]]> = VF * UF
-; DBG-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
-; DBG-NEXT: Live-in ir<1000> = original trip-count
-; DBG-EMPTY:
-; DBG-NEXT: ir-bb<entry>:
-; DBG-NEXT: Successor(s): scalar.ph, vector.ph
-; DBG-EMPTY:
-; DBG-NEXT: vector.ph:
-; DBG-NEXT: vp<[[END:%.+]]> = DERIVED-IV ir<false> + vp<[[VEC_TC]]> * ir<true>
-; DBG-NEXT: Successor(s): vector loop
-; DBG-EMPTY:
-; DBG-NEXT: <x1> vector loop: {
-; DBG-NEXT: vp<[[CAN_IV:%.+]]> = CANONICAL-IV
-; DBG-EMPTY:
-; DBG-NEXT: vector.body:
-; DBG-NEXT: vp<[[DERIVED_IV:%.+]]> = DERIVED-IV ir<false> + vp<[[CAN_IV]]> * ir<true>
-; DBG-NEXT: vp<[[STEPS1:%.+]]> = SCALAR-STEPS vp<[[DERIVED_IV]]>, ir<true>
-; DBG-NEXT: Successor(s): pred.store
-; DBG-EMPTY:
-; DBG-NEXT: <xVFxUF> pred.store: {
-; DBG-NEXT: pred.store.entry:
-; DBG-NEXT: BRANCH-ON-MASK vp<[[STEPS1]]>
-; DBG-NEXT: Successor(s): pred.store.if, pred.store.continue
-; DBG-EMPTY:
-; DBG-NEXT: pred.store.if:
-; DBG-NEXT: vp<[[STEPS2:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
-; DBG-NEXT: CLONE ir<%gep.src> = getelementptr inbounds ir<%src>, vp<[[STEPS2]]>
-; DBG-NEXT: CLONE ir<%l> = load ir<%gep.src>
-; DBG-NEXT: CLONE ir<%gep.dst> = getelementptr inbounds ir<%dst>, vp<[[STEPS2]]>
-; DBG-NEXT: CLONE store ir<%l>, ir<%gep.dst>
-; DBG-NEXT: Successor(s): pred.store.continue
-; DBG-EMPTY:
-; DBG-NEXT: pred.store.continue:
-; DBG-NEXT: No successors
-; DBG-NEXT: }
-; DBG-NEXT: Successor(s): cond.false.1
-; DBG-EMPTY:
-; DBG-NEXT: cond.false.1:
-; DBG-NEXT: EMIT vp<[[CAN_IV_INC:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
-; DBG-NEXT: EMIT branch-on-count vp<[[CAN_IV_INC]]>, vp<[[VEC_TC]]>
-; DBG-NEXT: No successors
-; DBG-NEXT: }
-; DBG-NEXT: Successor(s): middle.block
-; DBG-EMPTY:
-; DBG-NEXT: middle.block:
-; DBG-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<1000>, vp<[[VEC_TC]]>
-; DBG-NEXT: EMIT branch-on-cond vp<[[CMP]]>
-; DBG-NEXT: Successor(s): ir-bb<exit>, scalar.ph
-; DBG-EMPTY:
-; DBG-NEXT: ir-bb<exit>:
-; DBG-NEXT: No successors
-; DBG-EMPTY:
-; DBG-NEXT: scalar.ph:
-; DBG-NEXT: EMIT-SCALAR vp<[[RESUME1:%.+]]> = phi [ vp<[[VEC_TC]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
-; DBG-NEXT: EMIT-SCALAR vp<[[RESUME2:%.+]]>.1 = phi [ vp<[[END]]>, middle.block ], [ ir<false>, ir-bb<entry> ]
-; DBG-NEXT: Successor(s): ir-bb<loop.header>
-; DBG-EMPTY:
-; DBG-NEXT: ir-bb<loop.header>:
-; DBG-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] (extra operand: vp<[[RESUME1]]> from scalar.ph)
-; DBG-NEXT: IR %d = phi i1 [ false, %entry ], [ %d.next, %loop.latch ] (extra operand: vp<[[RESUME2]]>.1 from scalar.ph)
-; DBG-NEXT: IR %d.next = xor i1 %d, true
-; DBG-NEXT: No successors
-; DBG-NEXT: }
-
define void @test_scalarize_with_branch_cond(ptr %src, ptr %dst) {
-; CHECK-LABEL: @test_scalarize_with_branch_cond(
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %pred.store.continue4 ]
-; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDEX]] to i1
-; CHECK-NEXT: [[INDUCTION3:%.*]] = add i1 [[TMP0]], true
-; CHECK-NEXT: br i1 [[TMP0]], label %pred.store.if, label %pred.store.continue
-; CHECK: pred.store.if:
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr %src, i64 [[INDEX]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr %dst, i64 [[INDEX]]
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP1]], align 4
-; CHECK-NEXT: br label %pred.store.continue
-; CHECK: pred.store.continue:
-; CHECK-NEXT: br i1 [[INDUCTION3]], label %pred.store.if3, label %pred.store.continue4
-; CHECK: pred.store.if3:
-; CHECK-NEXT: [[INDUCTION5:%.*]] = add i64 [[INDEX]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr %src, i64 [[INDUCTION5]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr %dst, i64 [[INDUCTION5]]
-; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP2]], align 4
-; CHECK-NEXT: br label %pred.store.continue4
-; CHECK: pred.store.continue4:
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
-; CHECK-NEXT: br i1 [[TMP9]], label %middle.block, label %vector.body
-; CHECK: middle.block:
+; CHECK-LABEL: VPlan for loop in 'test_scalarize_with_branch_cond'
+; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: Live-in ir<1000> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = DERIVED-IV ir<false> + vp<[[VP2]]> * ir<true>
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = DERIVED-IV ir<false> + vp<[[VP4]]> * ir<true>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = SCALAR-STEPS vp<[[VP5]]>, ir<true>, vp<[[VP0]]>
+; CHECK-NEXT: Successor(s): pred.store
+; CHECK-EMPTY:
+; CHECK-NEXT: <xVFxUF> pred.store: {
+; CHECK-NEXT: pred.store.entry:
+; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP6]]>
+; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.store.if:
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: CLONE ir<%gep.src> = getelementptr inbounds ir<%src>, vp<[[VP7]]>
+; CHECK-NEXT: CLONE ir<%l> = load ir<%gep.src>
+; CHECK-NEXT: CLONE ir<%gep.dst> = getelementptr inbounds ir<%dst>, vp<[[VP7]]>
+; CHECK-NEXT: CLONE store ir<%l>, ir<%gep.dst>
+; CHECK-NEXT: Successor(s): pred.store.continue
+; CHECK-EMPTY:
+; CHECK-NEXT: pred.store.continue:
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): cond.false.1
+; CHECK-EMPTY:
+; CHECK-NEXT: cond.false.1:
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]>
+; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
+; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<exit>:
+; CHECK-NEXT: No successors
+; CHECK-EMPTY:
+; CHECK-NEXT: scalar.ph:
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val>.1 = phi [ vp<[[VP3]]>, middle.block ], [ ir<false>, ir-bb<entry> ]
+; CHECK-NEXT: Successor(s): ir-bb<loop.header>
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<loop.header>:
+; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK-NEXT: IR %d = phi i1 [ false, %entry ], [ %d.next, %loop.latch ] (extra operand: vp<%bc.resume.val>.1 from scalar.ph)
+; CHECK-NEXT: IR %d.next = xor i1 %d, true
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
;
entry:
br label %loop.header
@@ -187,68 +167,61 @@ exit:
; Make sure the widened induction gets replaced by scalar-steps for plans
; including the scalar VF, if it is used in first-order recurrences.
-; DBG-LABEL: 'first_order_recurrence_using_induction'
-; DBG: VPlan 'Initial VPlan for VF={1},UF>=1' {
-; DBG-NEXT: Live-in vp<[[VF:%.+]]> = VF
-; DBG-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
-; DBG-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count
-; DBG-NEXT: vp<[[TC:%.+]]> = original trip-count
-; DBG-EMPTY:
-; DBG-NEXT: ir-bb<entry>:
-; DBG-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i32 (1 smax %n) to i64)
-; DBG-NEXT: Successor(s): scalar.ph, vector.ph
-; DBG-EMPTY:
-; DBG-NEXT: vector.ph:
-; DBG-NEXT: Successor(s): vector loop
-; DBG-EMPTY:
-; DBG-NEXT: <x1> vector loop: {
-; DBG-NEXT: vp<[[CAN_IV:%.+]]> = CANONICAL-IV
-; DBG-EMPTY:
-; DBG-NEXT: vector.body:
-; DBG-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for> = phi ir<0>, vp<[[SCALAR_STEPS:.+]]>
-; DBG-NEXT: EMIT-SCALAR vp<[[TRUNC_IV:%.+]]> = trunc vp<[[CAN_IV]]> to i32
-; DBG-NEXT: vp<[[SCALAR_STEPS]]> = SCALAR-STEPS vp<[[TRUNC_IV]]>, ir<1>, vp<[[VF]]
-; DBG-NEXT: EMIT vp<[[IV_INC:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
-; DBG-NEXT: EMIT branch-on-count vp<[[IV_INC]]>, vp<[[VTC]]>
-; DBG-NEXT: No successors
-; DBG-NEXT: }
-; DBG-NEXT: Successor(s): middle.block
-; DBG-EMPTY:
-; DBG-NEXT: middle.block:
-; DBG-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%for>, vp<[[SCALAR_STEPS]]>
-; DBG-NEXT: CLONE store vp<[[SPLICE]]>, ir<%dst>
-; DBG-NEXT: EMIT vp<[[RESUME_1_PART:%.+]]> = extract-last-part vp<[[SCALAR_STEPS]]>
-; DBG-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VEC_TC]]>
-; DBG-NEXT: EMIT branch-on-cond vp<[[CMP]]>
-; DBG-NEXT: Successor(s): ir-bb<exit>, scalar.ph
-; DBG-EMPTY:
-; DBG-NEXT: ir-bb<exit>:
-; DBG-NEXT: No successors
-; DBG-EMPTY:
-; DBG-NEXT: scalar.ph:
-; DBG-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
-; DBG-NEXT: EMIT-SCALAR vp<[[RESUME_P:%.*]]> = phi [ vp<[[RESUME_1_PART]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
-; DBG-NEXT: Successor(s): ir-bb<loop>
-; DBG-EMPTY:
-; DBG-NEXT: ir-bb<loop>:
-; DBG-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph)
-; DBG-NEXT: IR %for = phi i32 [ 0, %entry ], [ %iv.trunc, %loop ] (extra operand: vp<[[RESUME_P]]> from scalar.ph)
-; DBG: IR %ec = icmp slt i32 %iv.next.trunc, %n
-; DBG-NEXT: No successors
-; DBG-NEXT: }
define void @first_order_recurrence_using_induction(i32 %n, ptr %dst) {
-; CHECK-LABEL: @first_order_recurrence_using_induction(
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
-; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INDEX]] to i32
-; CHECK-NEXT: [[INDUCTION:%.*]] = add i32 [[TMP3]], 0
-; CHECK-NEXT: [[INDUCTION1:%.*]] = add i32 [[TMP3]], 1
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], %n.vec
-; CHECK-NEXT: br i1 [[TMP4]], label %middle.block, label %vector.body
-; CHECK: middle.block:
-; CHECK-NEXT: store i32 [[INDUCTION]], ptr [[DST]], align 4
+; CHECK-LABEL: VPlan for loop in 'first_order_recurrence_using_induction'
+; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (zext i32 (1 smax %n) to i64)
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for> = phi ir<0>, vp<[[VP6:%[0-9]+]]>
+; CHECK-NEXT: EMIT-SCALAR vp<[[VP5:%[0-9]+]]> = trunc vp<[[VP4]]> to i32
+; CHECK-NEXT: vp<[[VP6]]> = SCALAR-STEPS vp<[[VP5]]>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = first-order splice ir<%for>, vp<[[VP6]]>
+; CHECK-NEXT: CLONE store vp<[[VP8]]>, ir<%dst>
+; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = extract-last-part vp<[[VP6]]>
+; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]>
+; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
+; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<exit>:
+; CHECK-NEXT: No successors
+; CHECK-EMPTY:
+; CHECK-NEXT: scalar.ph:
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<[[VP9]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK-NEXT: Successor(s): ir-bb<loop>
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<loop>:
+; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK-NEXT: IR %for = phi i32 [ 0, %entry ], [ %iv.trunc, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph)
+; CHECK-NEXT: IR %iv.trunc = trunc i64 %iv to i32
+; CHECK-NEXT: IR store i32 %for, ptr %dst, align 4
+; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 1
+; CHECK-NEXT: IR %iv.next.trunc = trunc i64 %iv.next to i32
+; CHECK-NEXT: IR %ec = icmp slt i32 %iv.next.trunc, %n
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
;
entry:
br label %loop
@@ -268,21 +241,58 @@ exit:
}
define i16 @reduction_with_casts() {
-; CHECK-LABEL: define i16 @reduction_with_casts() {
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.+]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.+]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[VEC_PHI]], 65535
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[VEC_PHI1]], 65535
-; CHECK-NEXT: [[TMP2]] = add i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 9998
-; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]]
-; CHECK: middle.block:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: br label %scalar.ph
+; CHECK-LABEL: VPlan for loop in 'reduction_with_casts'
+; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: Live-in ir<9999> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: vp<[[VP2:%[0-9]+]]> = DERIVED-IV ir<1> + vp<[[VP1]]> * ir<1>
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1>
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%count.0.in1> = phi (add) vp<[[VP3]]>, ir<%add>
+; CHECK-NEXT: CLONE ir<%conv1> = and ir<%count.0.in1>, ir<65535>
+; CHECK-NEXT: CLONE ir<%add> = add ir<%conv1>, ir<1>
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP0]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP1]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = compute-reduction-result (add) ir<%add>
+; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<9999>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
+; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<exit>:
+; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[VP6]]> from middle.block)
+; CHECK-NEXT: IR %count.0 = trunc i32 %add.lcssa to i16
+; CHECK-NEXT: No successors
+; CHECK-EMPTY:
+; CHECK-NEXT: scalar.ph:
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP6]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<1>, ir-bb<entry> ]
+; CHECK-NEXT: Successor(s): ir-bb<loop>
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<loop>:
+; CHECK-NEXT: IR %count.0.in1 = phi i32 [ 0, %entry ], [ %add, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph)
+; CHECK-NEXT: IR %iv = phi i16 [ 1, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK-NEXT: IR %conv1 = and i32 %count.0.in1, 65535
+; CHECK-NEXT: IR %add = add nuw nsw i32 %conv1, 1
+; CHECK-NEXT: IR %iv.next = add i16 %iv, 1
+; CHECK-NEXT: IR %cmp = icmp eq i16 %iv.next, 10000
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
;
entry:
br label %loop
@@ -303,19 +313,61 @@ exit:
}
define void @scalarize_ptrtoint(ptr %src, ptr %dst) {
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr ptr, ptr %src, i64 [[TMP1]]
-; CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP3]], align 8
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-NEXT: br i1 [[TMP12]], label %middle.block, label %vector.body
-; CHECK: middle.block:
-; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP5]] to i64
-; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP7]], 10
-; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP9]] to ptr
-; CHECK-NEXT: store ptr [[TMP11]], ptr %dst, align 8
+; CHECK-LABEL: VPlan for loop in 'scalarize_ptrtoint'
+; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: Live-in ir<1024> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: CLONE ir<%gep> = getelementptr ir<%src>, vp<[[VP4]]>
+; CHECK-NEXT: CLONE ir<%l> = load ir<%gep> (!alias.scope <{{.*}}>)
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+; CHECK-NEXT: EMIT-SCALAR ir<%cast> = ptrtoint ir<%l> to i64
+; CHECK-NEXT: CLONE ir<%add> = add ir<%cast>, ir<10>
+; CHECK-NEXT: EMIT-SCALAR ir<%cast.2> = inttoptr ir<%add> to ptr
+; CHECK-NEXT: CLONE store ir<%cast.2>, ir<%dst> (!alias.scope <{{.*}}>, !noalias <{{.*}}>)
+; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<[[VP2]]>
+; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
+; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<exit>:
+; CHECK-NEXT: No successors
+; CHECK-EMPTY:
+; CHECK-NEXT: scalar.ph:
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
+; CHECK-NEXT: Successor(s): ir-bb<loop>
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<loop>:
+; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK-NEXT: IR %gep = getelementptr ptr, ptr %src, i64 %iv
+; CHECK-NEXT: IR %l = load ptr, ptr %gep, align 8
+; CHECK-NEXT: IR %cast = ptrtoint ptr %l to i64
+; CHECK-NEXT: IR %add = add i64 %cast, 10
+; CHECK-NEXT: IR %cast.2 = inttoptr i64 %add to ptr
+; CHECK-NEXT: IR store ptr %cast.2, ptr %dst, align 8
+; CHECK-NEXT: IR %iv.next = add i64 %iv, 1
+; CHECK-NEXT: IR %ec = icmp eq i64 %iv.next, 1024
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+;
entry:
br label %loop
@@ -337,27 +389,62 @@ exit:
}
define void @pr76986_trunc_sext_interleaving_only(i16 %arg, ptr noalias %src, ptr noalias %dst) {
-; CHECK-LABEL: define void @pr76986_trunc_sext_interleaving_only(
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr %src, i64 [[INDEX]]
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr %src, i64 [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP2]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP3]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = sext i8 [[TMP4]] to i32
-; CHECK-NEXT: [[TMP7:%.*]] = sext i8 [[TMP5]] to i32
-; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP6]] to i16
-; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP7]] to i16
-; CHECK-NEXT: [[TMP10:%.*]] = sdiv i16 [[TMP8]], %arg
-; CHECK-NEXT: [[TMP11:%.*]] = sdiv i16 [[TMP9]], %arg
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i16, ptr %dst, i64 [[INDEX]]
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i16, ptr %dst, i64 [[TMP1]]
-; CHECK-NEXT: store i16 [[TMP10]], ptr [[TMP12]], align 2
-; CHECK-NEXT: store i16 [[TMP11]], ptr [[TMP13]], align 2
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 14934
-; CHECK-NEXT: br i1 [[TMP14]], label %middle.block, label %vector.body
+; CHECK-LABEL: VPlan for loop in 'pr76986_trunc_sext_interleaving_only'
+; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: Live-in ir<14934> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<bb>:
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: CLONE ir<%gep.src> = getelementptr inbounds ir<%src>, vp<[[VP4]]>
+; CHECK-NEXT: CLONE ir<%l> = load ir<%gep.src>
+; CHECK-NEXT: EMIT-SCALAR ir<%sext> = sext ir<%l> to i32
+; CHECK-NEXT: EMIT-SCALAR ir<%trunc> = trunc ir<%sext> to i16
+; CHECK-NEXT: CLONE ir<%sdiv> = sdiv ir<%trunc>, ir<%arg>
+; CHECK-NEXT: CLONE ir<%gep.dst> = getelementptr inbounds ir<%dst>, vp<[[VP4]]>
+; CHECK-NEXT: CLONE store ir<%sdiv>, ir<%gep.dst>
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<14934>, vp<[[VP2]]>
+; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
+; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<exit>:
+; CHECK-NEXT: No successors
+; CHECK-EMPTY:
+; CHECK-NEXT: scalar.ph:
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<bb> ]
+; CHECK-NEXT: Successor(s): ir-bb<loop>
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<loop>:
+; CHECK-NEXT: IR %iv = phi i64 [ 0, %bb ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK-NEXT: IR %gep.src = getelementptr inbounds i8, ptr %src, i64 %iv
+; CHECK-NEXT: IR %l = load i8, ptr %gep.src, align 1
+; CHECK-NEXT: IR %sext = sext i8 %l to i32
+; CHECK-NEXT: IR %trunc = trunc i32 %sext to i16
+; CHECK-NEXT: IR %sdiv = sdiv i16 %trunc, %arg
+; CHECK-NEXT: IR %gep.dst = getelementptr inbounds i16, ptr %dst, i64 %iv
+; CHECK-NEXT: IR store i16 %sdiv, ptr %gep.dst, align 2
+; CHECK-NEXT: IR %iv.next = add i64 %iv, 1
+; CHECK-NEXT: IR %icmp = icmp ult i64 %iv, 14933
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
;
bb:
br label %loop
@@ -380,27 +467,63 @@ exit:
}
define void @pr179671(ptr align 8 dereferenceable(120) %p, ptr %a, i32 %b) {
-; CHECK-LABEL: define void @pr179671(
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
-; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi ptr [ %a, %vector.ph ], [ [[NEXT_GEP3:%.*]], %vector.body ]
-; CHECK-NEXT: [[DOTCAST1:%.*]] = trunc i64 [[INDEX]] to i32
-; CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[DOTCAST1]], 3
-; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 %b, [[TMP10]]
-; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[OFFSET_IDX]], 3
-; CHECK-NEXT: [[OFFSET_IDX2:%.*]] = shl i64 [[INDEX]], 7
-; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX2]], 0
-; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX2]], 128
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr null, i64 [[TMP15]]
-; CHECK-NEXT: [[NEXT_GEP3]] = getelementptr i8, ptr null, i64 [[TMP12]]
-; CHECK-NEXT: store ptr [[VECTOR_RECUR]], ptr [[NEXT_GEP]], align 8
-; CHECK-NEXT: store ptr [[NEXT_GEP]], ptr [[NEXT_GEP3]], align 8
-; CHECK-NEXT: store ptr [[NEXT_GEP3]], ptr [[INV_PTR:%.*]], align 8
-; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], 3
-; CHECK-NEXT: store i32 [[TMP13]], ptr [[INV_PTR2:%.*]], align 8
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC:%.*]]
-; CHECK-NEXT: br i1 [[TMP14]], label %[[LOOP_1:.*]], label %vector.body
+; CHECK-LABEL: VPlan for loop in 'pr179671'
+; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: IR %inv_ptr = getelementptr inbounds nuw i8, ptr %p, i64 24
+; CHECK-NEXT: IR %inv_ptr2 = getelementptr inbounds nuw i8, ptr %p, i64 40
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = EXPAND SCEV (1 + (zext i32 (1431655767 + (1431655765 * %b)) to i64))<nuw><nsw>
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%b> + vp<[[VP2]]> * ir<3>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = DERIVED-IV ir<null> + vp<[[VP2]]> * ir<128>
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%load12> = phi ir<%a>, vp<%next.gep>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = DERIVED-IV ir<%b> + vp<[[VP6]]> * ir<3>
+; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = SCALAR-STEPS vp<[[VP7]]>, ir<3>, vp<[[VP0]]>
+; CHECK-NEXT: vp<[[VP9:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP6]]> * ir<128>
+; CHECK-NEXT: vp<[[VP10:%[0-9]+]]> = SCALAR-STEPS vp<[[VP9]]>, ir<128>, vp<[[VP0]]>
+; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<null>, vp<[[VP10]]>
+; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = first-order splice ir<%load12>, vp<%next.gep>
+; CHECK-NEXT: CLONE store vp<[[VP11]]>, vp<%next.gep>
+; CHECK-NEXT: CLONE store vp<%next.gep>, ir<%inv_ptr>
+; CHECK-NEXT: CLONE ir<%sadd_val> = add vp<[[VP8]]>, ir<3>
+; CHECK-NEXT: CLONE store ir<%sadd_val>, ir<%inv_ptr2>
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+; CHECK-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = extract-last-part vp<%next.gep>
+; CHECK-NEXT: Successor(s): scalar.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: scalar.ph:
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%b>, ir-bb<entry> ]
+; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<[[VP13]]>, middle.block ], [ ir<%a>, ir-bb<entry> ]
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val>.1 = phi [ vp<[[VP5]]>, middle.block ], [ ir<null>, ir-bb<entry> ]
+; CHECK-NEXT: Successor(s): ir-bb<loop.header>
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<loop.header>:
+; CHECK-NEXT: IR %load23 = phi i32 [ %b, %entry ], [ %sadd_val, %loop.5 ] (extra operand: vp<%bc.resume.val> from scalar.ph)
+; CHECK-NEXT: IR %load12 = phi ptr [ %a, %entry ], [ %phi_ptr1, %loop.5 ] (extra operand: vp<%scalar.recur.init> from scalar.ph)
+; CHECK-NEXT: IR %phi_ptr1 = phi ptr [ null, %entry ], [ %phi_ptr_next, %loop.5 ] (extra operand: vp<%bc.resume.val>.1 from scalar.ph)
+; CHECK-NEXT: IR %phi_ptr_next = getelementptr i8, ptr %phi_ptr1, i64 128
+; CHECK-NEXT: IR store ptr %load12, ptr %phi_ptr1, align 8
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+;
entry:
%inv_ptr = getelementptr inbounds nuw i8, ptr %p, i64 24
%inv_ptr2 = getelementptr inbounds nuw i8, ptr %p, i64 40
diff --git a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll b/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
new file mode 100644
index 0000000000000..483205bf53eb5
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
@@ -0,0 +1,479 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck %s
+; Keep in sync with VPlan-version of the test:
+; RUN: llvm-diff %s %S/VPlan/interleave-and-scalarize-only.ll 2>&1 | count 0
+
+define void @test_scalarize_call(i32 %start, ptr %dst) {
+; CHECK-LABEL: define void @test_scalarize_call(
+; CHECK-SAME: i32 [[START:%.*]], ptr [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = sub i32 1000, [[START]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP0]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP0]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP0]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[START]], [[N_VEC]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 [[START]], [[INDEX]]
+; CHECK-NEXT: [[INDUCTION1:%.*]] = add i32 [[OFFSET_IDX]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.smin.i32(i32 [[OFFSET_IDX]], i32 65535)
+; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[INDUCTION1]], i32 65535)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[OFFSET_IDX]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[INDUCTION1]]
+; CHECK-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 8
+; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP4]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
+; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP0]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[MIN:%.*]] = tail call i32 @llvm.smin.i32(i32 [[IV]], i32 65535)
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[IV]]
+; CHECK-NEXT: store i32 [[MIN]], ptr [[ARRAYIDX]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], 1
+; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 1000
+; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
+ %min = tail call i32 @llvm.smin.i32(i32 %iv, i32 65535)
+ %arrayidx = getelementptr inbounds i32 , ptr %dst, i32 %iv
+ store i32 %min, ptr %arrayidx, align 8
+ %iv.next = add nsw i32 %iv, 1
+ %tobool.not = icmp eq i32 %iv.next, 1000
+ br i1 %tobool.not, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @test_scalarize_with_branch_cond(ptr %src, ptr %dst) {
+; CHECK-LABEL: define void @test_scalarize_with_branch_cond(
+; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[SRC2:%.*]] = ptrtoaddr ptr [[SRC]] to i64
+; CHECK-NEXT: [[DST1:%.*]] = ptrtoaddr ptr [[DST]] to i64
+; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[DST1]], [[SRC2]]
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[TMP5]], 1
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP8]], 7
+; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE4:.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDEX]] to i1
+; CHECK-NEXT: [[INDUCTION3:%.*]] = add i1 [[TMP0]], true
+; CHECK-NEXT: br i1 [[TMP0]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
+; CHECK: [[PRED_STORE_IF]]:
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[INDEX]]
+; CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP1]], align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
+; CHECK: [[PRED_STORE_CONTINUE]]:
+; CHECK-NEXT: br i1 [[INDUCTION3]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4]]
+; CHECK: [[PRED_STORE_IF3]]:
+; CHECK-NEXT: [[INDUCTION5:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDUCTION5]]
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[INDUCTION5]]
+; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP2]], align 4
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
+; CHECK: [[PRED_STORE_CONTINUE4]]:
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
+; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
+; CHECK: [[LOOP_HEADER]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
+; CHECK-NEXT: [[D:%.*]] = phi i1 [ false, %[[SCALAR_PH]] ], [ [[D_NEXT:%.*]], %[[LOOP_LATCH]] ]
+; CHECK-NEXT: [[D_NEXT]] = xor i1 [[D]], true
+; CHECK-NEXT: br i1 [[D]], label %[[COND_FALSE:.*]], label %[[LOOP_LATCH]]
+; CHECK: [[COND_FALSE]]:
+; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]]
+; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4
+; CHECK-NEXT: store i32 [[L]], ptr [[GEP_DST]], align 4
+; CHECK-NEXT: br label %[[LOOP_LATCH]]
+; CHECK: [[LOOP_LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ %d = phi i1 [ false, %entry ], [ %d.next, %loop.latch ]
+ %d.next = xor i1 %d, true
+ br i1 %d, label %cond.false, label %loop.latch
+
+cond.false:
+ %gep.src = getelementptr inbounds i32, ptr %src, i64 %iv
+ %gep.dst = getelementptr inbounds i32, ptr %dst, i64 %iv
+ %l = load i32, ptr %gep.src, align 4
+ store i32 %l, ptr %gep.dst
+ br label %loop.latch
+
+loop.latch:
+ %iv.next = add nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 1000
+ br i1 %ec, label %exit, label %loop.header
+
+exit:
+ ret void
+}
+
+; Make sure the widened induction gets replaced by scalar-steps for plans
+; including the scalar VF, if it is used in first-order recurrences.
+
+
+define void @first_order_recurrence_using_induction(i32 %n, ptr %dst) {
+; CHECK-LABEL: define void @first_order_recurrence_using_induction(
+; CHECK-SAME: i32 [[N:%.*]], ptr [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smax.i32(i32 [[N]], i32 1)
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INDEX]] to i32
+; CHECK-NEXT: [[INDUCTION:%.*]] = add i32 [[TMP3]], 0
+; CHECK-NEXT: [[INDUCTION1:%.*]] = add i32 [[TMP3]], 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: store i32 [[INDUCTION]], ptr [[DST]], align 4
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i32 [ [[INDUCTION1]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[FOR:%.*]] = phi i32 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[IV_TRUNC:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV_TRUNC]] = trunc i64 [[IV]] to i32
+; CHECK-NEXT: store i32 [[FOR]], ptr [[DST]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT_TRUNC:%.*]] = trunc i64 [[IV_NEXT]] to i32
+; CHECK-NEXT: [[EC:%.*]] = icmp slt i32 [[IV_NEXT_TRUNC]], [[N]]
+; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ],[ %iv.next, %loop ]
+ %for = phi i32 [ 0, %entry ], [ %iv.trunc, %loop ]
+ %iv.trunc = trunc i64 %iv to i32
+ store i32 %for, ptr %dst
+ %iv.next = add nuw nsw i64 %iv, 1
+ %iv.next.trunc = trunc i64 %iv.next to i32
+ %ec = icmp slt i32 %iv.next.trunc, %n
+ br i1 %ec, label %loop, label %exit
+
+exit:
+ ret void
+}
+
+define i16 @reduction_with_casts() {
+; CHECK-LABEL: define i16 @reduction_with_casts() {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[VEC_PHI]], 65535
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[VEC_PHI1]], 65535
+; CHECK-NEXT: [[TMP2]] = add i32 [[TMP0]], 1
+; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 9998
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[COUNT_0_IN1:%.*]] = phi i32 [ [[BIN_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i16 [ 9999, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[CONV1:%.*]] = and i32 [[COUNT_0_IN1]], 65535
+; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[CONV1]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[IV_NEXT]], 10000
+; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], %[[LOOP]] ]
+; CHECK-NEXT: [[COUNT_0:%.*]] = trunc i32 [[ADD_LCSSA]] to i16
+; CHECK-NEXT: ret i16 [[COUNT_0]]
+;
+entry:
+ br label %loop
+
+loop:
+ %count.0.in1 = phi i32 [ 0, %entry ], [ %add, %loop ]
+ %iv = phi i16 [ 1, %entry ], [ %iv.next, %loop ]
+ %conv1 = and i32 %count.0.in1, 65535
+ %add = add nuw nsw i32 %conv1, 1
+ %iv.next = add i16 %iv, 1
+ %cmp = icmp eq i16 %iv.next, 10000
+ br i1 %cmp, label %exit, label %loop
+
+exit:
+ %add.lcssa = phi i32 [ %add, %loop ]
+ %count.0 = trunc i32 %add.lcssa to i16
+ ret i16 %count.0
+}
+
+define void @scalarize_ptrtoint(ptr %src, ptr %dst) {
+; CHECK-LABEL: define void @scalarize_ptrtoint(
+; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 8
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 8192
+; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]]
+; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr ptr, ptr [[SRC]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !alias.scope [[META10:![0-9]+]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP2]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 10
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; CHECK-NEXT: store ptr [[TMP6]], ptr [[DST]], align 8, !alias.scope [[META14:![0-9]+]], !noalias [[META10]]
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr ptr, ptr [[SRC]], i64 [[IV]]
+; CHECK-NEXT: [[L:%.*]] = load ptr, ptr [[GEP]], align 8
+; CHECK-NEXT: [[CAST:%.*]] = ptrtoint ptr [[L]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add i64 [[CAST]], 10
+; CHECK-NEXT: [[CAST_2:%.*]] = inttoptr i64 [[ADD]] to ptr
+; CHECK-NEXT: store ptr [[CAST_2]], ptr [[DST]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP16:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep = getelementptr ptr, ptr %src, i64 %iv
+ %l = load ptr, ptr %gep, align 8
+ %cast = ptrtoint ptr %l to i64
+ %add = add i64 %cast, 10
+ %cast.2 = inttoptr i64 %add to ptr
+ store ptr %cast.2, ptr %dst, align 8
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 1024
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @pr76986_trunc_sext_interleaving_only(i16 %arg, ptr noalias %src, ptr noalias %dst) {
+; CHECK-LABEL: define void @pr76986_trunc_sext_interleaving_only(
+; CHECK-SAME: i16 [[ARG:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) {
+; CHECK-NEXT: [[BB:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP2]], align 1
+; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP3]], align 1
+; CHECK-NEXT: [[TMP6:%.*]] = sext i8 [[TMP4]] to i32
+; CHECK-NEXT: [[TMP7:%.*]] = sext i8 [[TMP5]] to i32
+; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP6]] to i16
+; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP7]] to i16
+; CHECK-NEXT: [[TMP10:%.*]] = sdiv i16 [[TMP8]], [[ARG]]
+; CHECK-NEXT: [[TMP11:%.*]] = sdiv i16 [[TMP9]], [[ARG]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[TMP1]]
+; CHECK-NEXT: store i16 [[TMP10]], ptr [[TMP12]], align 2
+; CHECK-NEXT: store i16 [[TMP11]], ptr [[TMP13]], align 2
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 14934
+; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+bb:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %bb ], [ %iv.next, %loop ]
+ %gep.src = getelementptr inbounds i8, ptr %src, i64 %iv
+ %l = load i8, ptr %gep.src
+ %sext = sext i8 %l to i32
+ %trunc = trunc i32 %sext to i16
+ %sdiv = sdiv i16 %trunc, %arg
+ %gep.dst = getelementptr inbounds i16, ptr %dst, i64 %iv
+ store i16 %sdiv, ptr %gep.dst
+ %iv.next = add i64 %iv, 1
+ %icmp = icmp ult i64 %iv, 14933
+ br i1 %icmp, label %loop, label %exit
+
+exit:
+ ret void
+}
+
+define void @pr179671(ptr align 8 dereferenceable(120) %p, ptr %a, i32 %b) {
+; CHECK-LABEL: define void @pr179671(
+; CHECK-SAME: ptr align 8 dereferenceable(120) [[P:%.*]], ptr [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[INV_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 24
+; CHECK-NEXT: [[INV_PTR2:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 40
+; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[B]], 1431655765
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 1431655767
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP3]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
+; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 2, i64 [[N_MOD_VF]]
+; CHECK-NEXT: [[INDEX:%.*]] = sub i64 [[TMP3]], [[TMP5]]
+; CHECK-NEXT: [[DOTCAST1:%.*]] = trunc i64 [[INDEX]] to i32
+; CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[DOTCAST1]], 3
+; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[B]], [[TMP10]]
+; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[INDEX]], 7
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr null, i64 [[TMP9]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi ptr [ [[A]], %[[VECTOR_PH]] ], [ [[NEXT_GEP3:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[INDEX1]] to i32
+; CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], 3
+; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 [[B]], [[TMP17]]
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[OFFSET_IDX]], 3
+; CHECK-NEXT: [[OFFSET_IDX2:%.*]] = shl i64 [[INDEX1]], 7
+; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX2]], 0
+; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX2]], 128
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr null, i64 [[TMP15]]
+; CHECK-NEXT: [[NEXT_GEP3]] = getelementptr i8, ptr null, i64 [[TMP12]]
+; CHECK-NEXT: store ptr [[VECTOR_RECUR]], ptr [[NEXT_GEP]], align 8
+; CHECK-NEXT: store ptr [[NEXT_GEP]], ptr [[NEXT_GEP3]], align 8
+; CHECK-NEXT: store ptr [[NEXT_GEP3]], ptr [[INV_PTR]], align 8
+; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], 3
+; CHECK-NEXT: store i32 [[TMP13]], ptr [[INV_PTR2]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 2
+; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[INDEX]]
+; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP8]], %[[MIDDLE_BLOCK]] ], [ [[B]], %[[ENTRY]] ]
+; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi ptr [ [[NEXT_GEP3]], %[[MIDDLE_BLOCK]] ], [ [[A]], %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi ptr [ [[TMP14]], %[[MIDDLE_BLOCK]] ], [ null, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
+; CHECK: [[LOOP_HEADER]]:
+; CHECK-NEXT: [[LOAD23:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[SADD_VAL:%.*]], %[[LOOP_5:.*]] ]
+; CHECK-NEXT: [[LOAD12:%.*]] = phi ptr [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[PHI_PTR1:%.*]], %[[LOOP_5]] ]
+; CHECK-NEXT: [[PHI_PTR1]] = phi ptr [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ], [ [[PHI_PTR_NEXT:%.*]], %[[LOOP_5]] ]
+; CHECK-NEXT: [[PHI_PTR_NEXT]] = getelementptr i8, ptr [[PHI_PTR1]], i64 128
+; CHECK-NEXT: store ptr [[LOAD12]], ptr [[PHI_PTR1]], align 8
+; CHECK-NEXT: br label %[[LOOP_3:.*]]
+; CHECK: [[LOOP_3]]:
+; CHECK-NEXT: store ptr [[PHI_PTR1]], ptr [[INV_PTR]], align 8
+; CHECK-NEXT: [[SADD_VAL]] = add i32 [[LOAD23]], 3
+; CHECK-NEXT: [[SADD_OV:%.*]] = icmp eq i32 [[SADD_VAL]], 8
+; CHECK-NEXT: br i1 [[SADD_OV]], label %[[EXIT_0:.*]], label %[[LOOP_5]]
+; CHECK: [[LOOP_5]]:
+; CHECK-NEXT: store i32 [[SADD_VAL]], ptr [[INV_PTR2]], align 8
+; CHECK-NEXT: br label %[[LOOP_HEADER]], !llvm.loop [[LOOP19:![0-9]+]]
+; CHECK: [[EXIT_0]]:
+; CHECK-NEXT: store i32 0, ptr [[P]], align 4
+; CHECK-NEXT: ret void
+; CHECK: [[EXIT:.*:]]
+; CHECK-NEXT: ret void
+;
+entry:
+ %inv_ptr = getelementptr inbounds nuw i8, ptr %p, i64 24
+ %inv_ptr2 = getelementptr inbounds nuw i8, ptr %p, i64 40
+ br label %loop.header
+
+loop.header:
+ %load23 = phi i32 [ %b, %entry ], [ %sadd_val, %loop.5 ]
+ %load12 = phi ptr [ %a, %entry ], [ %phi_ptr1, %loop.5 ]
+ %phi_ptr1 = phi ptr [ null, %entry ], [ %phi_ptr_next, %loop.5 ]
+ %phi_ptr_next = getelementptr i8, ptr %phi_ptr1, i64 128
+ store ptr %load12, ptr %phi_ptr1, align 8
+ br label %loop.3
+
+loop.3:
+ store ptr %phi_ptr1, ptr %inv_ptr, align 8
+ %sadd_val = add i32 %load23, 3
+ %sadd_ov = icmp eq i32 %sadd_val, 8
+ br i1 %sadd_ov, label %exit.0, label %loop.5
+
+loop.5:
+ store i32 %sadd_val, ptr %inv_ptr2, align 8
+ br label %loop.header
+
+exit.0:
+ store i32 0, ptr %p, align 4
+ ret void
+
+exit:
+ ret void
+}
>From 4d583f9db9ef5dffd2cc2684a9c36fb299965cac Mon Sep 17 00:00:00 2001
From: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: Thu, 23 Jul 2026 08:32:03 -0700
Subject: [PATCH 2/3] Drop `llvm-diff` checks for keeping files in sync
---
.../Transforms/LoopVectorize/interleave-and-scalarize-only.ll | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll b/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
index 483205bf53eb5..69871823130ce 100644
--- a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
+++ b/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
@@ -1,7 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck %s
-; Keep in sync with VPlan-version of the test:
-; RUN: llvm-diff %s %S/VPlan/interleave-and-scalarize-only.ll 2>&1 | count 0
define void @test_scalarize_call(i32 %start, ptr %dst) {
; CHECK-LABEL: define void @test_scalarize_call(
>From a9e49b594fe314b4ea38f4cd8b0d997191270dc2 Mon Sep 17 00:00:00 2001
From: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: Thu, 23 Jul 2026 16:56:31 -0700
Subject: [PATCH 3/3] Use `-vplan-print-metadata=false` instead of manual
`{{.*}}`
---
.../LoopVectorize/VPlan/interleave-and-scalarize-only.ll | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
index 4120311e552e2..1cc75db39a7b4 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -vplan-print-after=printOptimizedVPlan -disable-output %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -vplan-print-after=printOptimizedVPlan -disable-output -vplan-print-metadata=false %s 2>&1 | FileCheck %s
;
define void @test_scalarize_call(i32 %start, ptr %dst) {
@@ -332,7 +332,7 @@ define void @scalarize_ptrtoint(ptr %src, ptr %dst) {
; CHECK-NEXT: vector.body:
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep> = getelementptr ir<%src>, vp<[[VP4]]>
-; CHECK-NEXT: CLONE ir<%l> = load ir<%gep> (!alias.scope <{{.*}}>)
+; CHECK-NEXT: CLONE ir<%l> = load ir<%gep>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
@@ -343,7 +343,7 @@ define void @scalarize_ptrtoint(ptr %src, ptr %dst) {
; CHECK-NEXT: EMIT-SCALAR ir<%cast> = ptrtoint ir<%l> to i64
; CHECK-NEXT: CLONE ir<%add> = add ir<%cast>, ir<10>
; CHECK-NEXT: EMIT-SCALAR ir<%cast.2> = inttoptr ir<%add> to ptr
-; CHECK-NEXT: CLONE store ir<%cast.2>, ir<%dst> (!alias.scope <{{.*}}>, !noalias <{{.*}}>)
+; CHECK-NEXT: CLONE store ir<%cast.2>, ir<%dst>
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
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