[llvm] af795ff - [AMDGPU] Fix pre-GFX11 llvm.fptosi.sat.i16.f32 lowering (#211703)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 24 06:47:47 PDT 2026
Author: Dragan Mladjenovic
Date: 2026-07-24T09:47:42-04:00
New Revision: af795ffee92313af4a439919264737d4d9d7886c
URL: https://github.com/llvm/llvm-project/commit/af795ffee92313af4a439919264737d4d9d7886c
DIFF: https://github.com/llvm/llvm-project/commit/af795ffee92313af4a439919264737d4d9d7886c.diff
LOG: [AMDGPU] Fix pre-GFX11 llvm.fptosi.sat.i16.f32 lowering (#211703)
Added:
Modified:
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index ab2538c2f9f00..94cbdfa6a3943 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -3290,6 +3290,6 @@ let SubtargetPredicate = isGFX11Plus in {
// Fallback for f32 -> i16 saturated conversion on pre-GFX11. Required because
// f32 -> i16 has to be legal so that the packed pattern above can match.
let SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10 in {
- defm : FPToSSatI16Pat<(i16 (fp_to_sint_sat (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)), i16)), 0x7fff, 0x8000>;
+ defm : FPToSSatI16Pat<(i16 (fp_to_sint_sat (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)), i16)), 0x7fff, 0xffff8000>;
defm : FPToUSatI16Pat<(i16 (fp_to_uint_sat (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)), i16)), 0xffff>;
}
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index 80f5989277b40..66b2ba892182a 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -133,7 +133,7 @@ define i16 @test_signed_i16_f32(float %f) nounwind {
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v1, s4
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
@@ -142,7 +142,7 @@ define i16 @test_signed_i16_f32(float %f) nounwind {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX9-NEXT: v_med3_i32 v0, v0, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -542,7 +542,7 @@ define i16 @test_s_signed_i16_f32(float inreg %f) nounwind {
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, s16
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v1, s4
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
;
@@ -551,7 +551,7 @@ define i16 @test_s_signed_i16_f32(float inreg %f) nounwind {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, s16
; GFX9-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX9-NEXT: v_med3_i32 v0, v0, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1823,7 +1823,7 @@ define i16 @test_signed_i16_f16(half %f) nounwind {
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v1, s4
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
@@ -2232,7 +2232,7 @@ define i16 @test_s_signed_i16_f16(half inreg %f) nounwind {
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v0, s16
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v1, s4
; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index 402c10f4e3ab2..c5355907e4e5f 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2883,7 +2883,7 @@ define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0xffff8000
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX7-GI-NEXT: v_med3_i32 v2, v2, v4, s4
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v4, s4
@@ -3785,7 +3785,7 @@ define <4 x i16> @test_s_signed_v4f16_v4i16(<4 x half> inreg %f) {
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, s17
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v4, s5
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v1, s4
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX7-GI-NEXT: v_readfirstlane_b32 s5, v0
@@ -4709,7 +4709,7 @@ define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v5, v5
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v7, v7
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v8, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v8, 0xffff8000
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX7-GI-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX7-GI-NEXT: v_med3_i32 v4, v4, v8, s4
@@ -6250,7 +6250,7 @@ define <8 x i16> @test_s_signed_v8f16_v8i16(<8 x half> inreg %f) {
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX7-GI-NEXT: v_mov_b32_e32 v2, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v2, 0xffff8000
; GFX7-GI-NEXT: s_lshr_b32 s5, s17, 16
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v2, s4
; GFX7-GI-NEXT: v_readfirstlane_b32 s8, v0
@@ -6717,7 +6717,7 @@ define <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0xffff8000
; GFX7-GI-NEXT: v_med3_i32 v1, v1, v4, s4
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v4, s4
; GFX7-GI-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -6740,7 +6740,7 @@ define <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX9-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff8000
; GFX9-NEXT: v_med3_i32 v2, v2, v4, s4
; GFX9-NEXT: v_med3_i32 v3, v3, v4, s4
; GFX9-NEXT: v_med3_i32 v0, v0, v4, s4
@@ -6798,7 +6798,7 @@ define <4 x i16> @test_s_signed_v4f32_v4i16(<4 x float> inreg %f) {
; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, s16
; GFX7-GI-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX7-GI-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v2, s17
; GFX7-GI-NEXT: v_med3_i32 v0, v0, v1, s4
; GFX7-GI-NEXT: v_readfirstlane_b32 s5, v0
@@ -6830,7 +6830,7 @@ define <4 x i16> @test_s_signed_v4f32_v4i16(<4 x float> inreg %f) {
; GFX9-NEXT: v_cvt_i32_f32_e32 v3, s17
; GFX9-NEXT: v_cvt_i32_f32_e32 v4, s16
; GFX9-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x8000
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff8000
; GFX9-NEXT: v_med3_i32 v5, v0, v1, s4
; GFX9-NEXT: v_med3_i32 v2, v2, v1, s4
; GFX9-NEXT: v_med3_i32 v0, v3, v1, s4
More information about the llvm-commits
mailing list