[llvm] [SelectionDAG] Stop forming minnum/maxnum in SDAGBuilder (PR #187738)
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llvm-commits at lists.llvm.org
Fri Jul 24 06:16:49 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
Author: Nikita Popov (nikic)
<details>
<summary>Changes</summary>
The right place to form these is DAGCombine, not SDAGBuilder. This removes the SPNB_RETURNS_ANY case, the SPNB_RETURNS_OTHER is left to a followup. We need to propagate FMF flags in a few more places to make this work.
---
Patch is 39.53 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/187738.diff
9 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+23-10)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (+2-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+2-3)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+2-1)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+6-14)
- (modified) llvm/test/CodeGen/AArch64/select_fmf.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll (+22-22)
- (modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll (+22-22)
- (modified) llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll (+107-254)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 232cd609251db..c48bce6e2a99d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12707,15 +12707,17 @@ SDValue DAGCombiner::visitCTPOP(SDNode *N) {
}
static bool isLegalToCombineMinNumMaxNum(SelectionDAG &DAG, SDValue LHS,
- SDValue RHS, const SDNodeFlags Flags,
+ SDValue RHS,
+ const SDNodeFlags SelectFlags,
+ const SDNodeFlags CmpFlags,
const TargetLowering &TLI) {
EVT VT = LHS.getValueType();
if (!VT.isFloatingPoint())
return false;
- return Flags.hasNoSignedZeros() &&
+ return SelectFlags.hasNoSignedZeros() &&
TLI.isProfitableToCombineMinNumMaxNum(VT) &&
- (Flags.hasNoNaNs() ||
+ (SelectFlags.hasNoNaNs() || CmpFlags.hasNoNaNs() ||
(DAG.isKnownNeverNaN(RHS) && DAG.isKnownNeverNaN(LHS)));
}
@@ -12724,7 +12726,16 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
ISD::CondCode CC,
const TargetLowering &TLI,
SelectionDAG &DAG) {
- EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+ EVT TransformVT = VT;
+ while (TLI.getTypeAction(*DAG.getContext(), TransformVT) !=
+ TargetLoweringBase::TypeLegal)
+ TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), TransformVT);
+
+ // We have checked nnan and nsz as pre-conditions for the transform.
+ SDNodeFlags Flags;
+ Flags.setNoNaNs(true);
+ Flags.setNoSignedZeros(true);
+
switch (CC) {
case ISD::SETOLT:
case ISD::SETOLE:
@@ -12737,11 +12748,11 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
// expanded in terms of it.
unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
- return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
+ return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS, Flags);
unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
- return DAG.getNode(Opcode, DL, VT, LHS, RHS);
+ return DAG.getNode(Opcode, DL, VT, LHS, RHS, Flags);
return SDValue();
}
case ISD::SETOGT:
@@ -12752,11 +12763,11 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
case ISD::SETUGE: {
unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
- return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
+ return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS, Flags);
unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
- return DAG.getNode(Opcode, DL, VT, LHS, RHS);
+ return DAG.getNode(Opcode, DL, VT, LHS, RHS, Flags);
return SDValue();
}
default:
@@ -13469,7 +13480,8 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
// select (fcmp gt x, y), x, y -> fmaxnum x, y
//
// This is OK if we don't care what happens if either operand is a NaN.
- if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(DAG, N1, N2, Flags, TLI))
+ if (N0.hasOneUse() &&
+ isLegalToCombineMinNumMaxNum(DAG, N1, N2, Flags, N0->getFlags(), TLI))
if (SDValue FMinMax =
combineMinNumMaxNum(DL, VT, Cond0, Cond1, N1, N2, CC))
return FMinMax;
@@ -14531,7 +14543,8 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
// NaN.
//
if (N0.hasOneUse() &&
- isLegalToCombineMinNumMaxNum(DAG, LHS, RHS, N->getFlags(), TLI)) {
+ isLegalToCombineMinNumMaxNum(DAG, LHS, RHS, N->getFlags(),
+ N0->getFlags(), TLI)) {
if (SDValue FMinMax = combineMinNumMaxNum(DL, VT, LHS, RHS, N1, N2, CC))
return FMinMax;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 25cc420c42482..d0a29b5365daa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -3026,8 +3026,8 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_ATOMIC_LOAD(SDNode *N) {
SDValue DAGTypeLegalizer::SoftPromoteHalfRes_SELECT(SDNode *N) {
SDValue Op1 = GetSoftPromotedHalf(N->getOperand(1));
SDValue Op2 = GetSoftPromotedHalf(N->getOperand(2));
- return DAG.getSelect(SDLoc(N), Op1.getValueType(), N->getOperand(0), Op1,
- Op2);
+ return DAG.getSelect(SDLoc(N), Op1.getValueType(), N->getOperand(0), Op1, Op2,
+ N->getFlags());
}
SDValue DAGTypeLegalizer::SoftPromoteHalfRes_SELECT_CC(SDNode *N) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 9ad56694cceeb..c71352fb20817 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -731,9 +731,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
if (BoolVT.bitsLT(CondVT))
Cond = DAG.getNode(ISD::TRUNCATE, SDLoc(N), BoolVT, Cond);
- return DAG.getSelect(SDLoc(N),
- LHS.getValueType(), Cond, LHS,
- GetScalarizedVector(N->getOperand(2)));
+ return DAG.getSelect(SDLoc(N), LHS.getValueType(), Cond, LHS,
+ GetScalarizedVector(N->getOperand(2)), N->getFlags());
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 679fa3fe36e27..e1844e66c825c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -14336,7 +14336,8 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
break;
}
case ISD::VSELECT:
- Scalars.push_back(getNode(ISD::SELECT, dl, EltVT, Operands));
+ Scalars.push_back(
+ getNode(ISD::SELECT, dl, EltVT, Operands, N->getFlags()));
break;
case ISD::SHL:
case ISD::SRA:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index effa4a8d5f1b9..f1c9809c2159e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3916,17 +3916,13 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
switch (SPR.NaNBehavior) {
case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
- case SPNB_RETURNS_NAN: break;
+ case SPNB_RETURNS_ANY:
+ case SPNB_RETURNS_NAN:
+ break;
case SPNB_RETURNS_OTHER:
Opc = ISD::FMINIMUMNUM;
Flags.setNoSignedZeros(true);
break;
- case SPNB_RETURNS_ANY:
- if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ||
- (UseScalarMinMax &&
- TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType())))
- Opc = ISD::FMINNUM;
- break;
}
break;
case SPF_FMAXNUM:
@@ -3935,17 +3931,13 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
switch (SPR.NaNBehavior) {
case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
- case SPNB_RETURNS_NAN: break;
+ case SPNB_RETURNS_NAN:
+ case SPNB_RETURNS_ANY:
+ break;
case SPNB_RETURNS_OTHER:
Opc = ISD::FMAXIMUMNUM;
Flags.setNoSignedZeros(true);
break;
- case SPNB_RETURNS_ANY:
- if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ||
- (UseScalarMinMax &&
- TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType())))
- Opc = ISD::FMAXNUM;
- break;
}
break;
case SPF_NABS:
diff --git a/llvm/test/CodeGen/AArch64/select_fmf.ll b/llvm/test/CodeGen/AArch64/select_fmf.ll
index 88f517af65bb6..333e25fb5b824 100644
--- a/llvm/test/CodeGen/AArch64/select_fmf.ll
+++ b/llvm/test/CodeGen/AArch64/select_fmf.ll
@@ -8,12 +8,12 @@
define float @select_select_fold_select_and(float %w, float %x, float %y, float %z) {
; CHECK-SD-LABEL: select_select_fold_select_and:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fminnm s4, s1, s2
; CHECK-SD-NEXT: fcmp s1, s2
+; CHECK-SD-NEXT: fmov s4, #0.50000000
+; CHECK-SD-NEXT: fcsel s1, s1, s2, lt
; CHECK-SD-NEXT: fmaxnm s2, s0, s3
-; CHECK-SD-NEXT: fmov s1, #0.50000000
-; CHECK-SD-NEXT: fccmp s4, s0, #4, lt
-; CHECK-SD-NEXT: fadd s1, s0, s1
+; CHECK-SD-NEXT: fccmp s1, s0, #4, lt
+; CHECK-SD-NEXT: fadd s1, s0, s4
; CHECK-SD-NEXT: fcsel s2, s2, s0, gt
; CHECK-SD-NEXT: fadd s4, s1, s2
; CHECK-SD-NEXT: fcmp s4, s1
@@ -98,13 +98,13 @@ exit: ; preds = %if.end.i159.i.i, %if.then.i
define float @select_select_fold_select_or(float %w, float %x, float %y, float %z) {
; CHECK-SD-LABEL: select_select_fold_select_or:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fminnm s4, s1, s2
; CHECK-SD-NEXT: fcmp s1, s2
-; CHECK-SD-NEXT: fmaxnm s2, s0, s3
-; CHECK-SD-NEXT: fmov s1, #0.50000000
-; CHECK-SD-NEXT: fccmp s4, s0, #0, ge
-; CHECK-SD-NEXT: fadd s1, s0, s1
-; CHECK-SD-NEXT: fcsel s2, s0, s2, gt
+; CHECK-SD-NEXT: fcsel s1, s1, s2, lt
+; CHECK-SD-NEXT: fccmp s0, s3, #0, ge
+; CHECK-SD-NEXT: fmov s2, #0.50000000
+; CHECK-SD-NEXT: fccmp s1, s0, #0, le
+; CHECK-SD-NEXT: fadd s1, s0, s2
+; CHECK-SD-NEXT: fcsel s2, s0, s3, gt
; CHECK-SD-NEXT: fadd s4, s1, s2
; CHECK-SD-NEXT: fcmp s4, s1
; CHECK-SD-NEXT: b.le .LBB1_2
diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
index c752a16a169ed..868372158449c 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
@@ -725,54 +725,54 @@ define <8 x half> @test_fmax_legacy_ugt_v8f16_fast(<8 x half> %a, <8 x half> %b)
; SI-LABEL: test_fmax_legacy_ugt_v8f16_fast:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v6
; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v6
-; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
-; SI-NEXT: v_max_f32_e32 v11, v11, v12
-; SI-NEXT: v_cvt_f32_f16_e32 v12, v15
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_max_f32_e32 v11, v11, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v15
; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_max_f32_e32 v13, v13, v14
+; SI-NEXT: v_max_f32_e32 v10, v10, v12
; SI-NEXT: v_max_f32_e32 v8, v8, v9
-; SI-NEXT: v_max_f32_e32 v12, v14, v12
-; SI-NEXT: v_max_f32_e32 v10, v10, v13
-; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
-; SI-NEXT: v_max_f32_e32 v0, v0, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_max_f32_e32 v3, v3, v7
; SI-NEXT: v_max_f32_e32 v2, v2, v6
; SI-NEXT: v_max_f32_e32 v1, v1, v5
+; SI-NEXT: v_max_f32_e32 v0, v0, v4
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v13
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v0, v0, v8
; SI-NEXT: v_or_b32_e32 v1, v1, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_or_b32_e32 v3, v3, v11
+; SI-NEXT: v_or_b32_e32 v2, v2, v11
+; SI-NEXT: v_or_b32_e32 v3, v3, v9
; SI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_fmax_legacy_ugt_v8f16_fast:
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
index cb35fb423380c..ce80d8d811186 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
@@ -726,54 +726,54 @@ define <8 x half> @test_fmin_legacy_ule_v8f16_fast(<8 x half> %a, <8 x half> %b)
; SI-LABEL: test_fmin_legacy_ule_v8f16_fast:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v6
; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v6
-; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
-; SI-NEXT: v_min_f32_e32 v11, v11, v12
-; SI-NEXT: v_cvt_f32_f16_e32 v12, v15
+; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
+; SI-NEXT: v_min_f32_e32 v11, v11, v12
+; SI-NEXT: v_cvt_f32_f16_e32 v12, v15
; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
-; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_min_f32_e32 v13, v13, v14
+; SI-NEXT: v_min_f32_e32 v10, v10, v12
; SI-NEXT: v_min_f32_e32 v8, v8, v9
-; SI-NEXT: v_min_f32_e32 v12, v14, v12
-; SI-NEXT: v_min_f32_e32 v10, v10, v13
-; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
-; SI-NEXT: v_min_f32_e32 v0, v0, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_min_f32_e32 v3, v3, v7
; SI-NEXT: v_min_f32_e32 v2, v2, v6
; SI-NEXT: v_min_f32_e32 v1, v1, v5
+; SI-NEXT: v_min_f32_e32 v0, v0, v4
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v13
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v0, v0, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v0, v0, v8
; SI-NEXT: v_or_b32_e32 v1, v1, v10
-; SI-NEXT: v_or_b32_e32 v2, v2, v4
-; SI-NEXT: v_or_b32_e32 v3, v3, v11
+; SI-NEXT: v_or_b32_e32 v2, v2, v11
+; SI-NEXT: v_or_b32_e32 v3, v3, v9
; SI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_fmin_legacy_ule_v8f16_fast:
diff --git a/llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
index 1eb1530117bcc..54abedf063864 100644
--- a/llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
@@ -155,17 +155,16 @@ define <2 x half> @v_max_pat_v2f16_oge(<2 x half> nofpclass(nan) %a, <2 x half>
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v0
-; GFX7-NEXT: v_cmp_ge_f32_e32 vcc, v5, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX7-NEXT: v_cmp_ge_f32_e32 vcc, v7, v6
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX7-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_max_pat_v2f16_oge:
@@ -200,17 +199,16 @@ define <2 x half> @v_min_pat_v2f16_olt(<2 x half> nofpclass(nan) %a, <2 x half>
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v0
-; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v5, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v7, v6
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-NEXT: v_cvt_f32_f16_e32 v3, v3
+; GFX7-NEXT: v_cvt_f32_f16_e32 v2, v2
+; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX7-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX7-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_min_pat_v2f16_olt:
@@ -245,17 +243,16 @@ define <2 x half> @v_max_pat_v2f16_uge(<2 x half> nofpclass(nan) %a, <2 x half>
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v4, v3
-; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v2
-; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v0
-; GFX7-NEXT: v_cmp_ge_f32_e32 vcc, v5, v4
-; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX7-NEXT: v_cmp_ge_f32_e32 vcc, v7, v6
-; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX7-NEXT: v_lshlre...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/187738
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