[llvm] 0e0418f - [AArch64] Mark SP-only register classes as non-allocatable (#211549)

[via llvm-commits]

Author: Cullen Rhodes
Date: 2026-07-24T10:27:09+01:00
New Revision: 0e0418f2fd8f3144b0dd036bcd85cacab5b6b262

URL: https://github.com/llvm/llvm-project/commit/0e0418f2fd8f3144b0dd036bcd85cacab5b6b262
DIFF: https://github.com/llvm/llvm-project/commit/0e0418f2fd8f3144b0dd036bcd85cacab5b6b262.diff

LOG: [AArch64] Mark SP-only register classes as non-allocatable (#211549)

Reserved registers are not allocatable and since these are singleton
classes, they should be marked as such.

Assisted-by: codex

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64RegisterInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index b9d851cd3498d..5c4b5f147659f 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -222,8 +222,11 @@ def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> {
   let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID,0, 32>";
 }
 
-def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>;
-def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>;
+// SP/WSP are always reserved.
+let isAllocatable = 0 in {
+  def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>;
+  def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>;
+}
 
 def GPR64spPlus0Operand : AsmOperandClass {
   let Name = "GPR64sp0";