[llvm] 3cba294 - [TableGen] Add register-info statistics (#211528)

[via llvm-commits]

Author: Cullen Rhodes
Date: 2026-07-24T07:47:08+01:00
New Revision: 3cba2943a9d391e2ba301dd37948ef8b248bb031

URL: https://github.com/llvm/llvm-project/commit/3cba2943a9d391e2ba301dd37948ef8b248bb031
DIFF: https://github.com/llvm/llvm-project/commit/3cba2943a9d391e2ba301dd37948ef8b248bb031.diff

LOG: [TableGen] Add register-info statistics (#211528)

Add statistics for the numbers of explicit and synthesized register
classes, along with the number of register pressure sets. This makes
growth in the generated register model easier to spot since it can be
surprising.

Assisted-by: codex

Added: 
    llvm/test/TableGen/aarch64-register-info-stats.td

Modified: 
    llvm/utils/TableGen/RegisterInfoEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/TableGen/aarch64-register-info-stats.td b/llvm/test/TableGen/aarch64-register-info-stats.td
new file mode 100644
index 0000000000000..326a77743410d
--- /dev/null
+++ b/llvm/test/TableGen/aarch64-register-info-stats.td
@@ -0,0 +1,18 @@
+// REQUIRES: asserts
+// RUN: llvm-tblgen -gen-register-info -stats \
+// RUN:   -I %p/../../lib/Target/AArch64 -I %p/../../include \
+// RUN:   %s -o %t.inc 2>&1 | FileCheck %s
+
+// Keep changes to the size of AArch64's generated register model visible.
+
+include "llvm/Target/Target.td"
+include "AArch64RegisterInfo.td"
+
+def TestInstrInfo : InstrInfo;
+def TestTarget : Target {
+  let InstructionSet = TestInstrInfo;
+}
+
+// CHECK-DAG: 83 register-info-emitter - Number of explicit register classes
+// CHECK-DAG: 447 register-info-emitter - Number of synthesized register classes
+// CHECK-DAG: 190 register-info-emitter - Number of register pressure sets

diff  --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 786c4a1323c35..6c64330c1f374 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -24,6 +24,7 @@
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/SparseBitVector.h"
+#include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/CodeGenTypes/MachineValueType.h"
 #include "llvm/Support/Casting.h"
@@ -50,6 +51,12 @@
 
 using namespace llvm;
 
+#define DEBUG_TYPE "register-info-emitter"
+
+STATISTIC(NumExplicitRegClasses, "Number of explicit register classes");
+STATISTIC(NumSynthesizedRegClasses, "Number of synthesized register classes");
+STATISTIC(NumRegPressureSets, "Number of register pressure sets");
+
 static cl::OptionCategory RegisterInfoCat("Options for -gen-register-info");
 
 static cl::opt<bool>
@@ -70,6 +77,14 @@ class RegisterInfoEmitter {
   RegisterInfoEmitter(const RecordKeeper &R)
       : Records(R), Target(R), RegBank(Target.getRegBank()) {
     RegBank.computeDerivedInfo();
+
+    const auto &RegClasses = RegBank.getRegClasses();
+    NumExplicitRegClasses =
+        llvm::count_if(RegClasses, [](const CodeGenRegisterClass &RC) {
+          return RC.getDef() != nullptr;
+        });
+    NumSynthesizedRegClasses = RegClasses.size() - NumExplicitRegClasses;
+    NumRegPressureSets = RegBank.getNumRegPressureSets();
   }
 
   // runEnums - Print out enum values for all of the registers.