[llvm] [LSR] VScale doesn't occupy a register if it's a legal offset (PR #206754)

[Graham Hunter via llvm-commits]

huntergr-arm wrote:

> It's quite possible that AArch64TTIImpl::isLSRCostLess is wrong and we should be prioritizing instruction cost over number of registers (and it currently has a TODO about this). I'm too busy with other things right now to look into this right now, but may have some time in maybe a few weeks.

Oh, it's almost certainly wrong.

Looks like it hasn't been touched since I added the AArch64 override with the initial vscale-aware work; we were previously using the generic TTIImpl version, which didn't compare instruction counts at all.

I think there might have been a few regressions with instruction count first, which is why I have the TODO about finding something better -- I was thinking about prioritizing instruction count unless the number of registers was over a threshold, but I never had the time to experiment.



https://github.com/llvm/llvm-project/pull/206754