[llvm] [RISCV] Add custom lowering for fixed-vector `CLMUL`/`CLMULH` (PR #210429)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 23 08:52:44 PDT 2026
================
@@ -1,1795 +1,2909 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v,+zvbc < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVBC,RV32ZVBC64
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v,+zvbc < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVBC,RV64ZVBC64
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v,+experimental-zvbc32e < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVBC,RV32ZVBC32
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v,+experimental-zvbc32e < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVBC,RV64ZVBC32
define <1 x i32> @clmul_v1i32(<1 x i32> %x, <1 x i32> %y) nounwind {
-; CHECK-LABEL: clmul_v1i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 69905
-; CHECK-NEXT: lui a1, 139810
-; CHECK-NEXT: addi a0, a0, 273
-; CHECK-NEXT: addi a2, a1, 546
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vand.vx v10, v9, a0
-; CHECK-NEXT: lui a1, 559241
-; CHECK-NEXT: vand.vx v11, v8, a2
-; CHECK-NEXT: vand.vx v12, v9, a2
-; CHECK-NEXT: addi a1, a1, -1912
-; CHECK-NEXT: vand.vx v13, v8, a0
-; CHECK-NEXT: lui a3, 279620
-; CHECK-NEXT: vand.vx v14, v9, a1
-; CHECK-NEXT: addi a3, a3, 1092
-; CHECK-NEXT: vand.vx v15, v8, a3
-; CHECK-NEXT: vmul.vv v16, v11, v10
-; CHECK-NEXT: vmul.vv v17, v13, v12
-; CHECK-NEXT: vand.vx v9, v9, a3
-; CHECK-NEXT: vmul.vv v18, v11, v14
-; CHECK-NEXT: vmul.vv v19, v13, v10
-; CHECK-NEXT: vand.vx v8, v8, a1
-; CHECK-NEXT: vmul.vv v20, v15, v14
-; CHECK-NEXT: vmul.vv v21, v15, v9
-; CHECK-NEXT: vxor.vv v16, v17, v16
-; CHECK-NEXT: vmul.vv v17, v8, v9
-; CHECK-NEXT: vxor.vv v18, v19, v18
-; CHECK-NEXT: vmul.vv v19, v11, v12
-; CHECK-NEXT: vxor.vv v16, v16, v20
-; CHECK-NEXT: vmul.vv v20, v13, v9
-; CHECK-NEXT: vmul.vv v9, v11, v9
-; CHECK-NEXT: vxor.vv v11, v18, v21
-; CHECK-NEXT: vmul.vv v18, v8, v12
-; CHECK-NEXT: vxor.vv v16, v16, v17
-; CHECK-NEXT: vmul.vv v17, v15, v10
-; CHECK-NEXT: vmul.vv v13, v13, v14
-; CHECK-NEXT: vxor.vv v19, v20, v19
-; CHECK-NEXT: vmul.vv v12, v15, v12
-; CHECK-NEXT: vmul.vv v14, v8, v14
-; CHECK-NEXT: vand.vx v15, v16, a2
-; CHECK-NEXT: vxor.vv v11, v11, v18
-; CHECK-NEXT: vxor.vv v16, v19, v17
-; CHECK-NEXT: vxor.vv v9, v13, v9
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vand.vx v10, v11, a0
-; CHECK-NEXT: vxor.vv v11, v16, v14
-; CHECK-NEXT: vxor.vv v9, v9, v12
-; CHECK-NEXT: vor.vv v10, v10, v15
-; CHECK-NEXT: vand.vx v11, v11, a3
-; CHECK-NEXT: vxor.vv v8, v9, v8
-; CHECK-NEXT: vor.vv v9, v10, v11
-; CHECK-NEXT: vand.vx v8, v8, a1
-; CHECK-NEXT: vor.vv v8, v9, v8
-; CHECK-NEXT: ret
+; RV32V-LABEL: clmul_v1i32:
+; RV32V: # %bb.0:
+; RV32V-NEXT: lui a0, 69905
+; RV32V-NEXT: lui a1, 139810
+; RV32V-NEXT: addi a0, a0, 273
+; RV32V-NEXT: addi a2, a1, 546
+; RV32V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV32V-NEXT: vand.vx v10, v9, a0
+; RV32V-NEXT: lui a1, 559241
+; RV32V-NEXT: vand.vx v11, v8, a2
+; RV32V-NEXT: vand.vx v12, v9, a2
+; RV32V-NEXT: addi a1, a1, -1912
+; RV32V-NEXT: vand.vx v13, v8, a0
+; RV32V-NEXT: lui a3, 279620
+; RV32V-NEXT: vand.vx v14, v9, a1
+; RV32V-NEXT: addi a3, a3, 1092
+; RV32V-NEXT: vand.vx v15, v8, a3
+; RV32V-NEXT: vmul.vv v16, v11, v10
+; RV32V-NEXT: vmul.vv v17, v13, v12
+; RV32V-NEXT: vand.vx v9, v9, a3
+; RV32V-NEXT: vmul.vv v18, v11, v14
+; RV32V-NEXT: vmul.vv v19, v13, v10
+; RV32V-NEXT: vand.vx v8, v8, a1
+; RV32V-NEXT: vmul.vv v20, v15, v14
+; RV32V-NEXT: vmul.vv v21, v15, v9
+; RV32V-NEXT: vxor.vv v16, v17, v16
+; RV32V-NEXT: vmul.vv v17, v8, v9
+; RV32V-NEXT: vxor.vv v18, v19, v18
+; RV32V-NEXT: vmul.vv v19, v11, v12
+; RV32V-NEXT: vxor.vv v16, v16, v20
+; RV32V-NEXT: vmul.vv v20, v13, v9
+; RV32V-NEXT: vmul.vv v9, v11, v9
+; RV32V-NEXT: vxor.vv v11, v18, v21
+; RV32V-NEXT: vmul.vv v18, v8, v12
+; RV32V-NEXT: vxor.vv v16, v16, v17
+; RV32V-NEXT: vmul.vv v17, v15, v10
+; RV32V-NEXT: vmul.vv v13, v13, v14
+; RV32V-NEXT: vxor.vv v19, v20, v19
+; RV32V-NEXT: vmul.vv v12, v15, v12
+; RV32V-NEXT: vmul.vv v14, v8, v14
+; RV32V-NEXT: vand.vx v15, v16, a2
+; RV32V-NEXT: vxor.vv v11, v11, v18
+; RV32V-NEXT: vxor.vv v16, v19, v17
+; RV32V-NEXT: vxor.vv v9, v13, v9
+; RV32V-NEXT: vmul.vv v8, v8, v10
+; RV32V-NEXT: vand.vx v10, v11, a0
+; RV32V-NEXT: vxor.vv v11, v16, v14
+; RV32V-NEXT: vxor.vv v9, v9, v12
+; RV32V-NEXT: vor.vv v10, v10, v15
+; RV32V-NEXT: vand.vx v11, v11, a3
+; RV32V-NEXT: vxor.vv v8, v9, v8
+; RV32V-NEXT: vor.vv v9, v10, v11
+; RV32V-NEXT: vand.vx v8, v8, a1
+; RV32V-NEXT: vor.vv v8, v9, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v1i32:
+; RV64V: # %bb.0:
+; RV64V-NEXT: lui a0, 69905
+; RV64V-NEXT: lui a1, 139810
+; RV64V-NEXT: addi a0, a0, 273
+; RV64V-NEXT: addi a2, a1, 546
+; RV64V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64V-NEXT: vand.vx v10, v9, a0
+; RV64V-NEXT: lui a1, 559241
+; RV64V-NEXT: vand.vx v11, v8, a2
+; RV64V-NEXT: vand.vx v12, v9, a2
+; RV64V-NEXT: addi a1, a1, -1912
+; RV64V-NEXT: vand.vx v13, v8, a0
+; RV64V-NEXT: lui a3, 279620
+; RV64V-NEXT: vand.vx v14, v9, a1
+; RV64V-NEXT: addi a3, a3, 1092
+; RV64V-NEXT: vand.vx v15, v8, a3
+; RV64V-NEXT: vmul.vv v16, v11, v10
+; RV64V-NEXT: vmul.vv v17, v13, v12
+; RV64V-NEXT: vand.vx v9, v9, a3
+; RV64V-NEXT: vmul.vv v18, v11, v14
+; RV64V-NEXT: vmul.vv v19, v13, v10
+; RV64V-NEXT: vand.vx v8, v8, a1
+; RV64V-NEXT: vmul.vv v20, v15, v14
+; RV64V-NEXT: vmul.vv v21, v15, v9
+; RV64V-NEXT: vxor.vv v16, v17, v16
+; RV64V-NEXT: vmul.vv v17, v8, v9
+; RV64V-NEXT: vxor.vv v18, v19, v18
+; RV64V-NEXT: vmul.vv v19, v11, v12
+; RV64V-NEXT: vxor.vv v16, v16, v20
+; RV64V-NEXT: vmul.vv v20, v13, v9
+; RV64V-NEXT: vmul.vv v9, v11, v9
+; RV64V-NEXT: vxor.vv v11, v18, v21
+; RV64V-NEXT: vmul.vv v18, v8, v12
+; RV64V-NEXT: vxor.vv v16, v16, v17
+; RV64V-NEXT: vmul.vv v17, v15, v10
+; RV64V-NEXT: vmul.vv v13, v13, v14
+; RV64V-NEXT: vxor.vv v19, v20, v19
+; RV64V-NEXT: vmul.vv v12, v15, v12
+; RV64V-NEXT: vmul.vv v14, v8, v14
+; RV64V-NEXT: vand.vx v15, v16, a2
+; RV64V-NEXT: vxor.vv v11, v11, v18
+; RV64V-NEXT: vxor.vv v16, v19, v17
+; RV64V-NEXT: vxor.vv v9, v13, v9
+; RV64V-NEXT: vmul.vv v8, v8, v10
+; RV64V-NEXT: vand.vx v10, v11, a0
+; RV64V-NEXT: vxor.vv v11, v16, v14
+; RV64V-NEXT: vxor.vv v9, v9, v12
+; RV64V-NEXT: vor.vv v10, v10, v15
+; RV64V-NEXT: vand.vx v11, v11, a3
+; RV64V-NEXT: vxor.vv v8, v9, v8
+; RV64V-NEXT: vor.vv v9, v10, v11
+; RV64V-NEXT: vand.vx v8, v8, a1
+; RV64V-NEXT: vor.vv v8, v9, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v1i32:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf2 v10, v9
+; RV32ZVBC64-NEXT: vzext.vf2 v9, v8
+; RV32ZVBC64-NEXT: vclmul.vv v8, v9, v10
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v8, v8, 0
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v1i32:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64ZVBC64-NEXT: vzext.vf2 v10, v9
+; RV64ZVBC64-NEXT: vzext.vf2 v9, v8
+; RV64ZVBC64-NEXT: vclmul.vv v8, v9, v10
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v8, v8, 0
+; RV64ZVBC64-NEXT: ret
+;
+; RV32ZVBC32-LABEL: clmul_v1i32:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v1i32:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV64ZVBC32-NEXT: ret
%a = call <1 x i32> @llvm.clmul.v1i32(<1 x i32> %x, <1 x i32> %y)
ret <1 x i32> %a
}
define <2 x i32> @clmul_v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
-; CHECK-LABEL: clmul_v2i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 69905
-; CHECK-NEXT: lui a1, 139810
-; CHECK-NEXT: addi a0, a0, 273
-; CHECK-NEXT: addi a2, a1, 546
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vand.vx v10, v9, a0
-; CHECK-NEXT: lui a1, 559241
-; CHECK-NEXT: vand.vx v11, v8, a2
-; CHECK-NEXT: vand.vx v12, v9, a2
-; CHECK-NEXT: addi a1, a1, -1912
-; CHECK-NEXT: vand.vx v13, v8, a0
-; CHECK-NEXT: lui a3, 279620
-; CHECK-NEXT: vand.vx v14, v9, a1
-; CHECK-NEXT: addi a3, a3, 1092
-; CHECK-NEXT: vand.vx v15, v8, a3
-; CHECK-NEXT: vmul.vv v16, v11, v10
-; CHECK-NEXT: vmul.vv v17, v13, v12
-; CHECK-NEXT: vand.vx v9, v9, a3
-; CHECK-NEXT: vmul.vv v18, v11, v14
-; CHECK-NEXT: vmul.vv v19, v13, v10
-; CHECK-NEXT: vand.vx v8, v8, a1
-; CHECK-NEXT: vmul.vv v20, v15, v14
-; CHECK-NEXT: vmul.vv v21, v15, v9
-; CHECK-NEXT: vxor.vv v16, v17, v16
-; CHECK-NEXT: vmul.vv v17, v8, v9
-; CHECK-NEXT: vxor.vv v18, v19, v18
-; CHECK-NEXT: vmul.vv v19, v11, v12
-; CHECK-NEXT: vxor.vv v16, v16, v20
-; CHECK-NEXT: vmul.vv v20, v13, v9
-; CHECK-NEXT: vmul.vv v9, v11, v9
-; CHECK-NEXT: vxor.vv v11, v18, v21
-; CHECK-NEXT: vmul.vv v18, v8, v12
-; CHECK-NEXT: vxor.vv v16, v16, v17
-; CHECK-NEXT: vmul.vv v17, v15, v10
-; CHECK-NEXT: vmul.vv v13, v13, v14
-; CHECK-NEXT: vxor.vv v19, v20, v19
-; CHECK-NEXT: vmul.vv v12, v15, v12
-; CHECK-NEXT: vmul.vv v14, v8, v14
-; CHECK-NEXT: vand.vx v15, v16, a2
-; CHECK-NEXT: vxor.vv v11, v11, v18
-; CHECK-NEXT: vxor.vv v16, v19, v17
-; CHECK-NEXT: vxor.vv v9, v13, v9
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vand.vx v10, v11, a0
-; CHECK-NEXT: vxor.vv v11, v16, v14
-; CHECK-NEXT: vxor.vv v9, v9, v12
-; CHECK-NEXT: vor.vv v10, v10, v15
-; CHECK-NEXT: vand.vx v11, v11, a3
-; CHECK-NEXT: vxor.vv v8, v9, v8
-; CHECK-NEXT: vor.vv v9, v10, v11
-; CHECK-NEXT: vand.vx v8, v8, a1
-; CHECK-NEXT: vor.vv v8, v9, v8
-; CHECK-NEXT: ret
+; RV32V-LABEL: clmul_v2i32:
+; RV32V: # %bb.0:
+; RV32V-NEXT: lui a0, 69905
+; RV32V-NEXT: lui a1, 139810
+; RV32V-NEXT: addi a0, a0, 273
+; RV32V-NEXT: addi a2, a1, 546
+; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32V-NEXT: vand.vx v10, v9, a0
+; RV32V-NEXT: lui a1, 559241
+; RV32V-NEXT: vand.vx v11, v8, a2
+; RV32V-NEXT: vand.vx v12, v9, a2
+; RV32V-NEXT: addi a1, a1, -1912
+; RV32V-NEXT: vand.vx v13, v8, a0
+; RV32V-NEXT: lui a3, 279620
+; RV32V-NEXT: vand.vx v14, v9, a1
+; RV32V-NEXT: addi a3, a3, 1092
+; RV32V-NEXT: vand.vx v15, v8, a3
+; RV32V-NEXT: vmul.vv v16, v11, v10
+; RV32V-NEXT: vmul.vv v17, v13, v12
+; RV32V-NEXT: vand.vx v9, v9, a3
+; RV32V-NEXT: vmul.vv v18, v11, v14
+; RV32V-NEXT: vmul.vv v19, v13, v10
+; RV32V-NEXT: vand.vx v8, v8, a1
+; RV32V-NEXT: vmul.vv v20, v15, v14
+; RV32V-NEXT: vmul.vv v21, v15, v9
+; RV32V-NEXT: vxor.vv v16, v17, v16
+; RV32V-NEXT: vmul.vv v17, v8, v9
+; RV32V-NEXT: vxor.vv v18, v19, v18
+; RV32V-NEXT: vmul.vv v19, v11, v12
+; RV32V-NEXT: vxor.vv v16, v16, v20
+; RV32V-NEXT: vmul.vv v20, v13, v9
+; RV32V-NEXT: vmul.vv v9, v11, v9
+; RV32V-NEXT: vxor.vv v11, v18, v21
+; RV32V-NEXT: vmul.vv v18, v8, v12
+; RV32V-NEXT: vxor.vv v16, v16, v17
+; RV32V-NEXT: vmul.vv v17, v15, v10
+; RV32V-NEXT: vmul.vv v13, v13, v14
+; RV32V-NEXT: vxor.vv v19, v20, v19
+; RV32V-NEXT: vmul.vv v12, v15, v12
+; RV32V-NEXT: vmul.vv v14, v8, v14
+; RV32V-NEXT: vand.vx v15, v16, a2
+; RV32V-NEXT: vxor.vv v11, v11, v18
+; RV32V-NEXT: vxor.vv v16, v19, v17
+; RV32V-NEXT: vxor.vv v9, v13, v9
+; RV32V-NEXT: vmul.vv v8, v8, v10
+; RV32V-NEXT: vand.vx v10, v11, a0
+; RV32V-NEXT: vxor.vv v11, v16, v14
+; RV32V-NEXT: vxor.vv v9, v9, v12
+; RV32V-NEXT: vor.vv v10, v10, v15
+; RV32V-NEXT: vand.vx v11, v11, a3
+; RV32V-NEXT: vxor.vv v8, v9, v8
+; RV32V-NEXT: vor.vv v9, v10, v11
+; RV32V-NEXT: vand.vx v8, v8, a1
+; RV32V-NEXT: vor.vv v8, v9, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v2i32:
+; RV64V: # %bb.0:
+; RV64V-NEXT: lui a0, 69905
+; RV64V-NEXT: lui a1, 139810
+; RV64V-NEXT: addi a0, a0, 273
+; RV64V-NEXT: addi a2, a1, 546
+; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64V-NEXT: vand.vx v10, v9, a0
+; RV64V-NEXT: lui a1, 559241
+; RV64V-NEXT: vand.vx v11, v8, a2
+; RV64V-NEXT: vand.vx v12, v9, a2
+; RV64V-NEXT: addi a1, a1, -1912
+; RV64V-NEXT: vand.vx v13, v8, a0
+; RV64V-NEXT: lui a3, 279620
+; RV64V-NEXT: vand.vx v14, v9, a1
+; RV64V-NEXT: addi a3, a3, 1092
+; RV64V-NEXT: vand.vx v15, v8, a3
+; RV64V-NEXT: vmul.vv v16, v11, v10
+; RV64V-NEXT: vmul.vv v17, v13, v12
+; RV64V-NEXT: vand.vx v9, v9, a3
+; RV64V-NEXT: vmul.vv v18, v11, v14
+; RV64V-NEXT: vmul.vv v19, v13, v10
+; RV64V-NEXT: vand.vx v8, v8, a1
+; RV64V-NEXT: vmul.vv v20, v15, v14
+; RV64V-NEXT: vmul.vv v21, v15, v9
+; RV64V-NEXT: vxor.vv v16, v17, v16
+; RV64V-NEXT: vmul.vv v17, v8, v9
+; RV64V-NEXT: vxor.vv v18, v19, v18
+; RV64V-NEXT: vmul.vv v19, v11, v12
+; RV64V-NEXT: vxor.vv v16, v16, v20
+; RV64V-NEXT: vmul.vv v20, v13, v9
+; RV64V-NEXT: vmul.vv v9, v11, v9
+; RV64V-NEXT: vxor.vv v11, v18, v21
+; RV64V-NEXT: vmul.vv v18, v8, v12
+; RV64V-NEXT: vxor.vv v16, v16, v17
+; RV64V-NEXT: vmul.vv v17, v15, v10
+; RV64V-NEXT: vmul.vv v13, v13, v14
+; RV64V-NEXT: vxor.vv v19, v20, v19
+; RV64V-NEXT: vmul.vv v12, v15, v12
+; RV64V-NEXT: vmul.vv v14, v8, v14
+; RV64V-NEXT: vand.vx v15, v16, a2
+; RV64V-NEXT: vxor.vv v11, v11, v18
+; RV64V-NEXT: vxor.vv v16, v19, v17
+; RV64V-NEXT: vxor.vv v9, v13, v9
+; RV64V-NEXT: vmul.vv v8, v8, v10
+; RV64V-NEXT: vand.vx v10, v11, a0
+; RV64V-NEXT: vxor.vv v11, v16, v14
+; RV64V-NEXT: vxor.vv v9, v9, v12
+; RV64V-NEXT: vor.vv v10, v10, v15
+; RV64V-NEXT: vand.vx v11, v11, a3
+; RV64V-NEXT: vxor.vv v8, v9, v8
+; RV64V-NEXT: vor.vv v9, v10, v11
+; RV64V-NEXT: vand.vx v8, v8, a1
+; RV64V-NEXT: vor.vv v8, v9, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v2i32:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf2 v10, v9
+; RV32ZVBC64-NEXT: vzext.vf2 v9, v8
+; RV32ZVBC64-NEXT: vclmul.vv v8, v9, v10
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v8, v8, 0
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v2i32:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64ZVBC64-NEXT: vzext.vf2 v10, v9
+; RV64ZVBC64-NEXT: vzext.vf2 v9, v8
+; RV64ZVBC64-NEXT: vclmul.vv v8, v9, v10
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v8, v8, 0
+; RV64ZVBC64-NEXT: ret
+;
+; RV32ZVBC32-LABEL: clmul_v2i32:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v2i32:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV64ZVBC32-NEXT: ret
%a = call <2 x i32> @llvm.clmul.v2i32(<2 x i32> %x, <2 x i32> %y)
ret <2 x i32> %a
}
define <4 x i32> @clmul_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
-; CHECK-LABEL: clmul_v4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 69905
-; CHECK-NEXT: addi a0, a0, 273
-; CHECK-NEXT: lui a1, 139810
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vand.vx v10, v9, a0
-; CHECK-NEXT: addi a1, a1, 546
-; CHECK-NEXT: vand.vx v11, v8, a1
-; CHECK-NEXT: vand.vx v12, v9, a1
-; CHECK-NEXT: vand.vx v13, v8, a0
-; CHECK-NEXT: vmul.vv v14, v11, v10
-; CHECK-NEXT: vmul.vv v15, v13, v12
-; CHECK-NEXT: lui a2, 559241
-; CHECK-NEXT: addi a2, a2, -1912
-; CHECK-NEXT: lui a3, 279620
-; CHECK-NEXT: vand.vx v16, v9, a2
-; CHECK-NEXT: addi a3, a3, 1092
-; CHECK-NEXT: vand.vx v17, v8, a3
-; CHECK-NEXT: vxor.vv v14, v15, v14
-; CHECK-NEXT: vmul.vv v15, v17, v16
-; CHECK-NEXT: vand.vx v9, v9, a3
-; CHECK-NEXT: vand.vx v8, v8, a2
-; CHECK-NEXT: vmul.vv v18, v11, v16
-; CHECK-NEXT: vmul.vv v19, v13, v10
-; CHECK-NEXT: vxor.vv v14, v14, v15
-; CHECK-NEXT: vmul.vv v15, v8, v9
-; CHECK-NEXT: vmul.vv v20, v17, v9
-; CHECK-NEXT: vxor.vv v18, v19, v18
-; CHECK-NEXT: vmul.vv v19, v8, v12
-; CHECK-NEXT: vxor.vv v14, v14, v15
-; CHECK-NEXT: vxor.vv v15, v18, v20
-; CHECK-NEXT: vand.vx v14, v14, a1
-; CHECK-NEXT: vxor.vv v15, v15, v19
-; CHECK-NEXT: vmul.vv v18, v11, v12
-; CHECK-NEXT: vmul.vv v19, v13, v9
-; CHECK-NEXT: vand.vx v15, v15, a0
-; CHECK-NEXT: vmul.vv v20, v17, v10
-; CHECK-NEXT: vor.vv v14, v15, v14
-; CHECK-NEXT: vxor.vv v15, v19, v18
-; CHECK-NEXT: vmul.vv v9, v11, v9
-; CHECK-NEXT: vmul.vv v11, v13, v16
-; CHECK-NEXT: vxor.vv v13, v15, v20
-; CHECK-NEXT: vmul.vv v15, v8, v16
-; CHECK-NEXT: vmul.vv v12, v17, v12
-; CHECK-NEXT: vxor.vv v9, v11, v9
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vxor.vv v10, v13, v15
-; CHECK-NEXT: vxor.vv v9, v9, v12
-; CHECK-NEXT: vand.vx v10, v10, a3
-; CHECK-NEXT: vxor.vv v8, v9, v8
-; CHECK-NEXT: vor.vv v9, v14, v10
-; CHECK-NEXT: vand.vx v8, v8, a2
-; CHECK-NEXT: vor.vv v8, v9, v8
-; CHECK-NEXT: ret
+; RV32V-LABEL: clmul_v4i32:
+; RV32V: # %bb.0:
+; RV32V-NEXT: lui a0, 69905
+; RV32V-NEXT: addi a0, a0, 273
+; RV32V-NEXT: lui a1, 139810
+; RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32V-NEXT: vand.vx v10, v9, a0
+; RV32V-NEXT: addi a1, a1, 546
+; RV32V-NEXT: vand.vx v11, v8, a1
+; RV32V-NEXT: vand.vx v12, v9, a1
+; RV32V-NEXT: vand.vx v13, v8, a0
+; RV32V-NEXT: vmul.vv v14, v11, v10
+; RV32V-NEXT: vmul.vv v15, v13, v12
+; RV32V-NEXT: lui a2, 559241
+; RV32V-NEXT: addi a2, a2, -1912
+; RV32V-NEXT: lui a3, 279620
+; RV32V-NEXT: vand.vx v16, v9, a2
+; RV32V-NEXT: addi a3, a3, 1092
+; RV32V-NEXT: vand.vx v17, v8, a3
+; RV32V-NEXT: vxor.vv v14, v15, v14
+; RV32V-NEXT: vmul.vv v15, v17, v16
+; RV32V-NEXT: vand.vx v9, v9, a3
+; RV32V-NEXT: vand.vx v8, v8, a2
+; RV32V-NEXT: vmul.vv v18, v11, v16
+; RV32V-NEXT: vmul.vv v19, v13, v10
+; RV32V-NEXT: vxor.vv v14, v14, v15
+; RV32V-NEXT: vmul.vv v15, v8, v9
+; RV32V-NEXT: vmul.vv v20, v17, v9
+; RV32V-NEXT: vxor.vv v18, v19, v18
+; RV32V-NEXT: vmul.vv v19, v8, v12
+; RV32V-NEXT: vxor.vv v14, v14, v15
+; RV32V-NEXT: vxor.vv v15, v18, v20
+; RV32V-NEXT: vand.vx v14, v14, a1
+; RV32V-NEXT: vxor.vv v15, v15, v19
+; RV32V-NEXT: vmul.vv v18, v11, v12
+; RV32V-NEXT: vmul.vv v19, v13, v9
+; RV32V-NEXT: vand.vx v15, v15, a0
+; RV32V-NEXT: vmul.vv v20, v17, v10
+; RV32V-NEXT: vor.vv v14, v15, v14
+; RV32V-NEXT: vxor.vv v15, v19, v18
+; RV32V-NEXT: vmul.vv v9, v11, v9
+; RV32V-NEXT: vmul.vv v11, v13, v16
+; RV32V-NEXT: vxor.vv v13, v15, v20
+; RV32V-NEXT: vmul.vv v15, v8, v16
+; RV32V-NEXT: vmul.vv v12, v17, v12
+; RV32V-NEXT: vxor.vv v9, v11, v9
+; RV32V-NEXT: vmul.vv v8, v8, v10
+; RV32V-NEXT: vxor.vv v10, v13, v15
+; RV32V-NEXT: vxor.vv v9, v9, v12
+; RV32V-NEXT: vand.vx v10, v10, a3
+; RV32V-NEXT: vxor.vv v8, v9, v8
+; RV32V-NEXT: vor.vv v9, v14, v10
+; RV32V-NEXT: vand.vx v8, v8, a2
+; RV32V-NEXT: vor.vv v8, v9, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v4i32:
+; RV64V: # %bb.0:
+; RV64V-NEXT: lui a0, 69905
+; RV64V-NEXT: addi a0, a0, 273
+; RV64V-NEXT: lui a1, 139810
+; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64V-NEXT: vand.vx v10, v9, a0
+; RV64V-NEXT: addi a1, a1, 546
+; RV64V-NEXT: vand.vx v11, v8, a1
+; RV64V-NEXT: vand.vx v12, v9, a1
+; RV64V-NEXT: vand.vx v13, v8, a0
+; RV64V-NEXT: vmul.vv v14, v11, v10
+; RV64V-NEXT: vmul.vv v15, v13, v12
+; RV64V-NEXT: lui a2, 559241
+; RV64V-NEXT: addi a2, a2, -1912
+; RV64V-NEXT: lui a3, 279620
+; RV64V-NEXT: vand.vx v16, v9, a2
+; RV64V-NEXT: addi a3, a3, 1092
+; RV64V-NEXT: vand.vx v17, v8, a3
+; RV64V-NEXT: vxor.vv v14, v15, v14
+; RV64V-NEXT: vmul.vv v15, v17, v16
+; RV64V-NEXT: vand.vx v9, v9, a3
+; RV64V-NEXT: vand.vx v8, v8, a2
+; RV64V-NEXT: vmul.vv v18, v11, v16
+; RV64V-NEXT: vmul.vv v19, v13, v10
+; RV64V-NEXT: vxor.vv v14, v14, v15
+; RV64V-NEXT: vmul.vv v15, v8, v9
+; RV64V-NEXT: vmul.vv v20, v17, v9
+; RV64V-NEXT: vxor.vv v18, v19, v18
+; RV64V-NEXT: vmul.vv v19, v8, v12
+; RV64V-NEXT: vxor.vv v14, v14, v15
+; RV64V-NEXT: vxor.vv v15, v18, v20
+; RV64V-NEXT: vand.vx v14, v14, a1
+; RV64V-NEXT: vxor.vv v15, v15, v19
+; RV64V-NEXT: vmul.vv v18, v11, v12
+; RV64V-NEXT: vmul.vv v19, v13, v9
+; RV64V-NEXT: vand.vx v15, v15, a0
+; RV64V-NEXT: vmul.vv v20, v17, v10
+; RV64V-NEXT: vor.vv v14, v15, v14
+; RV64V-NEXT: vxor.vv v15, v19, v18
+; RV64V-NEXT: vmul.vv v9, v11, v9
+; RV64V-NEXT: vmul.vv v11, v13, v16
+; RV64V-NEXT: vxor.vv v13, v15, v20
+; RV64V-NEXT: vmul.vv v15, v8, v16
+; RV64V-NEXT: vmul.vv v12, v17, v12
+; RV64V-NEXT: vxor.vv v9, v11, v9
+; RV64V-NEXT: vmul.vv v8, v8, v10
+; RV64V-NEXT: vxor.vv v10, v13, v15
+; RV64V-NEXT: vxor.vv v9, v9, v12
+; RV64V-NEXT: vand.vx v10, v10, a3
+; RV64V-NEXT: vxor.vv v8, v9, v8
+; RV64V-NEXT: vor.vv v9, v14, v10
+; RV64V-NEXT: vand.vx v8, v8, a2
+; RV64V-NEXT: vor.vv v8, v9, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v4i32:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf2 v10, v9
+; RV32ZVBC64-NEXT: vzext.vf2 v12, v8
+; RV32ZVBC64-NEXT: vclmul.vv v10, v12, v10
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v8, v10, 0
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v4i32:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64ZVBC64-NEXT: vzext.vf2 v10, v9
+; RV64ZVBC64-NEXT: vzext.vf2 v12, v8
+; RV64ZVBC64-NEXT: vclmul.vv v10, v12, v10
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v8, v10, 0
+; RV64ZVBC64-NEXT: ret
+;
+; RV32ZVBC32-LABEL: clmul_v4i32:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v4i32:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV64ZVBC32-NEXT: ret
%a = call <4 x i32> @llvm.clmul.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %a
}
define <8 x i32> @clmul_v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
-; CHECK-LABEL: clmul_v8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 69905
-; CHECK-NEXT: addi a0, a0, 273
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vand.vx v10, v8, a0
-; CHECK-NEXT: lui a1, 139810
-; CHECK-NEXT: addi a1, a1, 546
-; CHECK-NEXT: vand.vx v12, v8, a1
-; CHECK-NEXT: lui a2, 559241
-; CHECK-NEXT: addi a2, a2, -1912
-; CHECK-NEXT: vand.vx v14, v8, a2
-; CHECK-NEXT: vmul.vv v16, v12, v10
-; CHECK-NEXT: lui a3, 279620
-; CHECK-NEXT: addi a3, a3, 1092
-; CHECK-NEXT: vand.vx v8, v8, a3
-; CHECK-NEXT: vmul.vv v18, v8, v14
-; CHECK-NEXT: vxor.vv v16, v16, v16
-; CHECK-NEXT: vxor.vv v16, v16, v18
-; CHECK-NEXT: vxor.vv v16, v16, v18
-; CHECK-NEXT: vand.vx v16, v16, a1
-; CHECK-NEXT: vmul.vv v18, v14, v12
-; CHECK-NEXT: vmul.vv v20, v10, v10
-; CHECK-NEXT: vmul.vv v22, v8, v8
-; CHECK-NEXT: vxor.vv v20, v20, v18
-; CHECK-NEXT: vxor.vv v20, v20, v22
-; CHECK-NEXT: vxor.vv v18, v20, v18
-; CHECK-NEXT: vand.vx v18, v18, a0
-; CHECK-NEXT: vmul.vv v20, v8, v10
-; CHECK-NEXT: vmul.vv v22, v12, v12
-; CHECK-NEXT: vor.vv v16, v18, v16
-; CHECK-NEXT: vxor.vv v18, v20, v22
-; CHECK-NEXT: vmul.vv v22, v14, v14
-; CHECK-NEXT: vxor.vv v18, v18, v20
-; CHECK-NEXT: vxor.vv v18, v18, v22
-; CHECK-NEXT: vand.vx v18, v18, a3
-; CHECK-NEXT: vmul.vv v8, v12, v8
-; CHECK-NEXT: vmul.vv v10, v10, v14
-; CHECK-NEXT: vor.vv v12, v16, v18
-; CHECK-NEXT: vxor.vv v14, v10, v8
-; CHECK-NEXT: vxor.vv v8, v14, v8
-; CHECK-NEXT: vxor.vv v8, v8, v10
-; CHECK-NEXT: vand.vx v8, v8, a2
-; CHECK-NEXT: vor.vv v8, v12, v8
-; CHECK-NEXT: ret
+; RV32V-LABEL: clmul_v8i32:
+; RV32V: # %bb.0:
+; RV32V-NEXT: lui a0, 69905
+; RV32V-NEXT: addi a0, a0, 273
+; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32V-NEXT: vand.vx v10, v8, a0
+; RV32V-NEXT: lui a1, 139810
+; RV32V-NEXT: addi a1, a1, 546
+; RV32V-NEXT: vand.vx v12, v8, a1
+; RV32V-NEXT: lui a2, 559241
+; RV32V-NEXT: addi a2, a2, -1912
+; RV32V-NEXT: vand.vx v14, v8, a2
+; RV32V-NEXT: vmul.vv v16, v12, v10
+; RV32V-NEXT: lui a3, 279620
+; RV32V-NEXT: addi a3, a3, 1092
+; RV32V-NEXT: vand.vx v8, v8, a3
+; RV32V-NEXT: vmul.vv v18, v8, v14
+; RV32V-NEXT: vxor.vv v16, v16, v16
+; RV32V-NEXT: vxor.vv v16, v16, v18
+; RV32V-NEXT: vxor.vv v16, v16, v18
+; RV32V-NEXT: vand.vx v16, v16, a1
+; RV32V-NEXT: vmul.vv v18, v14, v12
+; RV32V-NEXT: vmul.vv v20, v10, v10
+; RV32V-NEXT: vmul.vv v22, v8, v8
+; RV32V-NEXT: vxor.vv v20, v20, v18
+; RV32V-NEXT: vxor.vv v20, v20, v22
+; RV32V-NEXT: vxor.vv v18, v20, v18
+; RV32V-NEXT: vand.vx v18, v18, a0
+; RV32V-NEXT: vmul.vv v20, v8, v10
+; RV32V-NEXT: vmul.vv v22, v12, v12
+; RV32V-NEXT: vor.vv v16, v18, v16
+; RV32V-NEXT: vxor.vv v18, v20, v22
+; RV32V-NEXT: vmul.vv v22, v14, v14
+; RV32V-NEXT: vxor.vv v18, v18, v20
+; RV32V-NEXT: vxor.vv v18, v18, v22
+; RV32V-NEXT: vand.vx v18, v18, a3
+; RV32V-NEXT: vmul.vv v8, v12, v8
+; RV32V-NEXT: vmul.vv v10, v10, v14
+; RV32V-NEXT: vor.vv v12, v16, v18
+; RV32V-NEXT: vxor.vv v14, v10, v8
+; RV32V-NEXT: vxor.vv v8, v14, v8
+; RV32V-NEXT: vxor.vv v8, v8, v10
+; RV32V-NEXT: vand.vx v8, v8, a2
+; RV32V-NEXT: vor.vv v8, v12, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v8i32:
+; RV64V: # %bb.0:
+; RV64V-NEXT: lui a0, 69905
+; RV64V-NEXT: addi a0, a0, 273
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64V-NEXT: vand.vx v10, v8, a0
+; RV64V-NEXT: lui a1, 139810
+; RV64V-NEXT: addi a1, a1, 546
+; RV64V-NEXT: vand.vx v12, v8, a1
+; RV64V-NEXT: lui a2, 559241
+; RV64V-NEXT: addi a2, a2, -1912
+; RV64V-NEXT: vand.vx v14, v8, a2
+; RV64V-NEXT: vmul.vv v16, v12, v10
+; RV64V-NEXT: lui a3, 279620
+; RV64V-NEXT: addi a3, a3, 1092
+; RV64V-NEXT: vand.vx v8, v8, a3
+; RV64V-NEXT: vmul.vv v18, v8, v14
+; RV64V-NEXT: vxor.vv v16, v16, v16
+; RV64V-NEXT: vxor.vv v16, v16, v18
+; RV64V-NEXT: vxor.vv v16, v16, v18
+; RV64V-NEXT: vand.vx v16, v16, a1
+; RV64V-NEXT: vmul.vv v18, v14, v12
+; RV64V-NEXT: vmul.vv v20, v10, v10
+; RV64V-NEXT: vmul.vv v22, v8, v8
+; RV64V-NEXT: vxor.vv v20, v20, v18
+; RV64V-NEXT: vxor.vv v20, v20, v22
+; RV64V-NEXT: vxor.vv v18, v20, v18
+; RV64V-NEXT: vand.vx v18, v18, a0
+; RV64V-NEXT: vmul.vv v20, v8, v10
+; RV64V-NEXT: vmul.vv v22, v12, v12
+; RV64V-NEXT: vor.vv v16, v18, v16
+; RV64V-NEXT: vxor.vv v18, v20, v22
+; RV64V-NEXT: vmul.vv v22, v14, v14
+; RV64V-NEXT: vxor.vv v18, v18, v20
+; RV64V-NEXT: vxor.vv v18, v18, v22
+; RV64V-NEXT: vand.vx v18, v18, a3
+; RV64V-NEXT: vmul.vv v8, v12, v8
+; RV64V-NEXT: vmul.vv v10, v10, v14
+; RV64V-NEXT: vor.vv v12, v16, v18
+; RV64V-NEXT: vxor.vv v14, v10, v8
+; RV64V-NEXT: vxor.vv v8, v14, v8
+; RV64V-NEXT: vxor.vv v8, v8, v10
+; RV64V-NEXT: vand.vx v8, v8, a2
+; RV64V-NEXT: vor.vv v8, v12, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v8i32:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf2 v12, v8
+; RV32ZVBC64-NEXT: vclmul.vv v12, v12, v12
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v8, v12, 0
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v8i32:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64ZVBC64-NEXT: vzext.vf2 v12, v8
+; RV64ZVBC64-NEXT: vclmul.vv v12, v12, v12
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v8, v12, 0
+; RV64ZVBC64-NEXT: ret
+;
+; RV32ZVBC32-LABEL: clmul_v8i32:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v8
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v8i32:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v8
+; RV64ZVBC32-NEXT: ret
%a = call <8 x i32> @llvm.clmul.v8i32(<8 x i32> %x, <8 x i32> %x)
ret <8 x i32> %a
}
define <16 x i32> @clmul_v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
-; CHECK-LABEL: clmul_v16i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: lui a1, 69905
-; CHECK-NEXT: addi a1, a1, 273
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; CHECK-NEXT: vand.vx v16, v12, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: mv a2, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: lui a0, 139810
-; CHECK-NEXT: addi a3, a0, 546
-; CHECK-NEXT: vand.vx v24, v8, a3
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vand.vx v20, v12, a3
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: mv a2, a0
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vand.vx v28, v8, a1
-; CHECK-NEXT: lui a0, 559241
-; CHECK-NEXT: addi a0, a0, -1912
-; CHECK-NEXT: vand.vx v4, v12, a0
-; CHECK-NEXT: vmul.vv v16, v24, v16
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: mv a4, a2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, a2, a4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vmul.vv v16, v28, v20
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs4r.v v28, (a2) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: lui a2, 279620
-; CHECK-NEXT: addi a2, a2, 1092
-; CHECK-NEXT: vand.vx v0, v8, a2
-; CHECK-NEXT: vmul.vv v16, v0, v4
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 2
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vxor.vv v20, v24, v20
-; CHECK-NEXT: vxor.vv v16, v20, v16
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 2
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vand.vx v12, v12, a2
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vmul.vv v16, v8, v12
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 4
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v16, v24, v4
-; CHECK-NEXT: addi a4, sp, 16
-; CHECK-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v16, v28, v16
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 2
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vxor.vv v20, v20, v28
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 2
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: addi a4, sp, 16
-; CHECK-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vxor.vv v28, v16, v20
-; CHECK-NEXT: vmul.vv v20, v0, v12
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 2
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 2
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v16, v8, v16
-; CHECK-NEXT: vxor.vv v20, v28, v20
-; CHECK-NEXT: vxor.vv v16, v20, v16
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 2
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vand.vx v20, v20, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs4r.v v20, (a3) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vand.vx v16, v16, a1
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: mv a3, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: mv a3, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v16, v24, v16
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v28, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v24, v28, v12
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: mv a3, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vor.vv v20, v20, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: mv a3, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vxor.vv v24, v24, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: mv a3, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v20, v0, v16
-; CHECK-NEXT: vmul.vv v16, v8, v4
-; CHECK-NEXT: vxor.vv v20, v24, v20
-; CHECK-NEXT: vxor.vv v16, v20, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v12, v20, v12
-; CHECK-NEXT: vmul.vv v20, v28, v4
-; CHECK-NEXT: vand.vx v16, v16, a2
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vor.vv v16, v24, v16
-; CHECK-NEXT: vxor.vv v12, v20, v12
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v20, v0, v20
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vmul.vv v8, v8, v24
-; CHECK-NEXT: vxor.vv v12, v12, v20
-; CHECK-NEXT: vxor.vv v8, v12, v8
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vor.vv v8, v16, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; RV32V-LABEL: clmul_v16i32:
+; RV32V: # %bb.0:
+; RV32V-NEXT: addi sp, sp, -16
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a1, a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: sub sp, sp, a0
+; RV32V-NEXT: lui a1, 69905
+; RV32V-NEXT: addi a1, a1, 273
+; RV32V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32V-NEXT: vand.vx v16, v12, a1
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 3
+; RV32V-NEXT: mv a2, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a2
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: lui a0, 139810
+; RV32V-NEXT: addi a3, a0, 546
+; RV32V-NEXT: vand.vx v24, v8, a3
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 4
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vand.vx v20, v12, a3
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a2, a0
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, a0, a2
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vand.vx v28, v8, a1
+; RV32V-NEXT: lui a0, 559241
+; RV32V-NEXT: addi a0, a0, -1912
+; RV32V-NEXT: vand.vx v4, v12, a0
+; RV32V-NEXT: vmul.vv v16, v24, v16
+; RV32V-NEXT: csrr a2, vlenb
+; RV32V-NEXT: slli a2, a2, 2
+; RV32V-NEXT: mv a4, a2
+; RV32V-NEXT: slli a2, a2, 1
+; RV32V-NEXT: add a2, a2, a4
+; RV32V-NEXT: add a2, sp, a2
+; RV32V-NEXT: addi a2, a2, 16
+; RV32V-NEXT: vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vmul.vv v16, v28, v20
+; RV32V-NEXT: csrr a2, vlenb
+; RV32V-NEXT: slli a2, a2, 2
+; RV32V-NEXT: add a2, sp, a2
+; RV32V-NEXT: addi a2, a2, 16
+; RV32V-NEXT: vs4r.v v28, (a2) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: csrr a2, vlenb
+; RV32V-NEXT: slli a2, a2, 3
+; RV32V-NEXT: add a2, sp, a2
+; RV32V-NEXT: addi a2, a2, 16
+; RV32V-NEXT: vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: lui a2, 279620
+; RV32V-NEXT: addi a2, a2, 1092
+; RV32V-NEXT: vand.vx v0, v8, a2
+; RV32V-NEXT: vmul.vv v16, v0, v4
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 2
+; RV32V-NEXT: mv a5, a4
+; RV32V-NEXT: slli a4, a4, 1
+; RV32V-NEXT: add a4, a4, a5
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 3
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vxor.vv v20, v24, v20
+; RV32V-NEXT: vxor.vv v16, v20, v16
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 2
+; RV32V-NEXT: mv a5, a4
+; RV32V-NEXT: slli a4, a4, 1
+; RV32V-NEXT: add a4, a4, a5
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vand.vx v12, v12, a2
+; RV32V-NEXT: vand.vx v8, v8, a0
+; RV32V-NEXT: vmul.vv v16, v8, v12
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 3
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 4
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v16, v24, v4
+; RV32V-NEXT: addi a4, sp, 16
+; RV32V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 3
+; RV32V-NEXT: mv a5, a4
+; RV32V-NEXT: slli a4, a4, 1
+; RV32V-NEXT: add a4, a4, a5
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v16, v28, v16
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 2
+; RV32V-NEXT: mv a5, a4
+; RV32V-NEXT: slli a4, a4, 1
+; RV32V-NEXT: add a4, a4, a5
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 3
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vxor.vv v20, v20, v28
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 2
+; RV32V-NEXT: mv a5, a4
+; RV32V-NEXT: slli a4, a4, 1
+; RV32V-NEXT: add a4, a4, a5
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: addi a4, sp, 16
+; RV32V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vxor.vv v28, v16, v20
+; RV32V-NEXT: vmul.vv v20, v0, v12
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 2
+; RV32V-NEXT: mv a5, a4
+; RV32V-NEXT: slli a4, a4, 2
+; RV32V-NEXT: add a4, a4, a5
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v16, v8, v16
+; RV32V-NEXT: vxor.vv v20, v28, v20
+; RV32V-NEXT: vxor.vv v16, v20, v16
+; RV32V-NEXT: csrr a4, vlenb
+; RV32V-NEXT: slli a4, a4, 2
+; RV32V-NEXT: mv a5, a4
+; RV32V-NEXT: slli a4, a4, 1
+; RV32V-NEXT: add a4, a4, a5
+; RV32V-NEXT: add a4, sp, a4
+; RV32V-NEXT: addi a4, a4, 16
+; RV32V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vand.vx v20, v20, a3
+; RV32V-NEXT: csrr a3, vlenb
+; RV32V-NEXT: slli a3, a3, 3
+; RV32V-NEXT: add a3, sp, a3
+; RV32V-NEXT: addi a3, a3, 16
+; RV32V-NEXT: vs4r.v v20, (a3) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vand.vx v16, v16, a1
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: mv a3, a1
+; RV32V-NEXT: slli a1, a1, 1
+; RV32V-NEXT: add a1, a1, a3
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: mv a3, a1
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: add a1, a1, a3
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v16, v24, v16
+; RV32V-NEXT: addi a1, sp, 16
+; RV32V-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v28, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v24, v28, v12
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: mv a3, a1
+; RV32V-NEXT: slli a1, a1, 1
+; RV32V-NEXT: add a1, a1, a3
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 3
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vor.vv v20, v20, v16
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: mv a3, a1
+; RV32V-NEXT: slli a1, a1, 1
+; RV32V-NEXT: add a1, a1, a3
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: addi a1, sp, 16
+; RV32V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vxor.vv v24, v24, v16
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 3
+; RV32V-NEXT: mv a3, a1
+; RV32V-NEXT: slli a1, a1, 1
+; RV32V-NEXT: add a1, a1, a3
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v20, v0, v16
+; RV32V-NEXT: vmul.vv v16, v8, v4
+; RV32V-NEXT: vxor.vv v20, v24, v20
+; RV32V-NEXT: vxor.vv v16, v20, v16
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 4
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v12, v20, v12
+; RV32V-NEXT: vmul.vv v20, v28, v4
+; RV32V-NEXT: vand.vx v16, v16, a2
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: mv a2, a1
+; RV32V-NEXT: slli a1, a1, 1
+; RV32V-NEXT: add a1, a1, a2
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vor.vv v16, v24, v16
+; RV32V-NEXT: vxor.vv v12, v20, v12
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: mv a2, a1
+; RV32V-NEXT: slli a1, a1, 2
+; RV32V-NEXT: add a1, a1, a2
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v20, v0, v20
+; RV32V-NEXT: csrr a1, vlenb
+; RV32V-NEXT: slli a1, a1, 3
+; RV32V-NEXT: mv a2, a1
+; RV32V-NEXT: slli a1, a1, 1
+; RV32V-NEXT: add a1, a1, a2
+; RV32V-NEXT: add a1, sp, a1
+; RV32V-NEXT: addi a1, a1, 16
+; RV32V-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v8, v8, v24
+; RV32V-NEXT: vxor.vv v12, v12, v20
+; RV32V-NEXT: vxor.vv v8, v12, v8
+; RV32V-NEXT: vand.vx v8, v8, a0
+; RV32V-NEXT: vor.vv v8, v16, v8
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a1, a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add sp, sp, a0
+; RV32V-NEXT: addi sp, sp, 16
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v16i32:
+; RV64V: # %bb.0:
+; RV64V-NEXT: addi sp, sp, -16
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 2
+; RV64V-NEXT: mv a1, a0
+; RV64V-NEXT: slli a0, a0, 1
+; RV64V-NEXT: add a1, a1, a0
+; RV64V-NEXT: slli a0, a0, 1
+; RV64V-NEXT: add a0, a0, a1
+; RV64V-NEXT: sub sp, sp, a0
+; RV64V-NEXT: lui a1, 69905
+; RV64V-NEXT: addi a1, a1, 273
+; RV64V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV64V-NEXT: vand.vx v16, v12, a1
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 3
+; RV64V-NEXT: mv a2, a0
+; RV64V-NEXT: slli a0, a0, 1
+; RV64V-NEXT: add a0, a0, a2
+; RV64V-NEXT: add a0, sp, a0
+; RV64V-NEXT: addi a0, a0, 16
+; RV64V-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: lui a0, 139810
+; RV64V-NEXT: addi a3, a0, 546
+; RV64V-NEXT: vand.vx v24, v8, a3
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 4
+; RV64V-NEXT: add a0, sp, a0
+; RV64V-NEXT: addi a0, a0, 16
+; RV64V-NEXT: vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vand.vx v20, v12, a3
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 2
+; RV64V-NEXT: mv a2, a0
+; RV64V-NEXT: slli a0, a0, 2
+; RV64V-NEXT: add a0, a0, a2
+; RV64V-NEXT: add a0, sp, a0
+; RV64V-NEXT: addi a0, a0, 16
+; RV64V-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vand.vx v28, v8, a1
+; RV64V-NEXT: lui a0, 559241
+; RV64V-NEXT: addi a0, a0, -1912
+; RV64V-NEXT: vand.vx v4, v12, a0
+; RV64V-NEXT: vmul.vv v16, v24, v16
+; RV64V-NEXT: csrr a2, vlenb
+; RV64V-NEXT: slli a2, a2, 2
+; RV64V-NEXT: mv a4, a2
+; RV64V-NEXT: slli a2, a2, 1
+; RV64V-NEXT: add a2, a2, a4
+; RV64V-NEXT: add a2, sp, a2
+; RV64V-NEXT: addi a2, a2, 16
+; RV64V-NEXT: vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vmul.vv v16, v28, v20
+; RV64V-NEXT: csrr a2, vlenb
+; RV64V-NEXT: slli a2, a2, 2
+; RV64V-NEXT: add a2, sp, a2
+; RV64V-NEXT: addi a2, a2, 16
+; RV64V-NEXT: vs4r.v v28, (a2) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a2, vlenb
+; RV64V-NEXT: slli a2, a2, 3
+; RV64V-NEXT: add a2, sp, a2
+; RV64V-NEXT: addi a2, a2, 16
+; RV64V-NEXT: vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: lui a2, 279620
+; RV64V-NEXT: addi a2, a2, 1092
+; RV64V-NEXT: vand.vx v0, v8, a2
+; RV64V-NEXT: vmul.vv v16, v0, v4
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 3
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v20, v24, v20
+; RV64V-NEXT: vxor.vv v16, v20, v16
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vand.vx v12, v12, a2
+; RV64V-NEXT: vand.vx v8, v8, a0
+; RV64V-NEXT: vmul.vv v16, v8, v12
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 3
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 4
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v16, v24, v4
+; RV64V-NEXT: addi a4, sp, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 3
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v16, v28, v16
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 3
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v20, v20, v28
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: addi a4, sp, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v28, v16, v20
+; RV64V-NEXT: vmul.vv v20, v0, v12
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v16, v8, v16
+; RV64V-NEXT: vxor.vv v20, v28, v20
+; RV64V-NEXT: vxor.vv v16, v20, v16
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vand.vx v20, v20, a3
+; RV64V-NEXT: csrr a3, vlenb
+; RV64V-NEXT: slli a3, a3, 3
+; RV64V-NEXT: add a3, sp, a3
+; RV64V-NEXT: addi a3, a3, 16
+; RV64V-NEXT: vs4r.v v20, (a3) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vand.vx v16, v16, a1
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v16, v24, v16
+; RV64V-NEXT: addi a1, sp, 16
+; RV64V-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v28, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v24, v28, v12
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vor.vv v20, v20, v16
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: addi a1, sp, 16
+; RV64V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v24, v24, v16
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 3
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v20, v0, v16
+; RV64V-NEXT: vmul.vv v16, v8, v4
+; RV64V-NEXT: vxor.vv v20, v24, v20
+; RV64V-NEXT: vxor.vv v16, v20, v16
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 4
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v12, v20, v12
+; RV64V-NEXT: vmul.vv v20, v28, v4
+; RV64V-NEXT: vand.vx v16, v16, a2
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a2, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vor.vv v16, v24, v16
+; RV64V-NEXT: vxor.vv v12, v20, v12
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a2, a1
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v20, v0, v20
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 3
+; RV64V-NEXT: mv a2, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v8, v8, v24
+; RV64V-NEXT: vxor.vv v12, v12, v20
+; RV64V-NEXT: vxor.vv v8, v12, v8
+; RV64V-NEXT: vand.vx v8, v8, a0
+; RV64V-NEXT: vor.vv v8, v16, v8
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 2
+; RV64V-NEXT: mv a1, a0
+; RV64V-NEXT: slli a0, a0, 1
+; RV64V-NEXT: add a1, a1, a0
+; RV64V-NEXT: slli a0, a0, 1
+; RV64V-NEXT: add a0, a0, a1
+; RV64V-NEXT: add sp, sp, a0
+; RV64V-NEXT: addi sp, sp, 16
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v16i32:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf2 v16, v12
+; RV32ZVBC64-NEXT: vzext.vf2 v24, v8
+; RV32ZVBC64-NEXT: vclmul.vv v16, v24, v16
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v8, v16, 0
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v16i32:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64ZVBC64-NEXT: vzext.vf2 v16, v12
+; RV64ZVBC64-NEXT: vzext.vf2 v24, v8
+; RV64ZVBC64-NEXT: vclmul.vv v16, v24, v16
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v8, v16, 0
+; RV64ZVBC64-NEXT: ret
+;
+; RV32ZVBC32-LABEL: clmul_v16i32:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v12
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v16i32:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v12
+; RV64ZVBC32-NEXT: ret
%a = call <16 x i32> @llvm.clmul.v16i32(<16 x i32> %x, <16 x i32> %y)
ret <16 x i32> %a
}
define <1 x i64> @clmul_v1i64(<1 x i64> %x, <1 x i64> %y) nounwind {
-; RV32-LABEL: clmul_v1i64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 69905
-; RV32-NEXT: addi a0, a0, 273
-; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v13, a0
-; RV32-NEXT: lui a0, 139810
-; RV32-NEXT: addi a0, a0, 546
-; RV32-NEXT: vmv.v.x v14, a0
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT: vand.vv v10, v9, v13
-; RV32-NEXT: vand.vv v11, v9, v14
-; RV32-NEXT: vand.vv v15, v8, v13
-; RV32-NEXT: vand.vv v16, v8, v14
-; RV32-NEXT: vmul.vv v17, v15, v11
-; RV32-NEXT: lui a0, 559241
-; RV32-NEXT: addi a0, a0, -1912
-; RV32-NEXT: vmul.vv v18, v16, v10
-; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v12, a0
-; RV32-NEXT: lui a0, 279620
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT: vxor.vi v17, v17, 0
-; RV32-NEXT: addi a0, a0, 1092
-; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v19, a0
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; RV32-NEXT: vxor.vv v17, v17, v18
-; RV32-NEXT: vand.vv v18, v9, v12
-; RV32-NEXT: vand.vv v20, v8, v19
-; RV32-NEXT: vmul.vv v21, v15, v10
-; RV32-NEXT: vand.vv v9, v9, v19
-; RV32-NEXT: vmul.vv v22, v16, v18
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vxor.vi v21, v21, 0
-; RV32-NEXT: vmul.vv v23, v20, v9
-; RV32-NEXT: vmul.vv v24, v20, v18
-; RV32-NEXT: vxor.vv v21, v21, v22
-; RV32-NEXT: vmul.vv v22, v8, v11
-; RV32-NEXT: vmul.vv v25, v8, v9
-; RV32-NEXT: vxor.vv v21, v21, v23
-; RV32-NEXT: vxor.vv v17, v17, v24
-; RV32-NEXT: vxor.vv v21, v21, v22
-; RV32-NEXT: vxor.vv v17, v17, v25
-; RV32-NEXT: vand.vv v13, v21, v13
-; RV32-NEXT: vmul.vv v21, v15, v9
-; RV32-NEXT: vand.vv v14, v17, v14
-; RV32-NEXT: vor.vi v13, v13, 0
-; RV32-NEXT: vmul.vv v17, v16, v11
-; RV32-NEXT: vxor.vi v21, v21, 0
-; RV32-NEXT: vmul.vv v22, v20, v10
-; RV32-NEXT: vor.vv v13, v13, v14
-; RV32-NEXT: vxor.vv v14, v21, v17
-; RV32-NEXT: vmul.vv v15, v15, v18
-; RV32-NEXT: vxor.vv v14, v14, v22
-; RV32-NEXT: vmul.vv v9, v16, v9
-; RV32-NEXT: vmul.vv v16, v8, v18
-; RV32-NEXT: vxor.vi v15, v15, 0
-; RV32-NEXT: vmul.vv v11, v20, v11
-; RV32-NEXT: vxor.vv v9, v15, v9
-; RV32-NEXT: vmul.vv v8, v8, v10
-; RV32-NEXT: vxor.vv v10, v14, v16
-; RV32-NEXT: vxor.vv v9, v9, v11
-; RV32-NEXT: vand.vv v10, v10, v19
-; RV32-NEXT: vxor.vv v8, v9, v8
-; RV32-NEXT: vor.vv v9, v13, v10
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vor.vv v8, v9, v8
-; RV32-NEXT: ret
+; RV32V-LABEL: clmul_v1i64:
+; RV32V: # %bb.0:
+; RV32V-NEXT: lui a0, 69905
+; RV32V-NEXT: addi a0, a0, 273
+; RV32V-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV32V-NEXT: vmv.v.x v13, a0
+; RV32V-NEXT: lui a0, 139810
+; RV32V-NEXT: addi a0, a0, 546
+; RV32V-NEXT: vmv.v.x v14, a0
+; RV32V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV32V-NEXT: vand.vv v10, v9, v13
+; RV32V-NEXT: vand.vv v11, v9, v14
+; RV32V-NEXT: vand.vv v15, v8, v13
+; RV32V-NEXT: vand.vv v16, v8, v14
+; RV32V-NEXT: vmul.vv v17, v15, v11
+; RV32V-NEXT: lui a0, 559241
+; RV32V-NEXT: addi a0, a0, -1912
+; RV32V-NEXT: vmul.vv v18, v16, v10
+; RV32V-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV32V-NEXT: vmv.v.x v12, a0
+; RV32V-NEXT: lui a0, 279620
+; RV32V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV32V-NEXT: vxor.vi v17, v17, 0
+; RV32V-NEXT: addi a0, a0, 1092
+; RV32V-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV32V-NEXT: vmv.v.x v19, a0
+; RV32V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV32V-NEXT: vxor.vv v17, v17, v18
+; RV32V-NEXT: vand.vv v18, v9, v12
+; RV32V-NEXT: vand.vv v20, v8, v19
+; RV32V-NEXT: vmul.vv v21, v15, v10
+; RV32V-NEXT: vand.vv v9, v9, v19
+; RV32V-NEXT: vmul.vv v22, v16, v18
+; RV32V-NEXT: vand.vv v8, v8, v12
+; RV32V-NEXT: vxor.vi v21, v21, 0
+; RV32V-NEXT: vmul.vv v23, v20, v9
+; RV32V-NEXT: vmul.vv v24, v20, v18
+; RV32V-NEXT: vxor.vv v21, v21, v22
+; RV32V-NEXT: vmul.vv v22, v8, v11
+; RV32V-NEXT: vmul.vv v25, v8, v9
+; RV32V-NEXT: vxor.vv v21, v21, v23
+; RV32V-NEXT: vxor.vv v17, v17, v24
+; RV32V-NEXT: vxor.vv v21, v21, v22
+; RV32V-NEXT: vxor.vv v17, v17, v25
+; RV32V-NEXT: vand.vv v13, v21, v13
+; RV32V-NEXT: vmul.vv v21, v15, v9
+; RV32V-NEXT: vand.vv v14, v17, v14
+; RV32V-NEXT: vor.vi v13, v13, 0
+; RV32V-NEXT: vmul.vv v17, v16, v11
+; RV32V-NEXT: vxor.vi v21, v21, 0
+; RV32V-NEXT: vmul.vv v22, v20, v10
+; RV32V-NEXT: vor.vv v13, v13, v14
+; RV32V-NEXT: vxor.vv v14, v21, v17
+; RV32V-NEXT: vmul.vv v15, v15, v18
+; RV32V-NEXT: vxor.vv v14, v14, v22
+; RV32V-NEXT: vmul.vv v9, v16, v9
+; RV32V-NEXT: vmul.vv v16, v8, v18
+; RV32V-NEXT: vxor.vi v15, v15, 0
+; RV32V-NEXT: vmul.vv v11, v20, v11
+; RV32V-NEXT: vxor.vv v9, v15, v9
+; RV32V-NEXT: vmul.vv v8, v8, v10
+; RV32V-NEXT: vxor.vv v10, v14, v16
+; RV32V-NEXT: vxor.vv v9, v9, v11
+; RV32V-NEXT: vand.vv v10, v10, v19
+; RV32V-NEXT: vxor.vv v8, v9, v8
+; RV32V-NEXT: vor.vv v9, v13, v10
+; RV32V-NEXT: vand.vv v8, v8, v12
+; RV32V-NEXT: vor.vv v8, v9, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v1i64:
+; RV64V: # %bb.0:
+; RV64V-NEXT: lui a0, 69905
+; RV64V-NEXT: addi a0, a0, 273
+; RV64V-NEXT: lui a1, 139810
+; RV64V-NEXT: slli a2, a0, 32
+; RV64V-NEXT: addi a1, a1, 546
+; RV64V-NEXT: add a0, a0, a2
+; RV64V-NEXT: slli a2, a1, 32
+; RV64V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64V-NEXT: vand.vx v10, v9, a0
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: vand.vx v11, v8, a1
+; RV64V-NEXT: vand.vx v12, v9, a1
+; RV64V-NEXT: vand.vx v13, v8, a0
+; RV64V-NEXT: vmul.vv v14, v11, v10
+; RV64V-NEXT: vmul.vv v15, v13, v12
+; RV64V-NEXT: lui a2, 279620
+; RV64V-NEXT: lui a3, %hi(.LCPI5_0)
+; RV64V-NEXT: addi a2, a2, 1092
+; RV64V-NEXT: ld a3, %lo(.LCPI5_0)(a3)
+; RV64V-NEXT: slli a4, a2, 32
+; RV64V-NEXT: add a2, a2, a4
+; RV64V-NEXT: vand.vx v16, v8, a2
+; RV64V-NEXT: vand.vx v17, v9, a3
+; RV64V-NEXT: vxor.vv v14, v15, v14
+; RV64V-NEXT: vmul.vv v15, v16, v17
+; RV64V-NEXT: vand.vx v8, v8, a3
+; RV64V-NEXT: vand.vx v9, v9, a2
+; RV64V-NEXT: vmul.vv v18, v11, v17
+; RV64V-NEXT: vmul.vv v19, v13, v10
+; RV64V-NEXT: vxor.vv v14, v14, v15
+; RV64V-NEXT: vmul.vv v15, v8, v9
+; RV64V-NEXT: vmul.vv v20, v16, v9
+; RV64V-NEXT: vxor.vv v18, v19, v18
+; RV64V-NEXT: vmul.vv v19, v8, v12
+; RV64V-NEXT: vxor.vv v14, v14, v15
+; RV64V-NEXT: vxor.vv v15, v18, v20
+; RV64V-NEXT: vand.vx v14, v14, a1
+; RV64V-NEXT: vxor.vv v15, v15, v19
+; RV64V-NEXT: vmul.vv v18, v11, v12
+; RV64V-NEXT: vmul.vv v19, v13, v9
+; RV64V-NEXT: vand.vx v15, v15, a0
+; RV64V-NEXT: vmul.vv v20, v16, v10
+; RV64V-NEXT: vor.vv v14, v15, v14
+; RV64V-NEXT: vxor.vv v15, v19, v18
+; RV64V-NEXT: vmul.vv v9, v11, v9
+; RV64V-NEXT: vmul.vv v11, v13, v17
+; RV64V-NEXT: vxor.vv v13, v15, v20
+; RV64V-NEXT: vmul.vv v15, v8, v17
+; RV64V-NEXT: vmul.vv v12, v16, v12
+; RV64V-NEXT: vxor.vv v9, v11, v9
+; RV64V-NEXT: vmul.vv v8, v8, v10
+; RV64V-NEXT: vxor.vv v10, v13, v15
+; RV64V-NEXT: vxor.vv v9, v9, v12
+; RV64V-NEXT: vand.vx v10, v10, a2
+; RV64V-NEXT: vxor.vv v8, v9, v8
+; RV64V-NEXT: vor.vv v9, v14, v10
+; RV64V-NEXT: vand.vx v8, v8, a3
+; RV64V-NEXT: vor.vv v8, v9, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v1i64:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV32ZVBC64-NEXT: vclmul.vv v8, v8, v9
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v1i64:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64ZVBC64-NEXT: vclmul.vv v8, v8, v9
+; RV64ZVBC64-NEXT: ret
;
-; RV64-LABEL: clmul_v1i64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 69905
-; RV64-NEXT: addi a0, a0, 273
-; RV64-NEXT: lui a1, 139810
-; RV64-NEXT: slli a2, a0, 32
-; RV64-NEXT: addi a1, a1, 546
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: slli a2, a1, 32
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v10, v9, a0
-; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: vand.vx v11, v8, a1
-; RV64-NEXT: vand.vx v12, v9, a1
-; RV64-NEXT: vand.vx v13, v8, a0
-; RV64-NEXT: vmul.vv v14, v11, v10
-; RV64-NEXT: vmul.vv v15, v13, v12
-; RV64-NEXT: lui a2, 279620
-; RV64-NEXT: lui a3, %hi(.LCPI5_0)
-; RV64-NEXT: addi a2, a2, 1092
-; RV64-NEXT: ld a3, %lo(.LCPI5_0)(a3)
-; RV64-NEXT: slli a4, a2, 32
-; RV64-NEXT: add a2, a2, a4
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vand.vx v17, v9, a3
-; RV64-NEXT: vxor.vv v14, v15, v14
-; RV64-NEXT: vmul.vv v15, v16, v17
-; RV64-NEXT: vand.vx v8, v8, a3
-; RV64-NEXT: vand.vx v9, v9, a2
-; RV64-NEXT: vmul.vv v18, v11, v17
-; RV64-NEXT: vmul.vv v19, v13, v10
-; RV64-NEXT: vxor.vv v14, v14, v15
-; RV64-NEXT: vmul.vv v15, v8, v9
-; RV64-NEXT: vmul.vv v20, v16, v9
-; RV64-NEXT: vxor.vv v18, v19, v18
-; RV64-NEXT: vmul.vv v19, v8, v12
-; RV64-NEXT: vxor.vv v14, v14, v15
-; RV64-NEXT: vxor.vv v15, v18, v20
-; RV64-NEXT: vand.vx v14, v14, a1
-; RV64-NEXT: vxor.vv v15, v15, v19
-; RV64-NEXT: vmul.vv v18, v11, v12
-; RV64-NEXT: vmul.vv v19, v13, v9
-; RV64-NEXT: vand.vx v15, v15, a0
-; RV64-NEXT: vmul.vv v20, v16, v10
-; RV64-NEXT: vor.vv v14, v15, v14
-; RV64-NEXT: vxor.vv v15, v19, v18
-; RV64-NEXT: vmul.vv v9, v11, v9
-; RV64-NEXT: vmul.vv v11, v13, v17
-; RV64-NEXT: vxor.vv v13, v15, v20
-; RV64-NEXT: vmul.vv v15, v8, v17
-; RV64-NEXT: vmul.vv v12, v16, v12
-; RV64-NEXT: vxor.vv v9, v11, v9
-; RV64-NEXT: vmul.vv v8, v8, v10
-; RV64-NEXT: vxor.vv v10, v13, v15
-; RV64-NEXT: vxor.vv v9, v9, v12
-; RV64-NEXT: vand.vx v10, v10, a2
-; RV64-NEXT: vxor.vv v8, v9, v8
-; RV64-NEXT: vor.vv v9, v14, v10
-; RV64-NEXT: vand.vx v8, v8, a3
-; RV64-NEXT: vor.vv v8, v9, v8
-; RV64-NEXT: ret
+; RV32ZVBC32-LABEL: clmul_v1i64:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: li a0, 32
+; RV32ZVBC32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV32ZVBC32-NEXT: vnsrl.wx v10, v8, a0
+; RV32ZVBC32-NEXT: vnsrl.wi v11, v9, 0
+; RV32ZVBC32-NEXT: vnsrl.wx v9, v9, a0
+; RV32ZVBC32-NEXT: vnsrl.wi v8, v8, 0
+; RV32ZVBC32-NEXT: vclmul.vv v10, v10, v11
+; RV32ZVBC32-NEXT: vclmul.vv v9, v8, v9
+; RV32ZVBC32-NEXT: vxor.vv v9, v9, v10
+; RV32ZVBC32-NEXT: vclmulh.vv v10, v8, v11
+; RV32ZVBC32-NEXT: vxor.vv v9, v10, v9
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32ZVBC32-NEXT: vzext.vf2 v10, v9
+; RV32ZVBC32-NEXT: vsll.vx v9, v10, a0
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v11
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32ZVBC32-NEXT: vzext.vf2 v10, v8
+; RV32ZVBC32-NEXT: vor.vv v8, v10, v9
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v1i64:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: li a0, 32
+; RV64ZVBC32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64ZVBC32-NEXT: vnsrl.wx v10, v8, a0
+; RV64ZVBC32-NEXT: vnsrl.wi v11, v9, 0
+; RV64ZVBC32-NEXT: vnsrl.wx v9, v9, a0
+; RV64ZVBC32-NEXT: vnsrl.wi v8, v8, 0
+; RV64ZVBC32-NEXT: vclmul.vv v10, v10, v11
+; RV64ZVBC32-NEXT: vclmul.vv v9, v8, v9
+; RV64ZVBC32-NEXT: vxor.vv v9, v9, v10
+; RV64ZVBC32-NEXT: vclmulh.vv v10, v8, v11
+; RV64ZVBC32-NEXT: vxor.vv v9, v10, v9
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64ZVBC32-NEXT: vzext.vf2 v10, v9
+; RV64ZVBC32-NEXT: vsll.vx v9, v10, a0
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v11
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64ZVBC32-NEXT: vzext.vf2 v10, v8
+; RV64ZVBC32-NEXT: vor.vv v8, v10, v9
+; RV64ZVBC32-NEXT: ret
%a = call <1 x i64> @llvm.clmul.v1i64(<1 x i64> %x, <1 x i64> %y)
ret <1 x i64> %a
}
define <2 x i64> @clmul_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
-; RV32-LABEL: clmul_v2i64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 69905
-; RV32-NEXT: addi a0, a0, 273
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v13, a0
-; RV32-NEXT: lui a0, 139810
-; RV32-NEXT: addi a0, a0, 546
-; RV32-NEXT: vmv.v.x v14, a0
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vand.vv v10, v9, v13
-; RV32-NEXT: vand.vv v11, v9, v14
-; RV32-NEXT: vand.vv v15, v8, v13
-; RV32-NEXT: vand.vv v16, v8, v14
-; RV32-NEXT: vmul.vv v17, v15, v11
-; RV32-NEXT: lui a0, 559241
-; RV32-NEXT: addi a0, a0, -1912
-; RV32-NEXT: vmul.vv v18, v16, v10
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v12, a0
-; RV32-NEXT: lui a0, 279620
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vxor.vi v17, v17, 0
-; RV32-NEXT: addi a0, a0, 1092
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v19, a0
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vxor.vv v17, v17, v18
-; RV32-NEXT: vand.vv v18, v9, v12
-; RV32-NEXT: vand.vv v20, v8, v19
-; RV32-NEXT: vmul.vv v21, v15, v10
-; RV32-NEXT: vand.vv v9, v9, v19
-; RV32-NEXT: vmul.vv v22, v16, v18
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vxor.vi v21, v21, 0
-; RV32-NEXT: vmul.vv v23, v20, v9
-; RV32-NEXT: vmul.vv v24, v20, v18
-; RV32-NEXT: vxor.vv v21, v21, v22
-; RV32-NEXT: vmul.vv v22, v8, v11
-; RV32-NEXT: vmul.vv v25, v8, v9
-; RV32-NEXT: vxor.vv v21, v21, v23
-; RV32-NEXT: vxor.vv v17, v17, v24
-; RV32-NEXT: vxor.vv v21, v21, v22
-; RV32-NEXT: vxor.vv v17, v17, v25
-; RV32-NEXT: vand.vv v13, v21, v13
-; RV32-NEXT: vmul.vv v21, v15, v9
-; RV32-NEXT: vand.vv v14, v17, v14
-; RV32-NEXT: vor.vi v13, v13, 0
-; RV32-NEXT: vmul.vv v17, v16, v11
-; RV32-NEXT: vxor.vi v21, v21, 0
-; RV32-NEXT: vmul.vv v22, v20, v10
-; RV32-NEXT: vor.vv v13, v13, v14
-; RV32-NEXT: vxor.vv v14, v21, v17
-; RV32-NEXT: vmul.vv v15, v15, v18
-; RV32-NEXT: vxor.vv v14, v14, v22
-; RV32-NEXT: vmul.vv v9, v16, v9
-; RV32-NEXT: vmul.vv v16, v8, v18
-; RV32-NEXT: vxor.vi v15, v15, 0
-; RV32-NEXT: vmul.vv v11, v20, v11
-; RV32-NEXT: vxor.vv v9, v15, v9
-; RV32-NEXT: vmul.vv v8, v8, v10
-; RV32-NEXT: vxor.vv v10, v14, v16
-; RV32-NEXT: vxor.vv v9, v9, v11
-; RV32-NEXT: vand.vv v10, v10, v19
-; RV32-NEXT: vxor.vv v8, v9, v8
-; RV32-NEXT: vor.vv v9, v13, v10
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vor.vv v8, v9, v8
-; RV32-NEXT: ret
+; RV32V-LABEL: clmul_v2i64:
+; RV32V: # %bb.0:
+; RV32V-NEXT: lui a0, 69905
+; RV32V-NEXT: addi a0, a0, 273
+; RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32V-NEXT: vmv.v.x v13, a0
+; RV32V-NEXT: lui a0, 139810
+; RV32V-NEXT: addi a0, a0, 546
+; RV32V-NEXT: vmv.v.x v14, a0
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32V-NEXT: vand.vv v10, v9, v13
+; RV32V-NEXT: vand.vv v11, v9, v14
+; RV32V-NEXT: vand.vv v15, v8, v13
+; RV32V-NEXT: vand.vv v16, v8, v14
+; RV32V-NEXT: vmul.vv v17, v15, v11
+; RV32V-NEXT: lui a0, 559241
+; RV32V-NEXT: addi a0, a0, -1912
+; RV32V-NEXT: vmul.vv v18, v16, v10
+; RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32V-NEXT: vmv.v.x v12, a0
+; RV32V-NEXT: lui a0, 279620
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32V-NEXT: vxor.vi v17, v17, 0
+; RV32V-NEXT: addi a0, a0, 1092
+; RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32V-NEXT: vmv.v.x v19, a0
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32V-NEXT: vxor.vv v17, v17, v18
+; RV32V-NEXT: vand.vv v18, v9, v12
+; RV32V-NEXT: vand.vv v20, v8, v19
+; RV32V-NEXT: vmul.vv v21, v15, v10
+; RV32V-NEXT: vand.vv v9, v9, v19
+; RV32V-NEXT: vmul.vv v22, v16, v18
+; RV32V-NEXT: vand.vv v8, v8, v12
+; RV32V-NEXT: vxor.vi v21, v21, 0
+; RV32V-NEXT: vmul.vv v23, v20, v9
+; RV32V-NEXT: vmul.vv v24, v20, v18
+; RV32V-NEXT: vxor.vv v21, v21, v22
+; RV32V-NEXT: vmul.vv v22, v8, v11
+; RV32V-NEXT: vmul.vv v25, v8, v9
+; RV32V-NEXT: vxor.vv v21, v21, v23
+; RV32V-NEXT: vxor.vv v17, v17, v24
+; RV32V-NEXT: vxor.vv v21, v21, v22
+; RV32V-NEXT: vxor.vv v17, v17, v25
+; RV32V-NEXT: vand.vv v13, v21, v13
+; RV32V-NEXT: vmul.vv v21, v15, v9
+; RV32V-NEXT: vand.vv v14, v17, v14
+; RV32V-NEXT: vor.vi v13, v13, 0
+; RV32V-NEXT: vmul.vv v17, v16, v11
+; RV32V-NEXT: vxor.vi v21, v21, 0
+; RV32V-NEXT: vmul.vv v22, v20, v10
+; RV32V-NEXT: vor.vv v13, v13, v14
+; RV32V-NEXT: vxor.vv v14, v21, v17
+; RV32V-NEXT: vmul.vv v15, v15, v18
+; RV32V-NEXT: vxor.vv v14, v14, v22
+; RV32V-NEXT: vmul.vv v9, v16, v9
+; RV32V-NEXT: vmul.vv v16, v8, v18
+; RV32V-NEXT: vxor.vi v15, v15, 0
+; RV32V-NEXT: vmul.vv v11, v20, v11
+; RV32V-NEXT: vxor.vv v9, v15, v9
+; RV32V-NEXT: vmul.vv v8, v8, v10
+; RV32V-NEXT: vxor.vv v10, v14, v16
+; RV32V-NEXT: vxor.vv v9, v9, v11
+; RV32V-NEXT: vand.vv v10, v10, v19
+; RV32V-NEXT: vxor.vv v8, v9, v8
+; RV32V-NEXT: vor.vv v9, v13, v10
+; RV32V-NEXT: vand.vv v8, v8, v12
+; RV32V-NEXT: vor.vv v8, v9, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v2i64:
+; RV64V: # %bb.0:
+; RV64V-NEXT: lui a0, 69905
+; RV64V-NEXT: addi a0, a0, 273
+; RV64V-NEXT: lui a1, 139810
+; RV64V-NEXT: slli a2, a0, 32
+; RV64V-NEXT: addi a1, a1, 546
+; RV64V-NEXT: add a0, a0, a2
+; RV64V-NEXT: slli a2, a1, 32
+; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64V-NEXT: vand.vx v10, v9, a0
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: vand.vx v11, v8, a1
+; RV64V-NEXT: vand.vx v12, v9, a1
+; RV64V-NEXT: vand.vx v13, v8, a0
+; RV64V-NEXT: vmul.vv v14, v11, v10
+; RV64V-NEXT: vmul.vv v15, v13, v12
+; RV64V-NEXT: lui a2, 279620
+; RV64V-NEXT: lui a3, %hi(.LCPI6_0)
+; RV64V-NEXT: addi a2, a2, 1092
+; RV64V-NEXT: ld a3, %lo(.LCPI6_0)(a3)
+; RV64V-NEXT: slli a4, a2, 32
+; RV64V-NEXT: add a2, a2, a4
+; RV64V-NEXT: vand.vx v16, v8, a2
+; RV64V-NEXT: vand.vx v17, v9, a3
+; RV64V-NEXT: vxor.vv v14, v15, v14
+; RV64V-NEXT: vmul.vv v15, v16, v17
+; RV64V-NEXT: vand.vx v8, v8, a3
+; RV64V-NEXT: vand.vx v9, v9, a2
+; RV64V-NEXT: vmul.vv v18, v11, v17
+; RV64V-NEXT: vmul.vv v19, v13, v10
+; RV64V-NEXT: vxor.vv v14, v14, v15
+; RV64V-NEXT: vmul.vv v15, v8, v9
+; RV64V-NEXT: vmul.vv v20, v16, v9
+; RV64V-NEXT: vxor.vv v18, v19, v18
+; RV64V-NEXT: vmul.vv v19, v8, v12
+; RV64V-NEXT: vxor.vv v14, v14, v15
+; RV64V-NEXT: vxor.vv v15, v18, v20
+; RV64V-NEXT: vand.vx v14, v14, a1
+; RV64V-NEXT: vxor.vv v15, v15, v19
+; RV64V-NEXT: vmul.vv v18, v11, v12
+; RV64V-NEXT: vmul.vv v19, v13, v9
+; RV64V-NEXT: vand.vx v15, v15, a0
+; RV64V-NEXT: vmul.vv v20, v16, v10
+; RV64V-NEXT: vor.vv v14, v15, v14
+; RV64V-NEXT: vxor.vv v15, v19, v18
+; RV64V-NEXT: vmul.vv v9, v11, v9
+; RV64V-NEXT: vmul.vv v11, v13, v17
+; RV64V-NEXT: vxor.vv v13, v15, v20
+; RV64V-NEXT: vmul.vv v15, v8, v17
+; RV64V-NEXT: vmul.vv v12, v16, v12
+; RV64V-NEXT: vxor.vv v9, v11, v9
+; RV64V-NEXT: vmul.vv v8, v8, v10
+; RV64V-NEXT: vxor.vv v10, v13, v15
+; RV64V-NEXT: vxor.vv v9, v9, v12
+; RV64V-NEXT: vand.vx v10, v10, a2
+; RV64V-NEXT: vxor.vv v8, v9, v8
+; RV64V-NEXT: vor.vv v9, v14, v10
+; RV64V-NEXT: vand.vx v8, v8, a3
+; RV64V-NEXT: vor.vv v8, v9, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v2i64:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32ZVBC64-NEXT: vclmul.vv v8, v8, v9
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v2i64:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64ZVBC64-NEXT: vclmul.vv v8, v8, v9
+; RV64ZVBC64-NEXT: ret
;
-; RV64-LABEL: clmul_v2i64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 69905
-; RV64-NEXT: addi a0, a0, 273
-; RV64-NEXT: lui a1, 139810
-; RV64-NEXT: slli a2, a0, 32
-; RV64-NEXT: addi a1, a1, 546
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: slli a2, a1, 32
-; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v10, v9, a0
-; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: vand.vx v11, v8, a1
-; RV64-NEXT: vand.vx v12, v9, a1
-; RV64-NEXT: vand.vx v13, v8, a0
-; RV64-NEXT: vmul.vv v14, v11, v10
-; RV64-NEXT: vmul.vv v15, v13, v12
-; RV64-NEXT: lui a2, 279620
-; RV64-NEXT: lui a3, %hi(.LCPI6_0)
-; RV64-NEXT: addi a2, a2, 1092
-; RV64-NEXT: ld a3, %lo(.LCPI6_0)(a3)
-; RV64-NEXT: slli a4, a2, 32
-; RV64-NEXT: add a2, a2, a4
-; RV64-NEXT: vand.vx v16, v8, a2
-; RV64-NEXT: vand.vx v17, v9, a3
-; RV64-NEXT: vxor.vv v14, v15, v14
-; RV64-NEXT: vmul.vv v15, v16, v17
-; RV64-NEXT: vand.vx v8, v8, a3
-; RV64-NEXT: vand.vx v9, v9, a2
-; RV64-NEXT: vmul.vv v18, v11, v17
-; RV64-NEXT: vmul.vv v19, v13, v10
-; RV64-NEXT: vxor.vv v14, v14, v15
-; RV64-NEXT: vmul.vv v15, v8, v9
-; RV64-NEXT: vmul.vv v20, v16, v9
-; RV64-NEXT: vxor.vv v18, v19, v18
-; RV64-NEXT: vmul.vv v19, v8, v12
-; RV64-NEXT: vxor.vv v14, v14, v15
-; RV64-NEXT: vxor.vv v15, v18, v20
-; RV64-NEXT: vand.vx v14, v14, a1
-; RV64-NEXT: vxor.vv v15, v15, v19
-; RV64-NEXT: vmul.vv v18, v11, v12
-; RV64-NEXT: vmul.vv v19, v13, v9
-; RV64-NEXT: vand.vx v15, v15, a0
-; RV64-NEXT: vmul.vv v20, v16, v10
-; RV64-NEXT: vor.vv v14, v15, v14
-; RV64-NEXT: vxor.vv v15, v19, v18
-; RV64-NEXT: vmul.vv v9, v11, v9
-; RV64-NEXT: vmul.vv v11, v13, v17
-; RV64-NEXT: vxor.vv v13, v15, v20
-; RV64-NEXT: vmul.vv v15, v8, v17
-; RV64-NEXT: vmul.vv v12, v16, v12
-; RV64-NEXT: vxor.vv v9, v11, v9
-; RV64-NEXT: vmul.vv v8, v8, v10
-; RV64-NEXT: vxor.vv v10, v13, v15
-; RV64-NEXT: vxor.vv v9, v9, v12
-; RV64-NEXT: vand.vx v10, v10, a2
-; RV64-NEXT: vxor.vv v8, v9, v8
-; RV64-NEXT: vor.vv v9, v14, v10
-; RV64-NEXT: vand.vx v8, v8, a3
-; RV64-NEXT: vor.vv v8, v9, v8
-; RV64-NEXT: ret
+; RV32ZVBC32-LABEL: clmul_v2i64:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: li a0, 32
+; RV32ZVBC32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32ZVBC32-NEXT: vnsrl.wx v10, v8, a0
+; RV32ZVBC32-NEXT: vnsrl.wi v11, v9, 0
+; RV32ZVBC32-NEXT: vnsrl.wx v9, v9, a0
+; RV32ZVBC32-NEXT: vnsrl.wi v8, v8, 0
+; RV32ZVBC32-NEXT: vclmul.vv v10, v10, v11
+; RV32ZVBC32-NEXT: vclmul.vv v9, v8, v9
+; RV32ZVBC32-NEXT: vxor.vv v9, v9, v10
+; RV32ZVBC32-NEXT: vclmulh.vv v10, v8, v11
+; RV32ZVBC32-NEXT: vxor.vv v9, v10, v9
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32ZVBC32-NEXT: vzext.vf2 v10, v9
+; RV32ZVBC32-NEXT: vsll.vx v9, v10, a0
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v11
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32ZVBC32-NEXT: vzext.vf2 v10, v8
+; RV32ZVBC32-NEXT: vor.vv v8, v10, v9
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v2i64:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: li a0, 32
+; RV64ZVBC32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64ZVBC32-NEXT: vnsrl.wx v10, v8, a0
+; RV64ZVBC32-NEXT: vnsrl.wi v11, v9, 0
+; RV64ZVBC32-NEXT: vnsrl.wx v9, v9, a0
+; RV64ZVBC32-NEXT: vnsrl.wi v8, v8, 0
+; RV64ZVBC32-NEXT: vclmul.vv v10, v10, v11
+; RV64ZVBC32-NEXT: vclmul.vv v9, v8, v9
+; RV64ZVBC32-NEXT: vxor.vv v9, v9, v10
+; RV64ZVBC32-NEXT: vclmulh.vv v10, v8, v11
+; RV64ZVBC32-NEXT: vxor.vv v9, v10, v9
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64ZVBC32-NEXT: vzext.vf2 v10, v9
+; RV64ZVBC32-NEXT: vsll.vx v9, v10, a0
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v11
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64ZVBC32-NEXT: vzext.vf2 v10, v8
+; RV64ZVBC32-NEXT: vor.vv v8, v10, v9
+; RV64ZVBC32-NEXT: ret
%a = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %a
}
define <4 x i64> @clmul_v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
-; RV32-LABEL: clmul_v4i64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 69905
-; RV32-NEXT: addi a0, a0, 273
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v22, a0
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vand.vv v12, v10, v22
-; RV32-NEXT: lui a0, 139810
-; RV32-NEXT: addi a0, a0, 546
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v30, a0
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vand.vv v16, v8, v30
-; RV32-NEXT: vand.vv v14, v10, v30
-; RV32-NEXT: vand.vv v20, v8, v22
-; RV32-NEXT: vmul.vv v18, v20, v14
-; RV32-NEXT: vmul.vv v24, v16, v12
-; RV32-NEXT: vxor.vi v18, v18, 0
-; RV32-NEXT: vxor.vv v6, v18, v24
-; RV32-NEXT: lui a0, 559241
-; RV32-NEXT: addi a0, a0, -1912
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v18, a0
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vand.vv v24, v10, v18
-; RV32-NEXT: lui a0, 279620
-; RV32-NEXT: addi a0, a0, 1092
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v28, a0
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vand.vv v26, v8, v28
-; RV32-NEXT: vand.vv v10, v10, v28
-; RV32-NEXT: vmul.vv v4, v26, v24
-; RV32-NEXT: vand.vv v8, v8, v18
-; RV32-NEXT: vmul.vv v2, v8, v10
-; RV32-NEXT: vxor.vv v6, v6, v4
-; RV32-NEXT: vxor.vv v6, v6, v2
-; RV32-NEXT: vand.vv v30, v6, v30
-; RV32-NEXT: vmul.vv v6, v20, v12
-; RV32-NEXT: vmul.vv v4, v16, v24
-; RV32-NEXT: vxor.vi v6, v6, 0
-; RV32-NEXT: vxor.vv v6, v6, v4
-; RV32-NEXT: vmul.vv v4, v26, v10
-; RV32-NEXT: vmul.vv v2, v8, v14
-; RV32-NEXT: vxor.vv v6, v6, v4
-; RV32-NEXT: vxor.vv v6, v6, v2
-; RV32-NEXT: vand.vv v22, v6, v22
-; RV32-NEXT: vor.vi v22, v22, 0
-; RV32-NEXT: vor.vv v22, v22, v30
-; RV32-NEXT: vmul.vv v30, v20, v10
-; RV32-NEXT: vmul.vv v6, v16, v14
-; RV32-NEXT: vxor.vi v30, v30, 0
-; RV32-NEXT: vxor.vv v30, v30, v6
-; RV32-NEXT: vmul.vv v6, v26, v12
-; RV32-NEXT: vmul.vv v4, v8, v24
-; RV32-NEXT: vxor.vv v30, v30, v6
-; RV32-NEXT: vxor.vv v30, v30, v4
-; RV32-NEXT: vand.vv v28, v30, v28
-; RV32-NEXT: vor.vv v22, v22, v28
-; RV32-NEXT: vmul.vv v20, v20, v24
-; RV32-NEXT: vmul.vv v10, v16, v10
-; RV32-NEXT: vxor.vi v16, v20, 0
-; RV32-NEXT: vxor.vv v10, v16, v10
-; RV32-NEXT: vmul.vv v14, v26, v14
-; RV32-NEXT: vmul.vv v8, v8, v12
-; RV32-NEXT: vxor.vv v10, v10, v14
-; RV32-NEXT: vxor.vv v8, v10, v8
-; RV32-NEXT: vand.vv v8, v8, v18
-; RV32-NEXT: vor.vv v8, v22, v8
-; RV32-NEXT: ret
+; RV32V-LABEL: clmul_v4i64:
+; RV32V: # %bb.0:
+; RV32V-NEXT: lui a0, 69905
+; RV32V-NEXT: addi a0, a0, 273
+; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32V-NEXT: vmv.v.x v22, a0
+; RV32V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32V-NEXT: vand.vv v12, v10, v22
+; RV32V-NEXT: lui a0, 139810
+; RV32V-NEXT: addi a0, a0, 546
+; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32V-NEXT: vmv.v.x v30, a0
+; RV32V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32V-NEXT: vand.vv v16, v8, v30
+; RV32V-NEXT: vand.vv v14, v10, v30
+; RV32V-NEXT: vand.vv v20, v8, v22
+; RV32V-NEXT: vmul.vv v18, v20, v14
+; RV32V-NEXT: vmul.vv v24, v16, v12
+; RV32V-NEXT: vxor.vi v18, v18, 0
+; RV32V-NEXT: vxor.vv v6, v18, v24
+; RV32V-NEXT: lui a0, 559241
+; RV32V-NEXT: addi a0, a0, -1912
+; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32V-NEXT: vmv.v.x v18, a0
+; RV32V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32V-NEXT: vand.vv v24, v10, v18
+; RV32V-NEXT: lui a0, 279620
+; RV32V-NEXT: addi a0, a0, 1092
+; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32V-NEXT: vmv.v.x v28, a0
+; RV32V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32V-NEXT: vand.vv v26, v8, v28
+; RV32V-NEXT: vand.vv v10, v10, v28
+; RV32V-NEXT: vmul.vv v4, v26, v24
+; RV32V-NEXT: vand.vv v8, v8, v18
+; RV32V-NEXT: vmul.vv v2, v8, v10
+; RV32V-NEXT: vxor.vv v6, v6, v4
+; RV32V-NEXT: vxor.vv v6, v6, v2
+; RV32V-NEXT: vand.vv v30, v6, v30
+; RV32V-NEXT: vmul.vv v6, v20, v12
+; RV32V-NEXT: vmul.vv v4, v16, v24
+; RV32V-NEXT: vxor.vi v6, v6, 0
+; RV32V-NEXT: vxor.vv v6, v6, v4
+; RV32V-NEXT: vmul.vv v4, v26, v10
+; RV32V-NEXT: vmul.vv v2, v8, v14
+; RV32V-NEXT: vxor.vv v6, v6, v4
+; RV32V-NEXT: vxor.vv v6, v6, v2
+; RV32V-NEXT: vand.vv v22, v6, v22
+; RV32V-NEXT: vor.vi v22, v22, 0
+; RV32V-NEXT: vor.vv v22, v22, v30
+; RV32V-NEXT: vmul.vv v30, v20, v10
+; RV32V-NEXT: vmul.vv v6, v16, v14
+; RV32V-NEXT: vxor.vi v30, v30, 0
+; RV32V-NEXT: vxor.vv v30, v30, v6
+; RV32V-NEXT: vmul.vv v6, v26, v12
+; RV32V-NEXT: vmul.vv v4, v8, v24
+; RV32V-NEXT: vxor.vv v30, v30, v6
+; RV32V-NEXT: vxor.vv v30, v30, v4
+; RV32V-NEXT: vand.vv v28, v30, v28
+; RV32V-NEXT: vor.vv v22, v22, v28
+; RV32V-NEXT: vmul.vv v20, v20, v24
+; RV32V-NEXT: vmul.vv v10, v16, v10
+; RV32V-NEXT: vxor.vi v16, v20, 0
+; RV32V-NEXT: vxor.vv v10, v16, v10
+; RV32V-NEXT: vmul.vv v14, v26, v14
+; RV32V-NEXT: vmul.vv v8, v8, v12
+; RV32V-NEXT: vxor.vv v10, v10, v14
+; RV32V-NEXT: vxor.vv v8, v10, v8
+; RV32V-NEXT: vand.vv v8, v8, v18
+; RV32V-NEXT: vor.vv v8, v22, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v4i64:
+; RV64V: # %bb.0:
+; RV64V-NEXT: lui a0, 69905
+; RV64V-NEXT: addi a0, a0, 273
+; RV64V-NEXT: slli a1, a0, 32
+; RV64V-NEXT: add a0, a0, a1
+; RV64V-NEXT: lui a1, 139810
+; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64V-NEXT: vand.vx v12, v10, a0
+; RV64V-NEXT: addi a1, a1, 546
+; RV64V-NEXT: slli a2, a1, 32
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: vand.vx v16, v8, a1
+; RV64V-NEXT: vand.vx v14, v10, a1
+; RV64V-NEXT: vand.vx v18, v8, a0
+; RV64V-NEXT: vmul.vv v20, v16, v12
+; RV64V-NEXT: vmul.vv v22, v18, v14
+; RV64V-NEXT: lui a2, %hi(.LCPI7_0)
+; RV64V-NEXT: vxor.vv v24, v22, v20
+; RV64V-NEXT: ld a2, %lo(.LCPI7_0)(a2)
+; RV64V-NEXT: vand.vx v20, v10, a2
+; RV64V-NEXT: lui a3, 279620
+; RV64V-NEXT: addi a3, a3, 1092
+; RV64V-NEXT: slli a4, a3, 32
+; RV64V-NEXT: add a3, a3, a4
+; RV64V-NEXT: vand.vx v22, v8, a3
+; RV64V-NEXT: vand.vx v8, v8, a2
+; RV64V-NEXT: vmul.vv v26, v22, v20
+; RV64V-NEXT: vand.vx v10, v10, a3
+; RV64V-NEXT: vmul.vv v28, v8, v10
+; RV64V-NEXT: vxor.vv v24, v24, v26
+; RV64V-NEXT: vxor.vv v24, v24, v28
+; RV64V-NEXT: vmul.vv v26, v16, v20
+; RV64V-NEXT: vmul.vv v28, v18, v12
+; RV64V-NEXT: vand.vx v24, v24, a1
+; RV64V-NEXT: vxor.vv v26, v28, v26
+; RV64V-NEXT: vmul.vv v28, v22, v10
+; RV64V-NEXT: vmul.vv v30, v8, v14
+; RV64V-NEXT: vxor.vv v26, v26, v28
+; RV64V-NEXT: vxor.vv v26, v26, v30
+; RV64V-NEXT: vand.vx v26, v26, a0
+; RV64V-NEXT: vmul.vv v28, v16, v14
+; RV64V-NEXT: vmul.vv v30, v18, v10
+; RV64V-NEXT: vor.vv v24, v26, v24
+; RV64V-NEXT: vxor.vv v26, v30, v28
+; RV64V-NEXT: vmul.vv v28, v22, v12
+; RV64V-NEXT: vmul.vv v30, v8, v20
+; RV64V-NEXT: vxor.vv v26, v26, v28
+; RV64V-NEXT: vxor.vv v26, v26, v30
+; RV64V-NEXT: vand.vx v26, v26, a3
+; RV64V-NEXT: vmul.vv v10, v16, v10
+; RV64V-NEXT: vmul.vv v16, v18, v20
+; RV64V-NEXT: vor.vv v18, v24, v26
+; RV64V-NEXT: vxor.vv v10, v16, v10
+; RV64V-NEXT: vmul.vv v14, v22, v14
+; RV64V-NEXT: vmul.vv v8, v8, v12
+; RV64V-NEXT: vxor.vv v10, v10, v14
+; RV64V-NEXT: vxor.vv v8, v10, v8
+; RV64V-NEXT: vand.vx v8, v8, a2
+; RV64V-NEXT: vor.vv v8, v18, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v4i64:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32ZVBC64-NEXT: vclmul.vv v8, v8, v10
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v4i64:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64ZVBC64-NEXT: vclmul.vv v8, v8, v10
+; RV64ZVBC64-NEXT: ret
;
-; RV64-LABEL: clmul_v4i64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 69905
-; RV64-NEXT: addi a0, a0, 273
-; RV64-NEXT: slli a1, a0, 32
-; RV64-NEXT: add a0, a0, a1
-; RV64-NEXT: lui a1, 139810
-; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v12, v10, a0
-; RV64-NEXT: addi a1, a1, 546
-; RV64-NEXT: slli a2, a1, 32
-; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: vand.vx v16, v8, a1
-; RV64-NEXT: vand.vx v14, v10, a1
-; RV64-NEXT: vand.vx v18, v8, a0
-; RV64-NEXT: vmul.vv v20, v16, v12
-; RV64-NEXT: vmul.vv v22, v18, v14
-; RV64-NEXT: lui a2, %hi(.LCPI7_0)
-; RV64-NEXT: vxor.vv v24, v22, v20
-; RV64-NEXT: ld a2, %lo(.LCPI7_0)(a2)
-; RV64-NEXT: vand.vx v20, v10, a2
-; RV64-NEXT: lui a3, 279620
-; RV64-NEXT: addi a3, a3, 1092
-; RV64-NEXT: slli a4, a3, 32
-; RV64-NEXT: add a3, a3, a4
-; RV64-NEXT: vand.vx v22, v8, a3
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vmul.vv v26, v22, v20
-; RV64-NEXT: vand.vx v10, v10, a3
-; RV64-NEXT: vmul.vv v28, v8, v10
-; RV64-NEXT: vxor.vv v24, v24, v26
-; RV64-NEXT: vxor.vv v24, v24, v28
-; RV64-NEXT: vmul.vv v26, v16, v20
-; RV64-NEXT: vmul.vv v28, v18, v12
-; RV64-NEXT: vand.vx v24, v24, a1
-; RV64-NEXT: vxor.vv v26, v28, v26
-; RV64-NEXT: vmul.vv v28, v22, v10
-; RV64-NEXT: vmul.vv v30, v8, v14
-; RV64-NEXT: vxor.vv v26, v26, v28
-; RV64-NEXT: vxor.vv v26, v26, v30
-; RV64-NEXT: vand.vx v26, v26, a0
-; RV64-NEXT: vmul.vv v28, v16, v14
-; RV64-NEXT: vmul.vv v30, v18, v10
-; RV64-NEXT: vor.vv v24, v26, v24
-; RV64-NEXT: vxor.vv v26, v30, v28
-; RV64-NEXT: vmul.vv v28, v22, v12
-; RV64-NEXT: vmul.vv v30, v8, v20
-; RV64-NEXT: vxor.vv v26, v26, v28
-; RV64-NEXT: vxor.vv v26, v26, v30
-; RV64-NEXT: vand.vx v26, v26, a3
-; RV64-NEXT: vmul.vv v10, v16, v10
-; RV64-NEXT: vmul.vv v16, v18, v20
-; RV64-NEXT: vor.vv v18, v24, v26
-; RV64-NEXT: vxor.vv v10, v16, v10
-; RV64-NEXT: vmul.vv v14, v22, v14
-; RV64-NEXT: vmul.vv v8, v8, v12
-; RV64-NEXT: vxor.vv v10, v10, v14
-; RV64-NEXT: vxor.vv v8, v10, v8
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vor.vv v8, v18, v8
-; RV64-NEXT: ret
+; RV32ZVBC32-LABEL: clmul_v4i64:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: li a0, 32
+; RV32ZVBC32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32ZVBC32-NEXT: vnsrl.wx v12, v8, a0
+; RV32ZVBC32-NEXT: vnsrl.wi v13, v10, 0
+; RV32ZVBC32-NEXT: vnsrl.wx v14, v10, a0
+; RV32ZVBC32-NEXT: vnsrl.wi v10, v8, 0
+; RV32ZVBC32-NEXT: vclmul.vv v8, v12, v13
+; RV32ZVBC32-NEXT: vclmul.vv v9, v10, v14
+; RV32ZVBC32-NEXT: vxor.vv v8, v9, v8
+; RV32ZVBC32-NEXT: vclmulh.vv v9, v10, v13
+; RV32ZVBC32-NEXT: vxor.vv v11, v9, v8
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32ZVBC32-NEXT: vzext.vf2 v8, v11
+; RV32ZVBC32-NEXT: vsll.vx v8, v8, a0
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v12, v10, v13
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32ZVBC32-NEXT: vzext.vf2 v10, v12
+; RV32ZVBC32-NEXT: vor.vv v8, v10, v8
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v4i64:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: li a0, 32
+; RV64ZVBC32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64ZVBC32-NEXT: vnsrl.wx v12, v8, a0
+; RV64ZVBC32-NEXT: vnsrl.wi v13, v10, 0
+; RV64ZVBC32-NEXT: vnsrl.wx v14, v10, a0
+; RV64ZVBC32-NEXT: vnsrl.wi v10, v8, 0
+; RV64ZVBC32-NEXT: vclmul.vv v8, v12, v13
+; RV64ZVBC32-NEXT: vclmul.vv v9, v10, v14
+; RV64ZVBC32-NEXT: vxor.vv v8, v9, v8
+; RV64ZVBC32-NEXT: vclmulh.vv v9, v10, v13
+; RV64ZVBC32-NEXT: vxor.vv v11, v9, v8
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64ZVBC32-NEXT: vzext.vf2 v8, v11
+; RV64ZVBC32-NEXT: vsll.vx v8, v8, a0
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v12, v10, v13
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64ZVBC32-NEXT: vzext.vf2 v10, v12
+; RV64ZVBC32-NEXT: vor.vv v8, v10, v8
+; RV64ZVBC32-NEXT: ret
%a = call <4 x i64> @llvm.clmul.v4i64(<4 x i64> %x, <4 x i64> %y)
ret <4 x i64> %a
}
define <8 x i64> @clmul_v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
-; RV32-LABEL: clmul_v8i64:
-; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 5
-; RV32-NEXT: sub sp, sp, a0
-; RV32-NEXT: lui a0, 69905
-; RV32-NEXT: addi a0, a0, 273
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v4, a0
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v4, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v28, v12, v4
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a1, a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v28, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: lui a0, 139810
-; RV32-NEXT: addi a0, a0, 546
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v20, a0
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v20
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vand.vv v16, v12, v20
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vand.vv v4, v8, v4
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs4r.v v4, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmul.vv v16, v4, v16
-; RV32-NEXT: vmul.vv v24, v24, v28
-; RV32-NEXT: vxor.vi v16, v16, 0
-; RV32-NEXT: vxor.vv v16, v16, v24
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: lui a0, 559241
-; RV32-NEXT: addi a0, a0, -1912
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v28, a0
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v28, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v24, v12, v28
-; RV32-NEXT: lui a0, 279620
-; RV32-NEXT: addi a0, a0, 1092
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a0
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v12, v12, v16
-; RV32-NEXT: vand.vv v16, v8, v16
-; RV32-NEXT: vand.vv v8, v8, v28
-; RV32-NEXT: vmul.vv v28, v16, v24
-; RV32-NEXT: vmul.vv v4, v8, v12
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v0, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vxor.vv v28, v0, v28
-; RV32-NEXT: vxor.vv v28, v28, v4
-; RV32-NEXT: vand.vv v20, v28, v20
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a1, a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl4r.v v0, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmul.vv v28, v0, v20
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmul.vv v4, v20, v24
-; RV32-NEXT: vxor.vi v28, v28, 0
-; RV32-NEXT: vxor.vv v28, v28, v4
-; RV32-NEXT: vmul.vv v4, v16, v12
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmul.vv v20, v8, v20
-; RV32-NEXT: vxor.vv v28, v28, v4
-; RV32-NEXT: vxor.vv v20, v28, v20
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vand.vv v20, v20, v28
-; RV32-NEXT: vor.vi v20, v20, 0
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vor.vv v20, v20, v28
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmul.vv v28, v0, v12
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmul.vv v4, v4, v20
-; RV32-NEXT: vxor.vi v28, v28, 0
-; RV32-NEXT: vxor.vv v28, v28, v4
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a1, a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmul.vv v4, v16, v20
-; RV32-NEXT: vmul.vv v20, v8, v24
-; RV32-NEXT: vxor.vv v28, v28, v4
-; RV32-NEXT: vxor.vv v20, v28, v20
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vand.vv v20, v20, v28
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vor.vv v20, v28, v20
-; RV32-NEXT: vmul.vv v24, v0, v24
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmul.vv v12, v28, v12
-; RV32-NEXT: vxor.vi v24, v24, 0
-; RV32-NEXT: vxor.vv v12, v24, v12
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmul.vv v16, v16, v24
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a1, a1, a0
-; RV32-NEXT: slli a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v24
-; RV32-NEXT: vxor.vv v12, v12, v16
-; RV32-NEXT: vxor.vv v8, v12, v8
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl4r.v v12, (a0) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v12
-; RV32-NEXT: vor.vv v8, v20, v8
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 5
-; RV32-NEXT: add sp, sp, a0
-; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: ret
+; RV32V-LABEL: clmul_v8i64:
+; RV32V: # %bb.0:
+; RV32V-NEXT: addi sp, sp, -16
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 5
+; RV32V-NEXT: sub sp, sp, a0
+; RV32V-NEXT: lui a0, 69905
+; RV32V-NEXT: addi a0, a0, 273
+; RV32V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32V-NEXT: vmv.v.x v4, a0
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v4, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32V-NEXT: vand.vv v28, v12, v4
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a1, a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v28, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: lui a0, 139810
+; RV32V-NEXT: addi a0, a0, 546
+; RV32V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32V-NEXT: vmv.v.x v20, a0
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32V-NEXT: vand.vv v24, v8, v20
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vand.vv v16, v12, v20
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 3
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vand.vv v4, v8, v4
+; RV32V-NEXT: addi a0, sp, 16
+; RV32V-NEXT: vs4r.v v4, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vmul.vv v16, v4, v16
+; RV32V-NEXT: vmul.vv v24, v24, v28
+; RV32V-NEXT: vxor.vi v16, v16, 0
+; RV32V-NEXT: vxor.vv v16, v16, v24
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: lui a0, 559241
+; RV32V-NEXT: addi a0, a0, -1912
+; RV32V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32V-NEXT: vmv.v.x v28, a0
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 4
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v28, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32V-NEXT: vand.vv v24, v12, v28
+; RV32V-NEXT: lui a0, 279620
+; RV32V-NEXT: addi a0, a0, 1092
+; RV32V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32V-NEXT: vmv.v.x v16, a0
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 3
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32V-NEXT: vand.vv v12, v12, v16
+; RV32V-NEXT: vand.vv v16, v8, v16
+; RV32V-NEXT: vand.vv v8, v8, v28
+; RV32V-NEXT: vmul.vv v28, v16, v24
+; RV32V-NEXT: vmul.vv v4, v8, v12
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v0, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vxor.vv v28, v0, v28
+; RV32V-NEXT: vxor.vv v28, v28, v4
+; RV32V-NEXT: vand.vv v20, v28, v20
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a1, a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: addi a0, sp, 16
+; RV32V-NEXT: vl4r.v v0, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v28, v0, v20
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v4, v20, v24
+; RV32V-NEXT: vxor.vi v28, v28, 0
+; RV32V-NEXT: vxor.vv v28, v28, v4
+; RV32V-NEXT: vmul.vv v4, v16, v12
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 3
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v20, v8, v20
+; RV32V-NEXT: vxor.vv v28, v28, v4
+; RV32V-NEXT: vxor.vv v20, v28, v20
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vand.vv v20, v20, v28
+; RV32V-NEXT: vor.vi v20, v20, 0
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vor.vv v20, v20, v28
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
+; RV32V-NEXT: vmul.vv v28, v0, v12
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 3
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v4, v4, v20
+; RV32V-NEXT: vxor.vi v28, v28, 0
+; RV32V-NEXT: vxor.vv v28, v28, v4
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a1, a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v4, v16, v20
+; RV32V-NEXT: vmul.vv v20, v8, v24
+; RV32V-NEXT: vxor.vv v28, v28, v4
+; RV32V-NEXT: vxor.vv v20, v28, v20
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 3
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vand.vv v20, v20, v28
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vor.vv v20, v28, v20
+; RV32V-NEXT: vmul.vv v24, v0, v24
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v12, v28, v12
+; RV32V-NEXT: vxor.vi v24, v24, 0
+; RV32V-NEXT: vxor.vv v12, v24, v12
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 3
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v16, v16, v24
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 2
+; RV32V-NEXT: mv a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a1, a1, a0
+; RV32V-NEXT: slli a0, a0, 1
+; RV32V-NEXT: add a0, a0, a1
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vmul.vv v8, v8, v24
+; RV32V-NEXT: vxor.vv v12, v12, v16
+; RV32V-NEXT: vxor.vv v8, v12, v8
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 4
+; RV32V-NEXT: add a0, sp, a0
+; RV32V-NEXT: addi a0, a0, 16
+; RV32V-NEXT: vl4r.v v12, (a0) # vscale x 32-byte Folded Reload
+; RV32V-NEXT: vand.vv v8, v8, v12
+; RV32V-NEXT: vor.vv v8, v20, v8
+; RV32V-NEXT: csrr a0, vlenb
+; RV32V-NEXT: slli a0, a0, 5
+; RV32V-NEXT: add sp, sp, a0
+; RV32V-NEXT: addi sp, sp, 16
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v8i64:
+; RV64V: # %bb.0:
+; RV64V-NEXT: addi sp, sp, -16
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 5
+; RV64V-NEXT: sub sp, sp, a0
+; RV64V-NEXT: lui a0, 69905
+; RV64V-NEXT: addi a0, a0, 273
+; RV64V-NEXT: slli a1, a0, 32
+; RV64V-NEXT: add a1, a0, a1
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64V-NEXT: vand.vx v16, v12, a1
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 2
+; RV64V-NEXT: mv a2, a0
+; RV64V-NEXT: slli a0, a0, 1
+; RV64V-NEXT: add a2, a2, a0
+; RV64V-NEXT: slli a0, a0, 1
+; RV64V-NEXT: add a0, a0, a2
+; RV64V-NEXT: add a0, sp, a0
+; RV64V-NEXT: addi a0, a0, 16
+; RV64V-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: lui a0, 139810
+; RV64V-NEXT: addi a0, a0, 546
+; RV64V-NEXT: slli a3, a0, 32
+; RV64V-NEXT: add a3, a0, a3
+; RV64V-NEXT: vand.vx v24, v8, a3
+; RV64V-NEXT: vand.vx v20, v12, a3
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 3
+; RV64V-NEXT: mv a2, a0
+; RV64V-NEXT: slli a0, a0, 1
+; RV64V-NEXT: add a0, a0, a2
+; RV64V-NEXT: add a0, sp, a0
+; RV64V-NEXT: addi a0, a0, 16
+; RV64V-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vand.vx v28, v8, a1
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 3
+; RV64V-NEXT: add a0, sp, a0
+; RV64V-NEXT: addi a0, a0, 16
+; RV64V-NEXT: vs4r.v v28, (a0) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: lui a0, %hi(.LCPI8_0)
+; RV64V-NEXT: ld a0, %lo(.LCPI8_0)(a0)
+; RV64V-NEXT: vand.vx v4, v12, a0
+; RV64V-NEXT: vmul.vv v16, v24, v16
+; RV64V-NEXT: csrr a2, vlenb
+; RV64V-NEXT: slli a2, a2, 2
+; RV64V-NEXT: mv a4, a2
+; RV64V-NEXT: slli a2, a2, 2
+; RV64V-NEXT: add a2, a2, a4
+; RV64V-NEXT: add a2, sp, a2
+; RV64V-NEXT: addi a2, a2, 16
+; RV64V-NEXT: vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a2, vlenb
+; RV64V-NEXT: slli a2, a2, 4
+; RV64V-NEXT: add a2, sp, a2
+; RV64V-NEXT: addi a2, a2, 16
+; RV64V-NEXT: vs4r.v v24, (a2) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: lui a2, 279620
+; RV64V-NEXT: vmul.vv v16, v28, v20
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: addi a2, a2, 1092
+; RV64V-NEXT: slli a4, a2, 32
+; RV64V-NEXT: add a2, a2, a4
+; RV64V-NEXT: vand.vx v0, v8, a2
+; RV64V-NEXT: vmul.vv v16, v0, v4
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v20, v28, v20
+; RV64V-NEXT: vxor.vv v16, v20, v16
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vand.vx v8, v8, a0
+; RV64V-NEXT: vand.vx v12, v12, a2
+; RV64V-NEXT: vmul.vv v16, v8, v12
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vmul.vv v16, v24, v4
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a5, a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 3
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v16, v28, v16
+; RV64V-NEXT: addi a4, sp, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v20, v20, v16
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: addi a4, sp, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v16, v20, v16
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vmul.vv v16, v0, v12
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 3
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v16, v8, v16
+; RV64V-NEXT: addi a4, sp, 16
+; RV64V-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 1
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v20, v20, v16
+; RV64V-NEXT: addi a4, sp, 16
+; RV64V-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v16, v20, v16
+; RV64V-NEXT: csrr a4, vlenb
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: mv a5, a4
+; RV64V-NEXT: slli a4, a4, 2
+; RV64V-NEXT: add a4, a4, a5
+; RV64V-NEXT: add a4, sp, a4
+; RV64V-NEXT: addi a4, a4, 16
+; RV64V-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vand.vx v20, v20, a3
+; RV64V-NEXT: csrr a3, vlenb
+; RV64V-NEXT: slli a3, a3, 2
+; RV64V-NEXT: mv a4, a3
+; RV64V-NEXT: slli a3, a3, 2
+; RV64V-NEXT: add a3, a3, a4
+; RV64V-NEXT: add a3, sp, a3
+; RV64V-NEXT: addi a3, a3, 16
+; RV64V-NEXT: vs4r.v v20, (a3) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vand.vx v16, v16, a1
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 3
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v16, v24, v16
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: vmul.vv v16, v28, v12
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vor.vv v24, v20, v24
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vxor.vv v24, v16, v20
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a3, a3, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a3
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v20, v0, v16
+; RV64V-NEXT: vmul.vv v16, v8, v4
+; RV64V-NEXT: vxor.vv v20, v24, v20
+; RV64V-NEXT: vxor.vv v16, v20, v16
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 4
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v12, v20, v12
+; RV64V-NEXT: vmul.vv v20, v28, v4
+; RV64V-NEXT: vand.vx v16, v16, a2
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a2, a1
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vor.vv v16, v24, v16
+; RV64V-NEXT: vxor.vv v12, v20, v12
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 3
+; RV64V-NEXT: mv a2, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v20, v0, v20
+; RV64V-NEXT: csrr a1, vlenb
+; RV64V-NEXT: slli a1, a1, 2
+; RV64V-NEXT: mv a2, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a2, a2, a1
+; RV64V-NEXT: slli a1, a1, 1
+; RV64V-NEXT: add a1, a1, a2
+; RV64V-NEXT: add a1, sp, a1
+; RV64V-NEXT: addi a1, a1, 16
+; RV64V-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV64V-NEXT: vmul.vv v8, v8, v24
+; RV64V-NEXT: vxor.vv v12, v12, v20
+; RV64V-NEXT: vxor.vv v8, v12, v8
+; RV64V-NEXT: vand.vx v8, v8, a0
+; RV64V-NEXT: vor.vv v8, v16, v8
+; RV64V-NEXT: csrr a0, vlenb
+; RV64V-NEXT: slli a0, a0, 5
+; RV64V-NEXT: add sp, sp, a0
+; RV64V-NEXT: addi sp, sp, 16
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v8i64:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32ZVBC64-NEXT: vclmul.vv v8, v8, v12
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v8i64:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64ZVBC64-NEXT: vclmul.vv v8, v8, v12
+; RV64ZVBC64-NEXT: ret
;
-; RV64-LABEL: clmul_v8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: addi sp, sp, -16
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 5
-; RV64-NEXT: sub sp, sp, a0
-; RV64-NEXT: lui a0, 69905
-; RV64-NEXT: addi a0, a0, 273
-; RV64-NEXT: slli a1, a0, 32
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v16, v12, a1
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 2
-; RV64-NEXT: mv a2, a0
-; RV64-NEXT: slli a0, a0, 1
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: slli a0, a0, 1
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
-; RV64-NEXT: lui a0, 139810
-; RV64-NEXT: addi a0, a0, 546
-; RV64-NEXT: slli a3, a0, 32
-; RV64-NEXT: add a3, a0, a3
-; RV64-NEXT: vand.vx v24, v8, a3
-; RV64-NEXT: vand.vx v20, v12, a3
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: mv a2, a0
-; RV64-NEXT: slli a0, a0, 1
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vand.vx v28, v8, a1
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs4r.v v28, (a0) # vscale x 32-byte Folded Spill
-; RV64-NEXT: lui a0, %hi(.LCPI8_0)
-; RV64-NEXT: ld a0, %lo(.LCPI8_0)(a0)
-; RV64-NEXT: vand.vx v4, v12, a0
-; RV64-NEXT: vmul.vv v16, v24, v16
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a2, a2, 2
-; RV64-NEXT: mv a4, a2
-; RV64-NEXT: slli a2, a2, 2
-; RV64-NEXT: add a2, a2, a4
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a2, a2, 4
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs4r.v v24, (a2) # vscale x 32-byte Folded Spill
-; RV64-NEXT: lui a2, 279620
-; RV64-NEXT: vmul.vv v16, v28, v20
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: addi a2, a2, 1092
-; RV64-NEXT: slli a4, a2, 32
-; RV64-NEXT: add a2, a2, a4
-; RV64-NEXT: vand.vx v0, v8, a2
-; RV64-NEXT: vmul.vv v16, v0, v4
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vxor.vv v20, v28, v20
-; RV64-NEXT: vxor.vv v16, v20, v16
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vand.vx v12, v12, a2
-; RV64-NEXT: vmul.vv v16, v8, v12
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vmul.vv v16, v24, v4
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a5, a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 3
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmul.vv v16, v28, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vxor.vv v20, v20, v16
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vxor.vv v16, v20, v16
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vmul.vv v16, v0, v12
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 3
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmul.vv v16, v8, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 1
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vxor.vv v20, v20, v16
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vxor.vv v16, v20, v16
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: mv a5, a4
-; RV64-NEXT: slli a4, a4, 2
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vand.vx v20, v20, a3
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: slli a3, a3, 2
-; RV64-NEXT: mv a4, a3
-; RV64-NEXT: slli a3, a3, 2
-; RV64-NEXT: add a3, a3, a4
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vs4r.v v20, (a3) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vand.vx v16, v16, a1
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: mv a3, a1
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, a1, a3
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: mv a3, a1
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, a1, a3
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmul.vv v16, v24, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vmul.vv v16, v28, v12
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: mv a3, a1
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: add a1, a1, a3
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: mv a3, a1
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, a1, a3
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vor.vv v24, v20, v24
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: mv a3, a1
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: add a1, a1, a3
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vxor.vv v24, v16, v20
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: mv a3, a1
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a3, a3, a1
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, a1, a3
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmul.vv v20, v0, v16
-; RV64-NEXT: vmul.vv v16, v8, v4
-; RV64-NEXT: vxor.vv v20, v24, v20
-; RV64-NEXT: vxor.vv v16, v20, v16
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 4
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmul.vv v12, v20, v12
-; RV64-NEXT: vmul.vv v20, v28, v4
-; RV64-NEXT: vand.vx v16, v16, a2
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: mv a2, a1
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v24, v16
-; RV64-NEXT: vxor.vv v12, v20, v12
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
-; RV64-NEXT: mv a2, a1
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmul.vv v20, v0, v20
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
-; RV64-NEXT: mv a2, a1
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a2, a2, a1
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmul.vv v8, v8, v24
-; RV64-NEXT: vxor.vv v12, v12, v20
-; RV64-NEXT: vxor.vv v8, v12, v8
-; RV64-NEXT: vand.vx v8, v8, a0
-; RV64-NEXT: vor.vv v8, v16, v8
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 5
-; RV64-NEXT: add sp, sp, a0
-; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: ret
+; RV32ZVBC32-LABEL: clmul_v8i64:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: li a0, 32
+; RV32ZVBC32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32ZVBC32-NEXT: vnsrl.wx v16, v8, a0
+; RV32ZVBC32-NEXT: vnsrl.wi v18, v12, 0
+; RV32ZVBC32-NEXT: vnsrl.wx v20, v12, a0
+; RV32ZVBC32-NEXT: vnsrl.wi v12, v8, 0
+; RV32ZVBC32-NEXT: vclmul.vv v8, v16, v18
+; RV32ZVBC32-NEXT: vclmul.vv v10, v12, v20
+; RV32ZVBC32-NEXT: vxor.vv v8, v10, v8
+; RV32ZVBC32-NEXT: vclmulh.vv v10, v12, v18
+; RV32ZVBC32-NEXT: vxor.vv v14, v10, v8
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32ZVBC32-NEXT: vzext.vf2 v8, v14
+; RV32ZVBC32-NEXT: vsll.vx v8, v8, a0
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v16, v12, v18
+; RV32ZVBC32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32ZVBC32-NEXT: vzext.vf2 v12, v16
+; RV32ZVBC32-NEXT: vor.vv v8, v12, v8
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v8i64:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: li a0, 32
+; RV64ZVBC32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVBC32-NEXT: vnsrl.wx v16, v8, a0
+; RV64ZVBC32-NEXT: vnsrl.wi v18, v12, 0
+; RV64ZVBC32-NEXT: vnsrl.wx v20, v12, a0
+; RV64ZVBC32-NEXT: vnsrl.wi v12, v8, 0
+; RV64ZVBC32-NEXT: vclmul.vv v8, v16, v18
+; RV64ZVBC32-NEXT: vclmul.vv v10, v12, v20
+; RV64ZVBC32-NEXT: vxor.vv v8, v10, v8
+; RV64ZVBC32-NEXT: vclmulh.vv v10, v12, v18
+; RV64ZVBC32-NEXT: vxor.vv v14, v10, v8
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64ZVBC32-NEXT: vzext.vf2 v8, v14
+; RV64ZVBC32-NEXT: vsll.vx v8, v8, a0
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v16, v12, v18
+; RV64ZVBC32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64ZVBC32-NEXT: vzext.vf2 v12, v16
+; RV64ZVBC32-NEXT: vor.vv v8, v12, v8
+; RV64ZVBC32-NEXT: ret
%a = call <8 x i64> @llvm.clmul.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %a
}
define <4 x i8> @clmul_v4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
-; CHECK-LABEL: clmul_v4i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 16
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vand.vi v10, v9, 2
-; CHECK-NEXT: vand.vi v11, v9, 1
-; CHECK-NEXT: vmul.vv v10, v8, v10
-; CHECK-NEXT: vmul.vv v11, v8, v11
-; CHECK-NEXT: vand.vi v12, v9, 4
-; CHECK-NEXT: vand.vi v13, v9, 8
-; CHECK-NEXT: vmul.vv v12, v8, v12
-; CHECK-NEXT: vxor.vv v10, v11, v10
-; CHECK-NEXT: vand.vx v11, v9, a0
-; CHECK-NEXT: vmul.vv v13, v8, v13
-; CHECK-NEXT: vxor.vv v10, v10, v12
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vmul.vv v11, v8, v11
-; CHECK-NEXT: vand.vx v12, v9, a0
-; CHECK-NEXT: li a0, 64
-; CHECK-NEXT: vxor.vv v10, v10, v13
-; CHECK-NEXT: vand.vx v13, v9, a0
-; CHECK-NEXT: vmul.vv v12, v8, v12
-; CHECK-NEXT: vxor.vv v10, v10, v11
-; CHECK-NEXT: vmul.vv v11, v8, v13
-; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: vand.vx v9, v9, a0
-; CHECK-NEXT: vxor.vv v10, v10, v12
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vxor.vv v9, v10, v11
-; CHECK-NEXT: vxor.vv v8, v9, v8
-; CHECK-NEXT: ret
+; RV32V-LABEL: clmul_v4i8:
+; RV32V: # %bb.0:
+; RV32V-NEXT: li a0, 16
+; RV32V-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; RV32V-NEXT: vand.vi v10, v9, 2
+; RV32V-NEXT: vand.vi v11, v9, 1
+; RV32V-NEXT: vmul.vv v10, v8, v10
+; RV32V-NEXT: vmul.vv v11, v8, v11
+; RV32V-NEXT: vand.vi v12, v9, 4
+; RV32V-NEXT: vand.vi v13, v9, 8
+; RV32V-NEXT: vmul.vv v12, v8, v12
+; RV32V-NEXT: vxor.vv v10, v11, v10
+; RV32V-NEXT: vand.vx v11, v9, a0
+; RV32V-NEXT: vmul.vv v13, v8, v13
+; RV32V-NEXT: vxor.vv v10, v10, v12
+; RV32V-NEXT: li a0, 32
+; RV32V-NEXT: vmul.vv v11, v8, v11
+; RV32V-NEXT: vand.vx v12, v9, a0
+; RV32V-NEXT: li a0, 64
+; RV32V-NEXT: vxor.vv v10, v10, v13
+; RV32V-NEXT: vand.vx v13, v9, a0
+; RV32V-NEXT: vmul.vv v12, v8, v12
+; RV32V-NEXT: vxor.vv v10, v10, v11
+; RV32V-NEXT: vmul.vv v11, v8, v13
+; RV32V-NEXT: li a0, 128
+; RV32V-NEXT: vand.vx v9, v9, a0
+; RV32V-NEXT: vxor.vv v10, v10, v12
+; RV32V-NEXT: vmul.vv v8, v8, v9
+; RV32V-NEXT: vxor.vv v9, v10, v11
+; RV32V-NEXT: vxor.vv v8, v9, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v4i8:
+; RV64V: # %bb.0:
+; RV64V-NEXT: li a0, 16
+; RV64V-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; RV64V-NEXT: vand.vi v10, v9, 2
+; RV64V-NEXT: vand.vi v11, v9, 1
+; RV64V-NEXT: vmul.vv v10, v8, v10
+; RV64V-NEXT: vmul.vv v11, v8, v11
+; RV64V-NEXT: vand.vi v12, v9, 4
+; RV64V-NEXT: vand.vi v13, v9, 8
+; RV64V-NEXT: vmul.vv v12, v8, v12
+; RV64V-NEXT: vxor.vv v10, v11, v10
+; RV64V-NEXT: vand.vx v11, v9, a0
+; RV64V-NEXT: vmul.vv v13, v8, v13
+; RV64V-NEXT: vxor.vv v10, v10, v12
+; RV64V-NEXT: li a0, 32
+; RV64V-NEXT: vmul.vv v11, v8, v11
+; RV64V-NEXT: vand.vx v12, v9, a0
+; RV64V-NEXT: li a0, 64
+; RV64V-NEXT: vxor.vv v10, v10, v13
+; RV64V-NEXT: vand.vx v13, v9, a0
+; RV64V-NEXT: vmul.vv v12, v8, v12
+; RV64V-NEXT: vxor.vv v10, v10, v11
+; RV64V-NEXT: vmul.vv v11, v8, v13
+; RV64V-NEXT: li a0, 128
+; RV64V-NEXT: vand.vx v9, v9, a0
+; RV64V-NEXT: vxor.vv v10, v10, v12
+; RV64V-NEXT: vmul.vv v8, v8, v9
+; RV64V-NEXT: vxor.vv v9, v10, v11
+; RV64V-NEXT: vxor.vv v8, v9, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v4i8:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf8 v10, v9
+; RV32ZVBC64-NEXT: vzext.vf8 v12, v8
+; RV32ZVBC64-NEXT: vclmul.vv v8, v12, v10
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v10, v8, 0
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v8, v10, 0
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v8, v8, 0
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v4i8:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64ZVBC64-NEXT: vzext.vf8 v10, v9
+; RV64ZVBC64-NEXT: vzext.vf8 v12, v8
+; RV64ZVBC64-NEXT: vclmul.vv v8, v12, v10
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v10, v8, 0
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v8, v10, 0
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v8, v8, 0
+; RV64ZVBC64-NEXT: ret
+;
+; RV32ZVBC32-LABEL: clmul_v4i8:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v4i8:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV64ZVBC32-NEXT: ret
%res = call <4 x i8> @llvm.clmul.v4i8(<4 x i8> %a, <4 x i8> %b)
ret <4 x i8> %res
}
define <4 x i16> @clmul_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind {
-; CHECK-LABEL: clmul_v4i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 16
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vand.vi v10, v9, 2
-; CHECK-NEXT: vand.vi v11, v9, 1
-; CHECK-NEXT: vand.vi v12, v9, 4
-; CHECK-NEXT: vmul.vv v10, v8, v10
-; CHECK-NEXT: vmul.vv v11, v8, v11
-; CHECK-NEXT: vand.vi v13, v9, 8
-; CHECK-NEXT: vmul.vv v12, v8, v12
-; CHECK-NEXT: vxor.vv v10, v11, v10
-; CHECK-NEXT: vmul.vv v11, v8, v13
-; CHECK-NEXT: vand.vx v13, v9, a0
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vxor.vv v10, v10, v12
-; CHECK-NEXT: vand.vx v12, v9, a0
-; CHECK-NEXT: vmul.vv v13, v8, v13
-; CHECK-NEXT: li a0, 64
-; CHECK-NEXT: vxor.vv v10, v10, v11
-; CHECK-NEXT: vand.vx v11, v9, a0
-; CHECK-NEXT: vmul.vv v12, v8, v12
-; CHECK-NEXT: vxor.vv v10, v10, v13
-; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: vmul.vv v11, v8, v11
-; CHECK-NEXT: vand.vx v13, v9, a0
-; CHECK-NEXT: li a0, 256
-; CHECK-NEXT: vxor.vv v10, v10, v12
-; CHECK-NEXT: vand.vx v12, v9, a0
-; CHECK-NEXT: vmul.vv v13, v8, v13
-; CHECK-NEXT: li a0, 512
-; CHECK-NEXT: vxor.vv v10, v10, v11
-; CHECK-NEXT: vand.vx v11, v9, a0
-; CHECK-NEXT: vmul.vv v12, v8, v12
-; CHECK-NEXT: vxor.vv v10, v10, v13
-; CHECK-NEXT: li a0, 1024
-; CHECK-NEXT: vmul.vv v11, v8, v11
-; CHECK-NEXT: vand.vx v13, v9, a0
-; CHECK-NEXT: li a0, 1
-; CHECK-NEXT: slli a0, a0, 11
-; CHECK-NEXT: vxor.vv v10, v10, v12
-; CHECK-NEXT: vand.vx v12, v9, a0
-; CHECK-NEXT: vmul.vv v13, v8, v13
-; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vxor.vv v10, v10, v11
-; CHECK-NEXT: vand.vx v11, v9, a0
-; CHECK-NEXT: vmul.vv v12, v8, v12
-; CHECK-NEXT: vxor.vv v10, v10, v13
-; CHECK-NEXT: lui a0, 2
-; CHECK-NEXT: vmul.vv v11, v8, v11
-; CHECK-NEXT: vand.vx v13, v9, a0
-; CHECK-NEXT: lui a0, 4
-; CHECK-NEXT: vxor.vv v10, v10, v12
-; CHECK-NEXT: vand.vx v12, v9, a0
-; CHECK-NEXT: vmul.vv v13, v8, v13
-; CHECK-NEXT: vxor.vv v10, v10, v11
-; CHECK-NEXT: vmul.vv v11, v8, v12
-; CHECK-NEXT: lui a0, 8
-; CHECK-NEXT: vand.vx v9, v9, a0
-; CHECK-NEXT: vxor.vv v10, v10, v13
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vxor.vv v9, v10, v11
-; CHECK-NEXT: vxor.vv v8, v9, v8
-; CHECK-NEXT: ret
+; RV32V-LABEL: clmul_v4i16:
+; RV32V: # %bb.0:
+; RV32V-NEXT: li a0, 16
+; RV32V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32V-NEXT: vand.vi v10, v9, 2
+; RV32V-NEXT: vand.vi v11, v9, 1
+; RV32V-NEXT: vand.vi v12, v9, 4
+; RV32V-NEXT: vmul.vv v10, v8, v10
+; RV32V-NEXT: vmul.vv v11, v8, v11
+; RV32V-NEXT: vand.vi v13, v9, 8
+; RV32V-NEXT: vmul.vv v12, v8, v12
+; RV32V-NEXT: vxor.vv v10, v11, v10
+; RV32V-NEXT: vmul.vv v11, v8, v13
+; RV32V-NEXT: vand.vx v13, v9, a0
+; RV32V-NEXT: li a0, 32
+; RV32V-NEXT: vxor.vv v10, v10, v12
+; RV32V-NEXT: vand.vx v12, v9, a0
+; RV32V-NEXT: vmul.vv v13, v8, v13
+; RV32V-NEXT: li a0, 64
+; RV32V-NEXT: vxor.vv v10, v10, v11
+; RV32V-NEXT: vand.vx v11, v9, a0
+; RV32V-NEXT: vmul.vv v12, v8, v12
+; RV32V-NEXT: vxor.vv v10, v10, v13
+; RV32V-NEXT: li a0, 128
+; RV32V-NEXT: vmul.vv v11, v8, v11
+; RV32V-NEXT: vand.vx v13, v9, a0
+; RV32V-NEXT: li a0, 256
+; RV32V-NEXT: vxor.vv v10, v10, v12
+; RV32V-NEXT: vand.vx v12, v9, a0
+; RV32V-NEXT: vmul.vv v13, v8, v13
+; RV32V-NEXT: li a0, 512
+; RV32V-NEXT: vxor.vv v10, v10, v11
+; RV32V-NEXT: vand.vx v11, v9, a0
+; RV32V-NEXT: vmul.vv v12, v8, v12
+; RV32V-NEXT: vxor.vv v10, v10, v13
+; RV32V-NEXT: li a0, 1024
+; RV32V-NEXT: vmul.vv v11, v8, v11
+; RV32V-NEXT: vand.vx v13, v9, a0
+; RV32V-NEXT: li a0, 1
+; RV32V-NEXT: slli a0, a0, 11
+; RV32V-NEXT: vxor.vv v10, v10, v12
+; RV32V-NEXT: vand.vx v12, v9, a0
+; RV32V-NEXT: vmul.vv v13, v8, v13
+; RV32V-NEXT: lui a0, 1
+; RV32V-NEXT: vxor.vv v10, v10, v11
+; RV32V-NEXT: vand.vx v11, v9, a0
+; RV32V-NEXT: vmul.vv v12, v8, v12
+; RV32V-NEXT: vxor.vv v10, v10, v13
+; RV32V-NEXT: lui a0, 2
+; RV32V-NEXT: vmul.vv v11, v8, v11
+; RV32V-NEXT: vand.vx v13, v9, a0
+; RV32V-NEXT: lui a0, 4
+; RV32V-NEXT: vxor.vv v10, v10, v12
+; RV32V-NEXT: vand.vx v12, v9, a0
+; RV32V-NEXT: vmul.vv v13, v8, v13
+; RV32V-NEXT: vxor.vv v10, v10, v11
+; RV32V-NEXT: vmul.vv v11, v8, v12
+; RV32V-NEXT: lui a0, 8
+; RV32V-NEXT: vand.vx v9, v9, a0
+; RV32V-NEXT: vxor.vv v10, v10, v13
+; RV32V-NEXT: vmul.vv v8, v8, v9
+; RV32V-NEXT: vxor.vv v9, v10, v11
+; RV32V-NEXT: vxor.vv v8, v9, v8
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmul_v4i16:
+; RV64V: # %bb.0:
+; RV64V-NEXT: li a0, 16
+; RV64V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64V-NEXT: vand.vi v10, v9, 2
+; RV64V-NEXT: vand.vi v11, v9, 1
+; RV64V-NEXT: vand.vi v12, v9, 4
+; RV64V-NEXT: vmul.vv v10, v8, v10
+; RV64V-NEXT: vmul.vv v11, v8, v11
+; RV64V-NEXT: vand.vi v13, v9, 8
+; RV64V-NEXT: vmul.vv v12, v8, v12
+; RV64V-NEXT: vxor.vv v10, v11, v10
+; RV64V-NEXT: vmul.vv v11, v8, v13
+; RV64V-NEXT: vand.vx v13, v9, a0
+; RV64V-NEXT: li a0, 32
+; RV64V-NEXT: vxor.vv v10, v10, v12
+; RV64V-NEXT: vand.vx v12, v9, a0
+; RV64V-NEXT: vmul.vv v13, v8, v13
+; RV64V-NEXT: li a0, 64
+; RV64V-NEXT: vxor.vv v10, v10, v11
+; RV64V-NEXT: vand.vx v11, v9, a0
+; RV64V-NEXT: vmul.vv v12, v8, v12
+; RV64V-NEXT: vxor.vv v10, v10, v13
+; RV64V-NEXT: li a0, 128
+; RV64V-NEXT: vmul.vv v11, v8, v11
+; RV64V-NEXT: vand.vx v13, v9, a0
+; RV64V-NEXT: li a0, 256
+; RV64V-NEXT: vxor.vv v10, v10, v12
+; RV64V-NEXT: vand.vx v12, v9, a0
+; RV64V-NEXT: vmul.vv v13, v8, v13
+; RV64V-NEXT: li a0, 512
+; RV64V-NEXT: vxor.vv v10, v10, v11
+; RV64V-NEXT: vand.vx v11, v9, a0
+; RV64V-NEXT: vmul.vv v12, v8, v12
+; RV64V-NEXT: vxor.vv v10, v10, v13
+; RV64V-NEXT: li a0, 1024
+; RV64V-NEXT: vmul.vv v11, v8, v11
+; RV64V-NEXT: vand.vx v13, v9, a0
+; RV64V-NEXT: li a0, 1
+; RV64V-NEXT: slli a0, a0, 11
+; RV64V-NEXT: vxor.vv v10, v10, v12
+; RV64V-NEXT: vand.vx v12, v9, a0
+; RV64V-NEXT: vmul.vv v13, v8, v13
+; RV64V-NEXT: lui a0, 1
+; RV64V-NEXT: vxor.vv v10, v10, v11
+; RV64V-NEXT: vand.vx v11, v9, a0
+; RV64V-NEXT: vmul.vv v12, v8, v12
+; RV64V-NEXT: vxor.vv v10, v10, v13
+; RV64V-NEXT: lui a0, 2
+; RV64V-NEXT: vmul.vv v11, v8, v11
+; RV64V-NEXT: vand.vx v13, v9, a0
+; RV64V-NEXT: lui a0, 4
+; RV64V-NEXT: vxor.vv v10, v10, v12
+; RV64V-NEXT: vand.vx v12, v9, a0
+; RV64V-NEXT: vmul.vv v13, v8, v13
+; RV64V-NEXT: vxor.vv v10, v10, v11
+; RV64V-NEXT: vmul.vv v11, v8, v12
+; RV64V-NEXT: lui a0, 8
+; RV64V-NEXT: vand.vx v9, v9, a0
+; RV64V-NEXT: vxor.vv v10, v10, v13
+; RV64V-NEXT: vmul.vv v8, v8, v9
+; RV64V-NEXT: vxor.vv v9, v10, v11
+; RV64V-NEXT: vxor.vv v8, v9, v8
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmul_v4i16:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf4 v10, v9
+; RV32ZVBC64-NEXT: vzext.vf4 v12, v8
+; RV32ZVBC64-NEXT: vclmul.vv v8, v12, v10
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v10, v8, 0
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32ZVBC64-NEXT: vnsrl.wi v8, v10, 0
+; RV32ZVBC64-NEXT: ret
+;
+; RV64ZVBC64-LABEL: clmul_v4i16:
+; RV64ZVBC64: # %bb.0:
+; RV64ZVBC64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64ZVBC64-NEXT: vzext.vf4 v10, v9
+; RV64ZVBC64-NEXT: vzext.vf4 v12, v8
+; RV64ZVBC64-NEXT: vclmul.vv v8, v12, v10
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v10, v8, 0
+; RV64ZVBC64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVBC64-NEXT: vnsrl.wi v8, v10, 0
+; RV64ZVBC64-NEXT: ret
+;
+; RV32ZVBC32-LABEL: clmul_v4i16:
+; RV32ZVBC32: # %bb.0:
+; RV32ZVBC32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV32ZVBC32-NEXT: ret
+;
+; RV64ZVBC32-LABEL: clmul_v4i16:
+; RV64ZVBC32: # %bb.0:
+; RV64ZVBC32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64ZVBC32-NEXT: vclmul.vv v8, v8, v9
+; RV64ZVBC32-NEXT: ret
%res = call <4 x i16> @llvm.clmul.v4i16(<4 x i16> %a, <4 x i16> %b)
ret <4 x i16> %res
}
define <4 x i8> @clmulr_v4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
-; CHECK-LABEL: clmulr_v4i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 16
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vzext.vf2 v10, v9
-; CHECK-NEXT: vzext.vf2 v9, v8
-; CHECK-NEXT: vand.vi v8, v10, 2
-; CHECK-NEXT: vand.vi v11, v10, 1
-; CHECK-NEXT: vand.vi v12, v10, 4
-; CHECK-NEXT: vmul.vv v8, v9, v8
-; CHECK-NEXT: vmul.vv v11, v9, v11
-; CHECK-NEXT: vand.vi v13, v10, 8
-; CHECK-NEXT: vmul.vv v12, v9, v12
-; CHECK-NEXT: vxor.vv v8, v11, v8
-; CHECK-NEXT: vmul.vv v11, v9, v13
-; CHECK-NEXT: vand.vx v13, v10, a0
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vxor.vv v8, v8, v12
-; CHECK-NEXT: vand.vx v12, v10, a0
-; CHECK-NEXT: vmul.vv v13, v9, v13
-; CHECK-NEXT: li a0, 64
-; CHECK-NEXT: vxor.vv v8, v8, v11
-; CHECK-NEXT: vand.vx v11, v10, a0
-; CHECK-NEXT: vmul.vv v12, v9, v12
-; CHECK-NEXT: vxor.vv v8, v8, v13
-; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: vmul.vv v11, v9, v11
-; CHECK-NEXT: vand.vx v13, v10, a0
-; CHECK-NEXT: li a0, 256
-; CHECK-NEXT: vxor.vv v8, v8, v12
-; CHECK-NEXT: vand.vx v12, v10, a0
-; CHECK-NEXT: vmul.vv v13, v9, v13
-; CHECK-NEXT: li a0, 512
-; CHECK-NEXT: vxor.vv v8, v8, v11
-; CHECK-NEXT: vand.vx v11, v10, a0
-; CHECK-NEXT: vmul.vv v12, v9, v12
-; CHECK-NEXT: vxor.vv v8, v8, v13
-; CHECK-NEXT: li a0, 1024
-; CHECK-NEXT: vmul.vv v11, v9, v11
-; CHECK-NEXT: vand.vx v13, v10, a0
-; CHECK-NEXT: li a0, 1
-; CHECK-NEXT: slli a0, a0, 11
-; CHECK-NEXT: vxor.vv v8, v8, v12
-; CHECK-NEXT: vand.vx v12, v10, a0
-; CHECK-NEXT: vmul.vv v13, v9, v13
-; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: vxor.vv v8, v8, v11
-; CHECK-NEXT: vand.vx v11, v10, a0
-; CHECK-NEXT: vmul.vv v12, v9, v12
-; CHECK-NEXT: vxor.vv v8, v8, v13
-; CHECK-NEXT: lui a0, 2
-; CHECK-NEXT: vmul.vv v11, v9, v11
-; CHECK-NEXT: vand.vx v13, v10, a0
-; CHECK-NEXT: lui a0, 4
-; CHECK-NEXT: vxor.vv v8, v8, v12
-; CHECK-NEXT: vand.vx v12, v10, a0
-; CHECK-NEXT: vmul.vv v13, v9, v13
-; CHECK-NEXT: vxor.vv v8, v8, v11
-; CHECK-NEXT: vmul.vv v11, v9, v12
-; CHECK-NEXT: lui a0, 8
-; CHECK-NEXT: vand.vx v10, v10, a0
-; CHECK-NEXT: vxor.vv v8, v8, v13
-; CHECK-NEXT: vmul.vv v9, v9, v10
-; CHECK-NEXT: vxor.vv v8, v8, v11
-; CHECK-NEXT: vxor.vv v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v8, 7
-; CHECK-NEXT: ret
+; RV32V-LABEL: clmulr_v4i8:
+; RV32V: # %bb.0:
+; RV32V-NEXT: li a0, 16
+; RV32V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32V-NEXT: vzext.vf2 v10, v9
+; RV32V-NEXT: vzext.vf2 v9, v8
+; RV32V-NEXT: vand.vi v8, v10, 2
+; RV32V-NEXT: vand.vi v11, v10, 1
+; RV32V-NEXT: vand.vi v12, v10, 4
+; RV32V-NEXT: vmul.vv v8, v9, v8
+; RV32V-NEXT: vmul.vv v11, v9, v11
+; RV32V-NEXT: vand.vi v13, v10, 8
+; RV32V-NEXT: vmul.vv v12, v9, v12
+; RV32V-NEXT: vxor.vv v8, v11, v8
+; RV32V-NEXT: vmul.vv v11, v9, v13
+; RV32V-NEXT: vand.vx v13, v10, a0
+; RV32V-NEXT: li a0, 32
+; RV32V-NEXT: vxor.vv v8, v8, v12
+; RV32V-NEXT: vand.vx v12, v10, a0
+; RV32V-NEXT: vmul.vv v13, v9, v13
+; RV32V-NEXT: li a0, 64
+; RV32V-NEXT: vxor.vv v8, v8, v11
+; RV32V-NEXT: vand.vx v11, v10, a0
+; RV32V-NEXT: vmul.vv v12, v9, v12
+; RV32V-NEXT: vxor.vv v8, v8, v13
+; RV32V-NEXT: li a0, 128
+; RV32V-NEXT: vmul.vv v11, v9, v11
+; RV32V-NEXT: vand.vx v13, v10, a0
+; RV32V-NEXT: li a0, 256
+; RV32V-NEXT: vxor.vv v8, v8, v12
+; RV32V-NEXT: vand.vx v12, v10, a0
+; RV32V-NEXT: vmul.vv v13, v9, v13
+; RV32V-NEXT: li a0, 512
+; RV32V-NEXT: vxor.vv v8, v8, v11
+; RV32V-NEXT: vand.vx v11, v10, a0
+; RV32V-NEXT: vmul.vv v12, v9, v12
+; RV32V-NEXT: vxor.vv v8, v8, v13
+; RV32V-NEXT: li a0, 1024
+; RV32V-NEXT: vmul.vv v11, v9, v11
+; RV32V-NEXT: vand.vx v13, v10, a0
+; RV32V-NEXT: li a0, 1
+; RV32V-NEXT: slli a0, a0, 11
+; RV32V-NEXT: vxor.vv v8, v8, v12
+; RV32V-NEXT: vand.vx v12, v10, a0
+; RV32V-NEXT: vmul.vv v13, v9, v13
+; RV32V-NEXT: lui a0, 1
+; RV32V-NEXT: vxor.vv v8, v8, v11
+; RV32V-NEXT: vand.vx v11, v10, a0
+; RV32V-NEXT: vmul.vv v12, v9, v12
+; RV32V-NEXT: vxor.vv v8, v8, v13
+; RV32V-NEXT: lui a0, 2
+; RV32V-NEXT: vmul.vv v11, v9, v11
+; RV32V-NEXT: vand.vx v13, v10, a0
+; RV32V-NEXT: lui a0, 4
+; RV32V-NEXT: vxor.vv v8, v8, v12
+; RV32V-NEXT: vand.vx v12, v10, a0
+; RV32V-NEXT: vmul.vv v13, v9, v13
+; RV32V-NEXT: vxor.vv v8, v8, v11
+; RV32V-NEXT: vmul.vv v11, v9, v12
+; RV32V-NEXT: lui a0, 8
+; RV32V-NEXT: vand.vx v10, v10, a0
+; RV32V-NEXT: vxor.vv v8, v8, v13
+; RV32V-NEXT: vmul.vv v9, v9, v10
+; RV32V-NEXT: vxor.vv v8, v8, v11
+; RV32V-NEXT: vxor.vv v8, v8, v9
+; RV32V-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32V-NEXT: vnsrl.wi v8, v8, 7
+; RV32V-NEXT: ret
+;
+; RV64V-LABEL: clmulr_v4i8:
+; RV64V: # %bb.0:
+; RV64V-NEXT: li a0, 16
+; RV64V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64V-NEXT: vzext.vf2 v10, v9
+; RV64V-NEXT: vzext.vf2 v9, v8
+; RV64V-NEXT: vand.vi v8, v10, 2
+; RV64V-NEXT: vand.vi v11, v10, 1
+; RV64V-NEXT: vand.vi v12, v10, 4
+; RV64V-NEXT: vmul.vv v8, v9, v8
+; RV64V-NEXT: vmul.vv v11, v9, v11
+; RV64V-NEXT: vand.vi v13, v10, 8
+; RV64V-NEXT: vmul.vv v12, v9, v12
+; RV64V-NEXT: vxor.vv v8, v11, v8
+; RV64V-NEXT: vmul.vv v11, v9, v13
+; RV64V-NEXT: vand.vx v13, v10, a0
+; RV64V-NEXT: li a0, 32
+; RV64V-NEXT: vxor.vv v8, v8, v12
+; RV64V-NEXT: vand.vx v12, v10, a0
+; RV64V-NEXT: vmul.vv v13, v9, v13
+; RV64V-NEXT: li a0, 64
+; RV64V-NEXT: vxor.vv v8, v8, v11
+; RV64V-NEXT: vand.vx v11, v10, a0
+; RV64V-NEXT: vmul.vv v12, v9, v12
+; RV64V-NEXT: vxor.vv v8, v8, v13
+; RV64V-NEXT: li a0, 128
+; RV64V-NEXT: vmul.vv v11, v9, v11
+; RV64V-NEXT: vand.vx v13, v10, a0
+; RV64V-NEXT: li a0, 256
+; RV64V-NEXT: vxor.vv v8, v8, v12
+; RV64V-NEXT: vand.vx v12, v10, a0
+; RV64V-NEXT: vmul.vv v13, v9, v13
+; RV64V-NEXT: li a0, 512
+; RV64V-NEXT: vxor.vv v8, v8, v11
+; RV64V-NEXT: vand.vx v11, v10, a0
+; RV64V-NEXT: vmul.vv v12, v9, v12
+; RV64V-NEXT: vxor.vv v8, v8, v13
+; RV64V-NEXT: li a0, 1024
+; RV64V-NEXT: vmul.vv v11, v9, v11
+; RV64V-NEXT: vand.vx v13, v10, a0
+; RV64V-NEXT: li a0, 1
+; RV64V-NEXT: slli a0, a0, 11
+; RV64V-NEXT: vxor.vv v8, v8, v12
+; RV64V-NEXT: vand.vx v12, v10, a0
+; RV64V-NEXT: vmul.vv v13, v9, v13
+; RV64V-NEXT: lui a0, 1
+; RV64V-NEXT: vxor.vv v8, v8, v11
+; RV64V-NEXT: vand.vx v11, v10, a0
+; RV64V-NEXT: vmul.vv v12, v9, v12
+; RV64V-NEXT: vxor.vv v8, v8, v13
+; RV64V-NEXT: lui a0, 2
+; RV64V-NEXT: vmul.vv v11, v9, v11
+; RV64V-NEXT: vand.vx v13, v10, a0
+; RV64V-NEXT: lui a0, 4
+; RV64V-NEXT: vxor.vv v8, v8, v12
+; RV64V-NEXT: vand.vx v12, v10, a0
+; RV64V-NEXT: vmul.vv v13, v9, v13
+; RV64V-NEXT: vxor.vv v8, v8, v11
+; RV64V-NEXT: vmul.vv v11, v9, v12
+; RV64V-NEXT: lui a0, 8
+; RV64V-NEXT: vand.vx v10, v10, a0
+; RV64V-NEXT: vxor.vv v8, v8, v13
+; RV64V-NEXT: vmul.vv v9, v9, v10
+; RV64V-NEXT: vxor.vv v8, v8, v11
+; RV64V-NEXT: vxor.vv v8, v8, v9
+; RV64V-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64V-NEXT: vnsrl.wi v8, v8, 7
+; RV64V-NEXT: ret
+;
+; RV32ZVBC64-LABEL: clmulr_v4i8:
+; RV32ZVBC64: # %bb.0:
+; RV32ZVBC64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf2 v10, v9
+; RV32ZVBC64-NEXT: vzext.vf2 v12, v8
+; RV32ZVBC64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32ZVBC64-NEXT: vzext.vf4 v8, v10
----------------
lukel97 wrote:
Im guessing this is because CLMUL generates ISD::ZERO_EXTENDs when custom lowered, but the zext arguments to the CLMUL in this test case have already been custom lowered to RISCVISD::ZEXT_VL by the time the CLMUL gets custom lowered.
https://github.com/llvm/llvm-project/pull/210429
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