[llvm] [mlir] [NVPTX] Add Rubin extensions to tcgen05.commit (PR #211577)
Rajat Bajpai via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 23 08:12:06 PDT 2026
https://github.com/rajatbajpai created https://github.com/llvm/llvm-project/pull/211577
The Rubin architecture extends `tcgen05.commit` operations with two additional features: support for 32-bit CTA multicast masks and the ability to track completion of Matrix A reads from shared memory for all prior `tcgen05.mma` operations.
This change adds support for these features to the `tcgen05.commit` intrinsics.
>From f46648201848a3e1887af7fc3635a096284f736e Mon Sep 17 00:00:00 2001
From: Rajat Bajpai <rbajpai at nvidia.com>
Date: Thu, 23 Jul 2026 10:40:42 +0000
Subject: [PATCH] [NVPTX] Add Rubin extensions to tcgen05.commit
The Rubin architecture extends `tcgen05.commit` operations with two
additional features: support for 32-bit CTA multicast masks and the
ability to track completion of Matrix A reads from shared memory for
all prior `tcgen05.mma` operations.
This change adds support for these features to the `tcgen05.commit`
intrinsics.
---
llvm/docs/NVPTXUsage.md | 16 +-
llvm/include/llvm/IR/IntrinsicsNVVM.td | 40 +-
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 41 +-
llvm/lib/Target/NVPTX/NVPTXSubtarget.h | 6 +
.../Assembler/auto_upgrade_nvvm_intrinsics.ll | 18 +
.../CodeGen/NVPTX/tcgen05-commit-rubin.ll | 438 ++++++++++++++++++
mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 2 +-
.../Target/LLVMIR/nvvm/tcgen05-commit.mlir | 8 +-
8 files changed, 532 insertions(+), 37 deletions(-)
create mode 100644 llvm/test/CodeGen/NVPTX/tcgen05-commit-rubin.ll
diff --git a/llvm/docs/NVPTXUsage.md b/llvm/docs/NVPTXUsage.md
index 923a2b10f6be9..edd3352079df5 100644
--- a/llvm/docs/NVPTXUsage.md
+++ b/llvm/docs/NVPTXUsage.md
@@ -2634,8 +2634,17 @@ For more information, refer to the [PTX ISA](https://docs.nvidia.com/cuda/parall
```llvm
declare void @llvm.nvvm.tcgen05.commit.{cg1,cg2}(ptr %mbar)
declare void @llvm.nvvm.tcgen05.commit.shared.{cg1,cg2}(ptr addrspace(3) %mbar)
-declare void @llvm.nvvm.tcgen05.commit.mc.{cg1,cg2}(ptr %mbar, i16 %mc)
-declare void @llvm.nvvm.tcgen05.commit.mc.shared.{cg1,cg2}(ptr addrspace(3) %mbar, i16 %mc)
+declare void @llvm.nvvm.tcgen05.commit.mc.{cg1,cg2}.i16(ptr %mbar, i16 %mc)
+declare void @llvm.nvvm.tcgen05.commit.mc.shared.{cg1,cg2}.i16(ptr addrspace(3) %mbar, i16 %mc)
+declare void @llvm.nvvm.tcgen05.commit.mc.{cg1,cg2}.i32(ptr %mbar, i32 %mc)
+declare void @llvm.nvvm.tcgen05.commit.mc.shared.{cg1,cg2}.i32(ptr addrspace(3) %mbar, i32 %mc)
+
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.{cg1,cg2}(ptr %bar_addr)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.shared.{cg1,cg2}(ptr addrspace(3) %bar_addr)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.{cg1,cg2}.i16(ptr %bar_addr, i16 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.{cg1,cg2}.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.{cg1,cg2}.i32(ptr %bar_addr, i32 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.{cg1,cg2}.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
```
##### Overview:
@@ -2647,7 +2656,8 @@ object (`%mbar`) track the completion of all prior asynchronous tcgen05
operations. The `.mc` variants allow signaling on the mbarrier objects of
multiple CTAs (specified by `%mc`) in the cluster. The `.cg1` and `.cg2`
variants generate `cta_group::1` and `cta_group::2` flavors of the
-instruction respectively.
+instruction, respectively. The `smem.a.read` variants allow tracking the completion
+of reads of Matrix A from shared memory for all prior `tcgen05.mma` operations.
For more information, refer to the [PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen-async-sync-operations-commit).
diff --git a/llvm/include/llvm/IR/IntrinsicsNVVM.td b/llvm/include/llvm/IR/IntrinsicsNVVM.td
index 40f3c40a76bc6..26be050d4b22a 100644
--- a/llvm/include/llvm/IR/IntrinsicsNVVM.td
+++ b/llvm/include/llvm/IR/IntrinsicsNVVM.td
@@ -3085,25 +3085,27 @@ foreach cta_group = ["cg1", "cg2"] in {
def int_nvvm_tcgen05_relinq_alloc_permit_ # cta_group : Intrinsic<[], [],
[IntrConvergent, IntrInaccessibleMemOnly]>;
- def int_nvvm_tcgen05_commit_ # cta_group : Intrinsic<[],
- [llvm_ptr_ty], // mbar_ptr
- [IntrConvergent, IntrInaccessibleMemOrArgMemOnly,
- NoCapture<ArgIndex<0>>]>;
-
- def int_nvvm_tcgen05_commit_shared_ # cta_group : Intrinsic<[],
- [llvm_shared_ptr_ty], // mbar_ptr
- [IntrConvergent, IntrInaccessibleMemOrArgMemOnly,
- NoCapture<ArgIndex<0>>]>;
-
- def int_nvvm_tcgen05_commit_mc_ # cta_group : Intrinsic<[],
- [llvm_ptr_ty, llvm_i16_ty], // mbar_ptr, cta_mask
- [IntrConvergent, IntrInaccessibleMemOrArgMemOnly,
- NoCapture<ArgIndex<0>>]>;
-
- def int_nvvm_tcgen05_commit_mc_shared_ # cta_group : Intrinsic<[],
- [llvm_shared_ptr_ty, llvm_i16_ty], // mbar_ptr, cta_mask
- [IntrConvergent, IntrInaccessibleMemOrArgMemOnly,
- NoCapture<ArgIndex<0>>]>;
+ foreach smem_a_read = ["", "smem_a_read_"] in {
+ def int_nvvm_tcgen05_commit_ # smem_a_read # cta_group : Intrinsic<[],
+ [llvm_ptr_ty], // mbar_ptr
+ [IntrConvergent, IntrInaccessibleMemOrArgMemOnly,
+ NoCapture<ArgIndex<0>>]>;
+
+ def int_nvvm_tcgen05_commit_ # smem_a_read # shared_ # cta_group : Intrinsic<[],
+ [llvm_shared_ptr_ty], // mbar_ptr
+ [IntrConvergent, IntrInaccessibleMemOrArgMemOnly,
+ NoCapture<ArgIndex<0>>]>;
+
+ def int_nvvm_tcgen05_commit_ # smem_a_read # mc_ # cta_group : Intrinsic<[],
+ [llvm_ptr_ty, llvm_anyint_ty], // mbar_ptr, cta_mask[16 or 32 bits]
+ [IntrConvergent, IntrInaccessibleMemOrArgMemOnly,
+ NoCapture<ArgIndex<0>>]>;
+
+ def int_nvvm_tcgen05_commit_ # smem_a_read # mc_shared_ # cta_group : Intrinsic<[],
+ [llvm_shared_ptr_ty, llvm_anyint_ty], // mbar_ptr, cta_mask[16 or 32 bits]
+ [IntrConvergent, IntrInaccessibleMemOrArgMemOnly,
+ NoCapture<ArgIndex<0>>]>;
+ }
def int_nvvm_tcgen05_shift_down_ # cta_group : Intrinsic<[],
[llvm_tmem_ptr_ty], // tmem_addr
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 5230e01261fd6..ea2147e720da4 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -5711,25 +5711,41 @@ def tcgen05_wait_ld: NullaryInst<"tcgen05.wait::ld.sync.aligned", int_nvvm_tcgen
def tcgen05_wait_st: NullaryInst<"tcgen05.wait::st.sync.aligned", int_nvvm_tcgen05_wait_st>;
multiclass TCGEN05_COMMIT_INTR<string AS, string num> {
- defvar prefix = "tcgen05.commit.cta_group::" # num #".mbarrier::arrive::one.shared::cluster";
+ defvar prefix = "tcgen05.commit.cta_group::" # num #
+ ".mbarrier::arrive::one.shared::cluster";
+ defvar prefix_smem_a_read = prefix # ".sync_restrict::shared::read::mma::a";
+ defvar intr_prefix = "int_nvvm_tcgen05_commit";
defvar intr_suffix = !if(!eq(AS, "shared"), "_shared", "") # "_cg" # num;
- defvar Intr = !cast<Intrinsic>("int_nvvm_tcgen05_commit" # intr_suffix);
- defvar IntrMC = !cast<Intrinsic>("int_nvvm_tcgen05_commit_mc" # intr_suffix);
+ defvar Intr = !cast<Intrinsic>(intr_prefix # intr_suffix);
+ defvar IntrMC = !cast<Intrinsic>(intr_prefix # "_mc" # intr_suffix);
+ defvar IntrSmemARead =
+ !cast<Intrinsic>(intr_prefix # "_smem_a_read" # intr_suffix);
+ defvar IntrSmemAReadMC =
+ !cast<Intrinsic>(intr_prefix # "_smem_a_read_mc" # intr_suffix);
def "" : BasicNVPTXInst<(outs), (ins ADDR:$mbar),
prefix # ".b64",
[(Intr addr:$mbar)]>;
def _MC : BasicNVPTXInst<(outs), (ins ADDR:$mbar, B16:$mc),
- prefix # ".multicast::cluster.b64",
- [(IntrMC addr:$mbar, B16:$mc)]>;
+ prefix # ".multicast::cluster.b64",
+ [(IntrMC addr:$mbar, i16:$mc)]>;
+ let Predicates = [callSubtarget<"hasTcgen05RubinFamilySupport">] in {
+ def _MC_32B : BasicNVPTXInst<(outs), (ins ADDR:$mbar, B32:$mc),
+ prefix # ".multicast::cluster::32b.b64",
+ [(IntrMC addr:$mbar, i32:$mc)]>;
+ def _SMRA : BasicNVPTXInst<(outs), (ins ADDR:$mbar),
+ prefix_smem_a_read # ".b64",
+ [(IntrSmemARead addr:$mbar)]>;
+ def _SMRA_MC : BasicNVPTXInst<(outs), (ins ADDR:$mbar, B16:$mc),
+ prefix_smem_a_read # ".multicast::cluster.b64",
+ [(IntrSmemAReadMC addr:$mbar, i16:$mc)]>;
+ def _SMRA_MC_32B : BasicNVPTXInst<(outs), (ins ADDR:$mbar, B32:$mc),
+ prefix_smem_a_read # ".multicast::cluster::32b.b64",
+ [(IntrSmemAReadMC addr:$mbar, i32:$mc)]>;
+ }
}
-defm TCGEN05_COMMIT_CG1 : TCGEN05_COMMIT_INTR<"", "1">;
-defm TCGEN05_COMMIT_CG2 : TCGEN05_COMMIT_INTR<"", "2">;
-defm TCGEN05_COMMIT_S64_CG1 : TCGEN05_COMMIT_INTR<"shared", "1">;
-defm TCGEN05_COMMIT_S64_CG2 : TCGEN05_COMMIT_INTR<"shared", "2">;
-
multiclass TCGEN05_CP_INTR<string shape, string src_fmt, string mc = ""> {
defvar dst_fmt = !if(!eq(src_fmt, ""), "", ".b8x16");
defvar fmt_asm = StrJoin<".", [dst_fmt, src_fmt]>.ret;
@@ -5762,6 +5778,11 @@ foreach src_fmt = ["", "b6x16_p32", "b4x16_p64"] in {
}
} // Predicates
+defm TCGEN05_COMMIT_CG1 : TCGEN05_COMMIT_INTR<"", "1">;
+defm TCGEN05_COMMIT_CG2 : TCGEN05_COMMIT_INTR<"", "2">;
+defm TCGEN05_COMMIT_S64_CG1 : TCGEN05_COMMIT_INTR<"shared", "1">;
+defm TCGEN05_COMMIT_S64_CG2 : TCGEN05_COMMIT_INTR<"shared", "2">;
+
let Predicates = [callSubtarget<"hasTcgen05ShiftSupport">] in {
multiclass TCGEN05_SHIFT_INTR<string num, Intrinsic Intr> {
def "" : BasicNVPTXInst<(outs),
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
index 1df5d326f63a6..9561e00c84023 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
@@ -140,6 +140,12 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
hasPTXWithAccelSMs(86, {100, 101});
}
+ // Checks Rubin family extensions support.
+ // - tcgen05.commit
+ bool hasTcgen05RubinFamilySupport() const {
+ return hasPTXWithFamilySMs(94, {107});
+ }
+
// Checks tcgen05.shift instruction support.
bool hasTcgen05ShiftSupport() const {
// sm_101 renamed to sm_110 in PTX 9.0
diff --git a/llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll b/llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
index c59c9bda203b8..d3b815a1ef708 100644
--- a/llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
+++ b/llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
@@ -115,6 +115,11 @@ declare ptr addrspace(3) @llvm.nvvm.mapa.shared.cluster(ptr addrspace(3), i32)
declare void @llvm.nvvm.cp.async.bulk.global.to.shared.cluster(ptr addrspace(3), ptr addrspace(3), ptr addrspace(1), i32, i16, i64, i1, i1)
declare void @llvm.nvvm.cp.async.bulk.shared.cta.to.cluster(ptr addrspace(3), ptr addrspace(3), ptr addrspace(3), i32)
+declare void @llvm.nvvm.tcgen05.commit.mc.cg1(ptr, i16)
+declare void @llvm.nvvm.tcgen05.commit.mc.cg2(ptr, i16)
+declare void @llvm.nvvm.tcgen05.commit.mc.shared.cg1(ptr addrspace(3), i16)
+declare void @llvm.nvvm.tcgen05.commit.mc.shared.cg2(ptr addrspace(3), i16)
+
declare void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.1d(ptr addrspace(3) %d, ptr addrspace(3) %bar, ptr %tm, i32 %d0, i16 %mc, i64 %ch, i1 %f1, i1 %f2);
declare void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d(ptr addrspace(3) %d, ptr addrspace(3) %bar, ptr %tm, i32 %d0, i32 %d1, i16 %mc, i64 %ch, i1 %f1, i1 %f2);
declare void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.3d(ptr addrspace(3) %d, ptr addrspace(3) %bar, ptr %tm, i32 %d0, i32 %d1, i32 %d2, i16 %mc, i64 %ch, i1 %f1, i1 %f2);
@@ -456,6 +461,19 @@ define void @nvvm_cp_async_bulk_intrinsics(ptr addrspace(3) %dst, ptr addrspace(
ret void
}
+; CHECK-LABEL: @nvvm_tcgen05_commit_mc_intrinsics
+define void @nvvm_tcgen05_commit_mc_intrinsics(ptr %bar, ptr addrspace(3) %bar_shared, i16 %cta_mask) {
+; CHECK: call void @llvm.nvvm.tcgen05.commit.mc.cg1.i16(ptr %bar, i16 %cta_mask)
+; CHECK: call void @llvm.nvvm.tcgen05.commit.mc.cg2.i16(ptr %bar, i16 %cta_mask)
+; CHECK: call void @llvm.nvvm.tcgen05.commit.mc.shared.cg1.i16(ptr addrspace(3) %bar_shared, i16 %cta_mask)
+; CHECK: call void @llvm.nvvm.tcgen05.commit.mc.shared.cg2.i16(ptr addrspace(3) %bar_shared, i16 %cta_mask)
+ call void @llvm.nvvm.tcgen05.commit.mc.cg1(ptr %bar, i16 %cta_mask)
+ call void @llvm.nvvm.tcgen05.commit.mc.cg2(ptr %bar, i16 %cta_mask)
+ call void @llvm.nvvm.tcgen05.commit.mc.shared.cg1(ptr addrspace(3) %bar_shared, i16 %cta_mask)
+ call void @llvm.nvvm.tcgen05.commit.mc.shared.cg2(ptr addrspace(3) %bar_shared, i16 %cta_mask)
+ ret void
+}
+
; CHECK-LABEL: @nvvm_cp_async_bulk_tensor_g2s_im2col
define void @nvvm_cp_async_bulk_tensor_g2s_im2col(ptr addrspace(3) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %im2col0, i16 %im2col1, i16 %im2col2, i16 %mc, i64 %ch) {
; CHECK: call void @llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.3d(ptr addrspace(7) %1, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %im2col0, i16 0, i64 0, i1 false, i1 false, i32 0)
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-commit-rubin.ll b/llvm/test/CodeGen/NVPTX/tcgen05-commit-rubin.ll
new file mode 100644
index 0000000000000..0b54e735ef3a9
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-commit-rubin.ll
@@ -0,0 +1,438 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_107f | FileCheck --check-prefixes=CHECK_PTX64 %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_107f --nvptx-short-ptr | FileCheck --check-prefixes=CHECK_PTX64_SHARED32 %s
+
+; RUN: %if ptxas-sm_107f && ptxas-isa-9.4 %{ llc < %s -march=nvptx64 -mcpu=sm_107f | %ptxas-verify -arch=sm_107f %}
+; RUN: %if ptxas-sm_107f && ptxas-isa-9.4 %{ llc < %s -march=nvptx64 -mcpu=sm_107f --nvptx-short-ptr | %ptxas-verify -arch=sm_107f %}
+
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.cg1(ptr %bar_addr)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.cg2(ptr %bar_addr)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.shared.cg1(ptr addrspace(3) %bar_addr)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.shared.cg2(ptr addrspace(3) %bar_addr)
+
+define void @test_tcgen05_commit_smem_a_read_cg1(ptr %bar_addr) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_cg1(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg1_param_0];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_cg1(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg1(ptr %bar_addr)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_cg2(ptr %bar_addr) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_cg2(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg2_param_0];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_cg2(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg2(ptr %bar_addr)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_shared_cg1(ptr addrspace(3) %bar_addr) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_shared_cg1(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_shared_cg1_param_0];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_shared_cg1(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_shared_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%r1];
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.shared.cg1(ptr addrspace(3) %bar_addr)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_shared_cg2(ptr addrspace(3) %bar_addr) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_shared_cg2(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_shared_cg2_param_0];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_shared_cg2(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_shared_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%r1];
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.shared.cg2(ptr addrspace(3) %bar_addr)
+
+ ret void
+}
+
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.i16(ptr %bar_addr, i16 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.i16(ptr %bar_addr, i16 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.cg1.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.cg2.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
+
+define void @test_tcgen05_commit_smem_a_read_mc_cg1(ptr %bar_addr, i16 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_cg1(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b16 %rs<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_cg1(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b16 %rs<2>;
+; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.i16(ptr %bar_addr, i16 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_mc_cg2(ptr %bar_addr, i16 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_cg2(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b16 %rs<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_cg2(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b16 %rs<2>;
+; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.i16(ptr %bar_addr, i16 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_mc_shared_cg1(ptr addrspace(3) %bar_addr, i16 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg1(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b16 %rs<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg1(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b16 %rs<2>;
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%r1], %rs1;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.cg1.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_mc_shared_cg2(ptr addrspace(3) %bar_addr, i16 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg2(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b16 %rs<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg2(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b16 %rs<2>;
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%r1], %rs1;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.cg2.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
+
+ ret void
+}
+
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.i32(ptr %bar_addr, i32 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.i32(ptr %bar_addr, i32 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.cg1.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.cg2.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
+
+define void @test_tcgen05_commit_smem_a_read_mc_cg1_i32(ptr %bar_addr, i32 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_cg1_i32(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_cg1_i32(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.i32(ptr %bar_addr, i32 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_mc_cg2_i32(ptr %bar_addr, i32 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_cg2_i32(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_cg2_i32(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.i32(ptr %bar_addr, i32 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32(ptr addrspace(3) %bar_addr, i32 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%r1], %r2;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.cg1.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32(ptr addrspace(3) %bar_addr, i32 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%r1], %r2;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.shared.cg2.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
+
+ ret void
+}
+
+declare void @llvm.nvvm.tcgen05.commit.mc.cg1.i32(ptr %bar_addr, i32 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.mc.cg2.i32(ptr %bar_addr, i32 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.mc.shared.cg1.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
+declare void @llvm.nvvm.tcgen05.commit.mc.shared.cg2.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
+
+define void @test_tcgen05_commit_mc_cg1_i32(ptr %bar_addr, i32 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_mc_cg1_i32(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg1_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_cg1_i32_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_mc_cg1_i32(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg1_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_cg1_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.mc.cg1.i32(ptr %bar_addr, i32 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_mc_cg2_i32(ptr %bar_addr, i32 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_mc_cg2_i32(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg2_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_cg2_i32_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_mc_cg2_i32(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg2_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_cg2_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.mc.cg2.i32(ptr %bar_addr, i32 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_mc_shared_cg1_i32(ptr addrspace(3) %bar_addr, i32 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_mc_shared_cg1_i32(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_shared_cg1_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_i32_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_mc_shared_cg1_i32(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_commit_mc_shared_cg1_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%r1], %r2;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.mc.shared.cg1.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
+
+ ret void
+}
+
+define void @test_tcgen05_commit_mc_shared_cg2_i32(ptr addrspace(3) %bar_addr, i32 %cta_mask) {
+; CHECK_PTX64-LABEL: test_tcgen05_commit_mc_shared_cg2_i32(
+; CHECK_PTX64: {
+; CHECK_PTX64-NEXT: .reg .b32 %r<2>;
+; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
+; CHECK_PTX64-EMPTY:
+; CHECK_PTX64-NEXT: // %bb.0:
+; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_shared_cg2_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_i32_param_1];
+; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
+; CHECK_PTX64-NEXT: ret;
+;
+; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_mc_shared_cg2_i32(
+; CHECK_PTX64_SHARED32: {
+; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
+; CHECK_PTX64_SHARED32-EMPTY:
+; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_commit_mc_shared_cg2_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%r1], %r2;
+; CHECK_PTX64_SHARED32-NEXT: ret;
+ call void @llvm.nvvm.tcgen05.commit.mc.shared.cg2.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
+
+ ret void
+}
diff --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
index 1f76218936e16..2bf21db6b6e6f 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
@@ -5331,7 +5331,7 @@ def NVVM_Tcgen05CommitOp : NVVM_Op<"tcgen05.commit", [NVVMRequiresSMf<[100, 101,
llvm::SmallVector<llvm::Value *> args;
auto id = NVVM::Tcgen05CommitOp::getIntrinsicIDAndArgs(
*op, moduleTranslation, args);
- createIntrinsicCall(builder, id, args);
+ createIntrinsicCall(builder, id, builder.getVoidTy(), args);
}];
}
diff --git a/mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir b/mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir
index 60475bf64ae7a..6997f8a98b2fc 100644
--- a/mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir
+++ b/mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir
@@ -8,10 +8,10 @@ llvm.func @llvm_nvvm_tcgen05_commit_generic(%barrier : !llvm.ptr, %cta_mask : i1
// CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.cg2(ptr %{{.*}})
nvvm.tcgen05.commit %barrier {group = #nvvm.cta_group<cta_2>} : !llvm.ptr
- // CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.mc.cg1(ptr %{{.*}}, i16 %{{.*}})
+ // CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.mc.cg1.i16(ptr %{{.*}}, i16 %{{.*}})
nvvm.tcgen05.commit %barrier, multicast_mask = %cta_mask : !llvm.ptr, i16
- // CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.mc.cg2(ptr %{{.*}}, i16 %{{.*}})
+ // CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.mc.cg2.i16(ptr %{{.*}}, i16 %{{.*}})
nvvm.tcgen05.commit %barrier, multicast_mask = %cta_mask {group = #nvvm.cta_group<cta_2>} : !llvm.ptr, i16
llvm.return
}
@@ -24,10 +24,10 @@ llvm.func @llvm_nvvm_tcgen05_commit_shared(%barrier : !llvm.ptr<3>, %cta_mask :
// CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.shared.cg2(ptr addrspace(3) %{{.*}})
nvvm.tcgen05.commit %barrier {group = #nvvm.cta_group<cta_2>} : !llvm.ptr<3>
- // CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.mc.shared.cg1(ptr addrspace(3) %{{.*}}, i16 %{{.*}})
+ // CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.mc.shared.cg1.i16(ptr addrspace(3) %{{.*}}, i16 %{{.*}})
nvvm.tcgen05.commit %barrier, multicast_mask = %cta_mask : !llvm.ptr<3>, i16
- // CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.mc.shared.cg2(ptr addrspace(3) %{{.*}}, i16 %{{.*}})
+ // CHECK-LLVM: call void @llvm.nvvm.tcgen05.commit.mc.shared.cg2.i16(ptr addrspace(3) %{{.*}}, i16 %{{.*}})
nvvm.tcgen05.commit %barrier, multicast_mask = %cta_mask {group = #nvvm.cta_group<cta_2>} : !llvm.ptr<3>, i16
llvm.return
}
More information about the llvm-commits
mailing list