[llvm] [RISCV] Add TuneNoDefaultUnroll to spacemit-x60 (PR #211502)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)

<details>
<summary>Changes</summary>

This feature has been added to generic CPUs in #<!-- -->135318 and we don't
see any significant regression on `spacemit-x60`.


---
Full diff: https://github.com/llvm/llvm-project/pull/211502.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+2-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 471b8694914a6..15a4f680d8082 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -908,7 +908,8 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                         TuneOptimizedNF4SegmentLoadStore,
                                         TuneEnableSelectOptimize,
                                         TuneVXRMPipelineFlush,
-                                        TunePreferAscendingLoadStore]> {
+                                        TunePreferAscendingLoadStore,
+                                        TuneNoDefaultUnroll]> {
   let MVendorID = 0x710;
   let MArchID = 0x8000000058000001;
   let MImpID = 0x1000000049772200;

``````````

</details>


https://github.com/llvm/llvm-project/pull/211502