[llvm] [MachineLICM] Only mark live-ins as non-invariant if defined in loop (PR #191755)
Yuyang Zhang via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 23 00:03:08 PDT 2026
https://github.com/yuyzhang512 updated https://github.com/llvm/llvm-project/pull/191755
>From 1cbe8d708d249e0031194381836b385908df45d1 Mon Sep 17 00:00:00 2001
From: yuyzhang512 <yuyzhang at amd.com>
Date: Wed, 22 Jul 2026 09:52:50 +0000
Subject: [PATCH] [MachineLICM] Only mark live-ins as non-invariant if defined
in loop
HoistRegionPostRA treated every loop live-in as defined in the loop, so any
instruction reading a live-in was not hoisted. A live-in never redefined in
the loop is invariant. Collect the register units defined in the loop, then
mark a live-in only if it overlaps one (register-unit granularity handles
tuples).
Helps instructions created after pre-RA LICM, e.g. the per-lane COPYs
Two-Address emits when lowering a REG_SEQUENCE into an aligned tuple, whose
constant-field copies read an invariant live-in.
---
llvm/lib/CodeGen/MachineLICM.cpp | 33 ++++++++++---
.../AArch64/avoid-free-ext-promotion.ll | 2 +-
.../CodeGen/AArch64/mlicm-implicit-defs.mir | 6 +--
llvm/test/CodeGen/AArch64/peephole-and-tst.ll | 2 +-
.../CodeGen/AMDGPU/indirect-addressing-si.ll | 20 ++++----
.../CodeGen/AMDGPU/insert-delay-alu-bug.ll | 4 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll | 1 -
...hinelicm-hoist-buffer-desc-const-fields.ll | 46 +++++++++++++++++++
.../CodeGen/AMDGPU/no-dup-inst-prefetch.ll | 34 +++++++-------
.../CodeGen/ARM/debug-info-branch-folding.ll | 1 +
llvm/test/CodeGen/ARM/shifter_operand.ll | 20 ++++----
.../AVR/branch-relaxation-long-backward.ll | 8 ++--
.../DAGCombiner_illegal_BUILD_VECTOR.ll | 2 +-
llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll | 3 +-
llvm/test/CodeGen/Thumb2/mve-phireg.ll | 35 +++++++-------
llvm/test/CodeGen/Thumb2/pr52817.ll | 8 ++--
.../CodeGen/X86/2007-01-13-StackPtrIndex.ll | 4 +-
.../CodeGen/X86/2009-04-25-CoalescerBug.ll | 2 +-
llvm/test/CodeGen/X86/apx/nf-regressions.ll | 24 +++++-----
llvm/test/CodeGen/X86/assertzext-demanded.ll | 2 +-
.../CodeGen/X86/combine-i64-trunc-srl-add.ll | 2 +-
llvm/test/CodeGen/X86/combine-pmuldq.ll | 4 +-
.../test/CodeGen/X86/constant-pool-sharing.ll | 8 ++--
llvm/test/CodeGen/X86/postalloc-coalescing.ll | 1 -
llvm/test/CodeGen/X86/pr22338.ll | 4 +-
llvm/test/CodeGen/X86/pr63108.ll | 8 ++--
.../test/CodeGen/X86/promote-sra-by-itself.ll | 2 +-
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 2 +-
.../CodeGen/X86/split-extend-vector-inreg.ll | 4 +-
llvm/test/CodeGen/X86/trunc-store.ll | 2 +-
llvm/test/CodeGen/X86/undef-label.ll | 11 +++--
31 files changed, 187 insertions(+), 118 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/machinelicm-hoist-buffer-desc-const-fields.ll
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 53fbd3bec76cd..f1eb1f22e202f 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -582,6 +582,20 @@ void MachineLICMImpl::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
}
}
+/// Set the register units defined by \p MI in \p Defs.
+static void addRegUnitDefs(const MachineInstr &MI, const TargetRegisterInfo *TRI,
+ BitVector &Defs) {
+ for (const MachineOperand &MO : MI.operands()) {
+ if (!MO.isReg() || !MO.isDef())
+ continue;
+ Register Reg = MO.getReg();
+ if (!Reg)
+ continue;
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ Defs.set(static_cast<unsigned>(Unit));
+ }
+}
+
/// Walk the specified region of the CFG and hoist loop invariants out to the
/// preheader.
void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
@@ -596,20 +610,27 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
SmallVector<CandidateInfo, 32> Candidates;
SmallDenseSet<int> StoredFIs;
- // Walk the entire region, count number of defs for each register, and
- // collect potential LICM candidates.
+ // First pass: collect all register units defined within the loop.
+ BitVector LoopRUDefs(NumRegUnits);
+ for (MachineBasicBlock *BB : CurLoop->getBlocks())
+ for (MachineInstr &MI : *BB)
+ addRegUnitDefs(MI, TRI, LoopRUDefs);
+
+ // Second pass: walk the entire region, count number of defs for each
+ // register, and collect potential LICM candidates.
for (MachineBasicBlock *BB : CurLoop->getBlocks()) {
// If the header of the loop containing this basic block is a landing pad,
// then don't try to hoist instructions out of this loop.
const MachineLoop *ML = MLI->getLoopFor(BB);
if (ML && ML->getHeader()->isEHPad()) continue;
- // Conservatively treat live-in's as an external def.
- // FIXME: That means a reload that're reused in successor block(s) will not
- // be LICM'ed.
+ // Only treat live-in registers that are also defined within the loop as
+ // non-invariant. Live-ins that are solely defined outside the loop are
+ // loop-invariant and should not block hoisting.
for (const auto &LI : BB->liveins()) {
for (MCRegUnit Unit : TRI->regunits(LI.PhysReg))
- RUDefs.set(static_cast<unsigned>(Unit));
+ if (LoopRUDefs.test(static_cast<unsigned>(Unit)))
+ RUDefs.set(static_cast<unsigned>(Unit));
}
// Funclet entry blocks will clobber all registers
diff --git a/llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll b/llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll
index 5f5b27af5c8cf..337eb90a13ed0 100644
--- a/llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll
+++ b/llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll
@@ -14,9 +14,9 @@ define void @avoid_promotion_1_and(ptr nocapture noundef %arg, ptr %p) {
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: ldr w8, [x0, #52]
; CHECK-NEXT: mov w9, #10 ; =0xa
+; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: LBB0_1: ; %bb8
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmp w8, #3
; CHECK-NEXT: b.lo LBB0_1
; CHECK-NEXT: ; %bb.2: ; %bb9
; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
diff --git a/llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir b/llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir
index 2c5a70288cfad..658755489ff44 100644
--- a/llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir
+++ b/llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir
@@ -62,15 +62,15 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x12 = COPY killed $x0
+ ; CHECK-NEXT: $x1 = COPY killed $x12
; CHECK-NEXT: $x2 = MOVi64imm 1024, implicit-def dead $x16
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK-NEXT: liveins: $x12, $x2
+ ; CHECK-NEXT: liveins: $x12, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x1 = COPY killed $x12
- ; CHECK-NEXT: $x16 = LDRXroX killed $x1, $x2, 0, 0
+ ; CHECK-NEXT: $x16 = LDRXroX $x1, $x2, 0, 0
; CHECK-NEXT: $xzr = SUBSXri $x16, 0, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 1, %bb.1, implicit $nzcv
; CHECK-NEXT: B %bb.2
diff --git a/llvm/test/CodeGen/AArch64/peephole-and-tst.ll b/llvm/test/CodeGen/AArch64/peephole-and-tst.ll
index 6449f5d5f07d3..8f775ebfbf51d 100644
--- a/llvm/test/CodeGen/AArch64/peephole-and-tst.ll
+++ b/llvm/test/CodeGen/AArch64/peephole-and-tst.ll
@@ -36,6 +36,7 @@ define i32 @test_func_i32_two_uses(i32 %in, i32 %bit, i32 %mask) {
; CHECK-GI-LABEL: test_func_i32_two_uses:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: adrp x8, :got:ptr_wrapper
+; CHECK-GI-NEXT: and w11, w2, w0
; CHECK-GI-NEXT: ldr x8, [x8, :got_lo12:ptr_wrapper]
; CHECK-GI-NEXT: ldr x9, [x8]
; CHECK-GI-NEXT: mov w8, wzr
@@ -49,7 +50,6 @@ define i32 @test_func_i32_two_uses(i32 %in, i32 %bit, i32 %mask) {
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-GI-NEXT: and w10, w1, w0
; CHECK-GI-NEXT: tst w1, w0
-; CHECK-GI-NEXT: and w11, w2, w0
; CHECK-GI-NEXT: cinc w8, w8, ne
; CHECK-GI-NEXT: cmp w10, w11
; CHECK-GI-NEXT: b.eq .LBB0_1
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
index 127f4996b7676..f2d44952e9dde 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
@@ -8720,6 +8720,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; GENERIC-NEXT: v_mov_b32_e32 v0, 8
; GENERIC-NEXT: s_mov_b32 s3, 0xf000
; GENERIC-NEXT: s_mov_b32 s2, -1
+; GENERIC-NEXT: s_waitcnt lgkmcnt(0)
+; GENERIC-NEXT: v_mov_b32_e32 v17, s1
; GENERIC-NEXT: s_branch .LBB26_3
; GENERIC-NEXT: .LBB26_1: ; in Loop: Header=BB26_3 Depth=1
; GENERIC-NEXT: s_mov_b64 s[4:5], -1
@@ -8733,14 +8735,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; GENERIC-NEXT: .LBB26_3: ; %bb2
; GENERIC-NEXT: ; =>This Loop Header: Depth=1
; GENERIC-NEXT: ; Child Loop BB26_5 Depth 2
-; GENERIC-NEXT: s_waitcnt lgkmcnt(0)
; GENERIC-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; GENERIC-NEXT: s_cbranch_vccnz .LBB26_1
; GENERIC-NEXT: ; %bb.4: ; %bb4
; GENERIC-NEXT: ; in Loop: Header=BB26_3 Depth=1
; GENERIC-NEXT: buffer_load_dword v16, off, s[0:3], 0 glc
; GENERIC-NEXT: s_waitcnt vmcnt(0)
-; GENERIC-NEXT: v_mov_b32_e32 v17, s1
; GENERIC-NEXT: s_mov_b64 s[4:5], exec
; GENERIC-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GENERIC-NEXT: .LBB26_5: ; Parent Loop BB26_3 Depth=1
@@ -9014,6 +9014,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; SI-MOVREL-NEXT: v_mov_b32_e32 v0, 8
; SI-MOVREL-NEXT: s_mov_b32 s3, 0xf000
; SI-MOVREL-NEXT: s_mov_b32 s2, -1
+; SI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-MOVREL-NEXT: v_mov_b32_e32 v17, s1
; SI-MOVREL-NEXT: s_branch .LBB26_3
; SI-MOVREL-NEXT: .LBB26_1: ; in Loop: Header=BB26_3 Depth=1
; SI-MOVREL-NEXT: s_mov_b64 s[4:5], -1
@@ -9027,14 +9029,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; SI-MOVREL-NEXT: .LBB26_3: ; %bb2
; SI-MOVREL-NEXT: ; =>This Loop Header: Depth=1
; SI-MOVREL-NEXT: ; Child Loop BB26_5 Depth 2
-; SI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
; SI-MOVREL-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; SI-MOVREL-NEXT: s_cbranch_vccnz .LBB26_1
; SI-MOVREL-NEXT: ; %bb.4: ; %bb4
; SI-MOVREL-NEXT: ; in Loop: Header=BB26_3 Depth=1
; SI-MOVREL-NEXT: buffer_load_dword v16, off, s[0:3], 0 glc
; SI-MOVREL-NEXT: s_waitcnt vmcnt(0)
-; SI-MOVREL-NEXT: v_mov_b32_e32 v17, s1
; SI-MOVREL-NEXT: s_mov_b64 s[4:5], exec
; SI-MOVREL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; SI-MOVREL-NEXT: .LBB26_5: ; Parent Loop BB26_3 Depth=1
@@ -9057,6 +9057,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; VI-MOVREL: ; %bb.0: ; %bb
; VI-MOVREL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-MOVREL-NEXT: v_mov_b32_e32 v0, 8
+; VI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-MOVREL-NEXT: v_mov_b32_e32 v17, s1
; VI-MOVREL-NEXT: s_branch .LBB26_3
; VI-MOVREL-NEXT: .LBB26_1: ; in Loop: Header=BB26_3 Depth=1
; VI-MOVREL-NEXT: s_mov_b64 s[2:3], -1
@@ -9070,14 +9072,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; VI-MOVREL-NEXT: .LBB26_3: ; %bb2
; VI-MOVREL-NEXT: ; =>This Loop Header: Depth=1
; VI-MOVREL-NEXT: ; Child Loop BB26_5 Depth 2
-; VI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
; VI-MOVREL-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; VI-MOVREL-NEXT: s_cbranch_vccnz .LBB26_1
; VI-MOVREL-NEXT: ; %bb.4: ; %bb4
; VI-MOVREL-NEXT: ; in Loop: Header=BB26_3 Depth=1
; VI-MOVREL-NEXT: flat_load_dword v16, v[0:1] glc
; VI-MOVREL-NEXT: s_waitcnt vmcnt(0)
-; VI-MOVREL-NEXT: v_mov_b32_e32 v17, s1
; VI-MOVREL-NEXT: s_mov_b64 s[2:3], exec
; VI-MOVREL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; VI-MOVREL-NEXT: .LBB26_5: ; Parent Loop BB26_3 Depth=1
@@ -9100,6 +9100,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; VI-IDXMODE: ; %bb.0: ; %bb
; VI-IDXMODE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-IDXMODE-NEXT: v_mov_b32_e32 v0, 8
+; VI-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
+; VI-IDXMODE-NEXT: v_mov_b32_e32 v17, s1
; VI-IDXMODE-NEXT: s_branch .LBB26_3
; VI-IDXMODE-NEXT: .LBB26_1: ; in Loop: Header=BB26_3 Depth=1
; VI-IDXMODE-NEXT: s_mov_b64 s[2:3], -1
@@ -9113,14 +9115,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; VI-IDXMODE-NEXT: .LBB26_3: ; %bb2
; VI-IDXMODE-NEXT: ; =>This Loop Header: Depth=1
; VI-IDXMODE-NEXT: ; Child Loop BB26_5 Depth 2
-; VI-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
; VI-IDXMODE-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; VI-IDXMODE-NEXT: s_cbranch_vccnz .LBB26_1
; VI-IDXMODE-NEXT: ; %bb.4: ; %bb4
; VI-IDXMODE-NEXT: ; in Loop: Header=BB26_3 Depth=1
; VI-IDXMODE-NEXT: flat_load_dword v16, v[0:1] glc
; VI-IDXMODE-NEXT: s_waitcnt vmcnt(0)
-; VI-IDXMODE-NEXT: v_mov_b32_e32 v17, s1
; VI-IDXMODE-NEXT: s_mov_b64 s[2:3], exec
; VI-IDXMODE-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; VI-IDXMODE-NEXT: .LBB26_5: ; Parent Loop BB26_3 Depth=1
@@ -9144,6 +9144,8 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; GFX9-IDXMODE: ; %bb.0: ; %bb
; GFX9-IDXMODE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v0, 8
+; GFX9-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v17, s1
; GFX9-IDXMODE-NEXT: s_branch .LBB26_3
; GFX9-IDXMODE-NEXT: .LBB26_1: ; in Loop: Header=BB26_3 Depth=1
; GFX9-IDXMODE-NEXT: s_mov_b64 s[2:3], -1
@@ -9157,14 +9159,12 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
; GFX9-IDXMODE-NEXT: .LBB26_3: ; %bb2
; GFX9-IDXMODE-NEXT: ; =>This Loop Header: Depth=1
; GFX9-IDXMODE-NEXT: ; Child Loop BB26_5 Depth 2
-; GFX9-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-IDXMODE-NEXT: v_cmp_le_i32_e32 vcc, s0, v0
; GFX9-IDXMODE-NEXT: s_cbranch_vccnz .LBB26_1
; GFX9-IDXMODE-NEXT: ; %bb.4: ; %bb4
; GFX9-IDXMODE-NEXT: ; in Loop: Header=BB26_3 Depth=1
; GFX9-IDXMODE-NEXT: global_load_dword v16, v[0:1], off glc
; GFX9-IDXMODE-NEXT: s_waitcnt vmcnt(0)
-; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v17, s1
; GFX9-IDXMODE-NEXT: s_mov_b64 s[2:3], exec
; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-IDXMODE-NEXT: .LBB26_5: ; Parent Loop BB26_3 Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
index 6ec64dbe69b08..a5f08a4e9d857 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
@@ -176,10 +176,10 @@ define amdgpu_kernel void @f2(i32 %arg, i32 %arg1, i32 %arg2, i1 %arg3, i32 %arg
; GFX11-NEXT: s_cbranch_vccz .LBB2_13
; GFX11-NEXT: ; %bb.10:
; GFX11-NEXT: s_xor_b32 s0, s3, -1
-; GFX11-NEXT: .LBB2_11: ; %bb17
-; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s0
+; GFX11-NEXT: .LBB2_11: ; %bb17
+; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_cbranch_vccz .LBB2_11
; GFX11-NEXT: ; %bb.12: ; %Flow6
; GFX11-NEXT: s_mov_b32 s21, -1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
index 8973dc21b118f..bec8cb74408cf 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
@@ -1720,7 +1720,6 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1,
; GFX12-GISEL-NEXT: .LBB25_2: ; %bb
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_add_f32 s0, s0, 0x3e800000
-; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0
; GFX12-GISEL-NEXT: s_cbranch_scc1 .LBB25_2
; GFX12-GISEL-NEXT: ; %bb.3: ; %bb33
; GFX12-GISEL-NEXT: s_and_not1_b64 s[2:3], s[2:3], exec
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-hoist-buffer-desc-const-fields.ll b/llvm/test/CodeGen/AMDGPU/machinelicm-hoist-buffer-desc-const-fields.ll
new file mode 100644
index 0000000000000..dc6272e06711e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-hoist-buffer-desc-const-fields.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=amdgcn -mcpu=gfx950 < %s | FileCheck %s
+
+; The descriptors' constant fields come from a REG_SEQUENCE that Two-Address
+; lowers into copies of a loop-invariant live-in, after pre-RA LICM has run, so
+; only post-RA MachineLICM can hoist them.
+define amdgpu_kernel void @buffer_desc_const_fields(ptr addrspace(1) %p) {
+; CHECK-LABEL: buffer_desc_const_fields:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; CHECK-NEXT: s_mov_b32 s2, 0
+; CHECK-NEXT: s_mov_b64 s[4:5], 0
+; CHECK-NEXT: s_and_b64 vcc, exec, -1
+; CHECK-NEXT: s_mov_b32 s10, s2
+; CHECK-NEXT: s_mov_b32 s11, s2
+; CHECK-NEXT: s_mov_b32 m0, 0
+; CHECK-NEXT: .p2align 5, , 4
+; CHECK-NEXT: .LBB0_1: ; %loop
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: s_and_b32 s1, s5, 0xffff
+; CHECK-NEXT: s_add_u32 s8, s4, 0x180
+; CHECK-NEXT: s_mov_b32 s0, s4
+; CHECK-NEXT: s_addc_u32 s4, s5, 0
+; CHECK-NEXT: s_and_b32 s9, s4, 0xffff
+; CHECK-NEXT: s_mov_b32 s3, s2
+; CHECK-NEXT: buffer_load_ubyte off, s[8:11], 0 lds
+; CHECK-NEXT: buffer_load_ubyte off, s[0:3], 0 lds
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_mov_b64 s[4:5], s[6:7]
+; CHECK-NEXT: s_mov_b64 vcc, vcc
+; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
+; CHECK-NEXT: ; %bb.2: ; %DummyReturnBlock
+; CHECK-NEXT: s_endpgm
+entry:
+ br label %loop
+loop:
+ %ptr = phi ptr addrspace(1) [ null, %entry ], [ %p, %loop ]
+ %rsrc0 = tail call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) %ptr, i16 0, i64 0, i32 0)
+ %ptr1 = getelementptr i8, ptr addrspace(1) %ptr, i64 384
+ %rsrc1 = tail call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) %ptr1, i16 0, i64 0, i32 0)
+ tail call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc1, ptr addrspace(3) null, i32 1, i32 0, i32 0, i32 0, i32 0)
+ tail call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc0, ptr addrspace(3) null, i32 1, i32 0, i32 0, i32 0, i32 0)
+ br label %loop
+}
+declare ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1), i16, i64, i32)
+declare void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8), ptr addrspace(3), i32, i32, i32, i32, i32)
diff --git a/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll b/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
index 22f17fa4a6dc9..1637211e9c66a 100644
--- a/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
@@ -10,8 +10,15 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s1, 0
+; GFX10-NEXT: s_mov_b32 s8, s4
+; GFX10-NEXT: s_mov_b32 s9, s4
+; GFX10-NEXT: s_mov_b32 s10, s4
+; GFX10-NEXT: s_mov_b32 s11, s4
+; GFX10-NEXT: s_mov_b32 s12, s4
+; GFX10-NEXT: s_mov_b32 s13, s4
+; GFX10-NEXT: s_mov_b32 s14, s4
+; GFX10-NEXT: s_mov_b32 s15, s4
; GFX10-NEXT: ; implicit-def: $sgpr2
-; GFX10-NEXT: s_inst_prefetch 0x1
; GFX10-NEXT: s_branch .LBB0_2
; GFX10-NEXT: .p2align 6
; GFX10-NEXT: .LBB0_1: ; %Flow
@@ -32,14 +39,6 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX10-NEXT: s_mov_b32 s5, s4
; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s7, s4
-; GFX10-NEXT: s_mov_b32 s8, s4
-; GFX10-NEXT: s_mov_b32 s9, s4
-; GFX10-NEXT: s_mov_b32 s10, s4
-; GFX10-NEXT: s_mov_b32 s11, s4
-; GFX10-NEXT: s_mov_b32 s12, s4
-; GFX10-NEXT: s_mov_b32 s13, s4
-; GFX10-NEXT: s_mov_b32 s14, s4
-; GFX10-NEXT: s_mov_b32 s15, s4
; GFX10-NEXT: s_andn2_b32 s2, s2, exec_lo
; GFX10-NEXT: image_sample_lz v1, [v2, v2, v1], s[8:15], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_3D
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -49,7 +48,6 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX10-NEXT: s_or_b32 s2, s2, s0
; GFX10-NEXT: s_branch .LBB0_1
; GFX10-NEXT: .LBB0_4: ; %loop0_merge
-; GFX10-NEXT: s_inst_prefetch 0x2
; GFX10-NEXT: s_endpgm
;
; GFX12-LABEL: _amdgpu_cs_main:
@@ -59,6 +57,14 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_mov_b32 s4, 0
; GFX12-NEXT: s_mov_b32 s1, 0
+; GFX12-NEXT: s_mov_b32 s8, s4
+; GFX12-NEXT: s_mov_b32 s9, s4
+; GFX12-NEXT: s_mov_b32 s10, s4
+; GFX12-NEXT: s_mov_b32 s11, s4
+; GFX12-NEXT: s_mov_b32 s12, s4
+; GFX12-NEXT: s_mov_b32 s13, s4
+; GFX12-NEXT: s_mov_b32 s14, s4
+; GFX12-NEXT: s_mov_b32 s15, s4
; GFX12-NEXT: ; implicit-def: $sgpr2
; GFX12-NEXT: s_branch .LBB0_2
; GFX12-NEXT: .LBB0_1: ; %Flow
@@ -80,14 +86,6 @@ define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX12-NEXT: s_mov_b32 s5, s4
; GFX12-NEXT: s_mov_b32 s6, s4
; GFX12-NEXT: s_mov_b32 s7, s4
-; GFX12-NEXT: s_mov_b32 s8, s4
-; GFX12-NEXT: s_mov_b32 s9, s4
-; GFX12-NEXT: s_mov_b32 s10, s4
-; GFX12-NEXT: s_mov_b32 s11, s4
-; GFX12-NEXT: s_mov_b32 s12, s4
-; GFX12-NEXT: s_mov_b32 s13, s4
-; GFX12-NEXT: s_mov_b32 s14, s4
-; GFX12-NEXT: s_mov_b32 s15, s4
; GFX12-NEXT: s_and_not1_b32 s2, s2, exec_lo
; GFX12-NEXT: image_sample_lz v1, [v2, v2, v1], s[8:15], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_3D
; GFX12-NEXT: s_wait_samplecnt 0x0
diff --git a/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll b/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
index ba71fdf54b26b..b691c7516c465 100644
--- a/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
+++ b/llvm/test/CodeGen/ARM/debug-info-branch-folding.ll
@@ -3,6 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
target triple = "thumbv7-apple-macosx10.6.7"
;CHECK: vadd.f32 q4, q8, q9
+;CHECK-NEXT: cmp r0, #0
;CHECK-NEXT: LBB0_1
;CHECK: @DEBUG_VALUE: x <- $q4{{$}}
diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll
index 00922b1bf2492..9e979588faa3c 100644
--- a/llvm/test/CodeGen/ARM/shifter_operand.ll
+++ b/llvm/test/CodeGen/ARM/shifter_operand.ll
@@ -461,18 +461,19 @@ define void @test_mutateddag(i32 %b, i32 %c, i32 %d, i1 %cc) {
; CHECK-THUMB-NEXT: movt r5, :upper16:arr_9
; CHECK-THUMB-NEXT: movt r2, #64028
; CHECK-THUMB-NEXT: lsls r3, r3, #31
+; CHECK-THUMB-NEXT: cmp r3, #0
; CHECK-THUMB-NEXT: add.w r0, r0, r4, lsl #1
; CHECK-THUMB-NEXT: add r0, r5
; CHECK-THUMB-NEXT: add r2, r0
; CHECK-THUMB-NEXT: movw r0, #25756
; CHECK-THUMB-NEXT: movt r0, #26
-; CHECK-THUMB-NEXT: muls r0, r1, r0
+; CHECK-THUMB-NEXT: mul r0, r1, r0
; CHECK-THUMB-NEXT: movw r1, #24420
; CHECK-THUMB-NEXT: movt r1, #19356
; CHECK-THUMB-NEXT: add.w r0, r0, r4, lsl #1
; CHECK-THUMB-NEXT: add r0, r5
; CHECK-THUMB-NEXT: add r1, r0
-; CHECK-THUMB-NEXT: movs r0, #0
+; CHECK-THUMB-NEXT: mov.w r0, #0
; CHECK-THUMB-NEXT: b .LBB19_2
; CHECK-THUMB-NEXT: .LBB19_1: @ %for.cond1.for.cond.cleanup_crit_edge
; CHECK-THUMB-NEXT: @ in Loop: Header=BB19_2 Depth=1
@@ -481,18 +482,17 @@ define void @test_mutateddag(i32 %b, i32 %c, i32 %d, i1 %cc) {
; CHECK-THUMB-NEXT: .LBB19_2: @ %for.cond
; CHECK-THUMB-NEXT: @ =>This Loop Header: Depth=1
; CHECK-THUMB-NEXT: @ Child Loop BB19_3 Depth 2
-; CHECK-THUMB-NEXT: movs r4, #0
-; CHECK-THUMB-NEXT: .LBB19_3: @ %for.cond2.preheader
-; CHECK-THUMB-NEXT: @ Parent Loop BB19_2 Depth=1
-; CHECK-THUMB-NEXT: @ => This Inner Loop Header: Depth=2
-; CHECK-THUMB-NEXT: cmp r3, #0
+; CHECK-THUMB-NEXT: mov.w r4, #0
; CHECK-THUMB-NEXT: str r0, [r2, r4]
; CHECK-THUMB-NEXT: bne .LBB19_1
-; CHECK-THUMB-NEXT: @ %bb.4: @ %for.cond2.preheader.2
-; CHECK-THUMB-NEXT: @ in Loop: Header=BB19_3 Depth=2
+; CHECK-THUMB-NEXT: .LBB19_3: @ %for.cond2.preheader.2
+; CHECK-THUMB-NEXT: @ Parent Loop BB19_2 Depth=1
+; CHECK-THUMB-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-THUMB-NEXT: str r0, [r1, r4]
; CHECK-THUMB-NEXT: add r4, r12
-; CHECK-THUMB-NEXT: b .LBB19_3
+; CHECK-THUMB-NEXT: str r0, [r2, r4]
+; CHECK-THUMB-NEXT: beq .LBB19_3
+; CHECK-THUMB-NEXT: b .LBB19_1
entry:
%0 = add i32 %d, -4
%1 = mul i32 %c, 864846
diff --git a/llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll b/llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll
index 9e1aa1066bff9..9357d89de2bf6 100644
--- a/llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll
+++ b/llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll
@@ -4,20 +4,20 @@
; ATTINY85: <main>:
; ATTINY85-NEXT: andi r24, 0x1
; ATTINY85: cpi r24, 0x0
-; ATTINY85-NEXT: breq .-2
+; ATTINY85: breq .-2
; ATTINY85-NEXT: R_AVR_7_PCREL .text+0x100c
; ATTINY85-NEXT: rjmp .-2
-; ATTINY85-NEXT: R_AVR_13_PCREL .text+0x2
+; ATTINY85-NEXT: R_AVR_13_PCREL .text+0x4
; ATTINY85: ldi r24, 0x3
; ATTINY85-NEXT: ret
; AVR3: <main>:
; AVR3-NEXT: andi r24, 0x1
; AVR3: cpi r24, 0x0
-; AVR3-NEXT: breq .-2
+; AVR3: breq .-2
; AVR3-NEXT: R_AVR_7_PCREL .text+0x100e
; AVR3-NEXT: jmp 0x0
-; AVR3-NEXT: R_AVR_CALL .text+0x2
+; AVR3-NEXT: R_AVR_CALL .text+0x4
; AVR3: ldi r24, 0x3
; AVR3-NEXT: ret
diff --git a/llvm/test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll b/llvm/test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll
index 02bae826dcbc1..694013b82536e 100644
--- a/llvm/test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll
+++ b/llvm/test/CodeGen/SystemZ/DAGCombiner_illegal_BUILD_VECTOR.ll
@@ -8,9 +8,9 @@
define void @pr32422(double %a0) {
; CHECK-LABEL: pr32422:
; CHECK: # %bb.0: # %BB
+; CHECK-NEXT: cdbr %f0, %f0
; CHECK-NEXT: .LBB0_1: # %CF
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cdbr %f0, %f0
; CHECK-NEXT: jo .LBB0_1
; CHECK-NEXT: # %bb.2: # %CF353
; CHECK-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
index 278f0bf2a30f6..84f865ee3cf72 100644
--- a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
@@ -11,9 +11,10 @@ define void @pr32275(<4 x i8> %B15) {
; CHECK-NEXT: vrepif %v1, 1
; CHECK-NEXT: vn %v0, %v0, %v1
; CHECK-NEXT: vlgvf %r0, %v0, 3
+; CHECK-NEXT: chi %r0, 0
; CHECK-NEXT: .LBB0_1: # %CF34
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cijlh %r0, 0, .LBB0_1
+; CHECK-NEXT: jlh .LBB0_1
; CHECK-NEXT: # %bb.2: # %CF36
; CHECK-NEXT: br %r14
BB:
diff --git a/llvm/test/CodeGen/Thumb2/mve-phireg.ll b/llvm/test/CodeGen/Thumb2/mve-phireg.ll
index 00a998cba6426..65ac504b1935d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-phireg.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-phireg.ll
@@ -17,12 +17,13 @@ define arm_aapcs_vfpcc void @k() {
; CHECK-NEXT: vldrw.u32 q6, [r5]
; CHECK-NEXT: vldrw.u32 q5, [r4]
; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vmov.i32 q0, #0x1
; CHECK-NEXT: vmov.i8 q1, #0x0
; CHECK-NEXT: vmov.i8 q2, #0xff
; CHECK-NEXT: vmov.i16 q3, #0x6
; CHECK-NEXT: vmov.i16 q4, #0x3
-; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: .LBB0_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vand q5, q5, q0
@@ -39,28 +40,28 @@ define arm_aapcs_vfpcc void @k() {
; CHECK-NEXT: vpsel q6, q4, q3
; CHECK-NEXT: vstrh.16 q6, [r0]
; CHECK-NEXT: vmov.i32 q6, #0x0
-; CHECK-NEXT: cbz r1, .LBB0_2
-; CHECK-NEXT: le .LBB0_1
-; CHECK-NEXT: .LBB0_2: @ %for.cond4.preheader
+; CHECK-NEXT: bne .LBB0_1
+; CHECK-NEXT: @ %bb.2: @ %for.cond4.preheader
; CHECK-NEXT: movs r6, #0
-; CHECK-NEXT: cbnz r6, .LBB0_5
-; CHECK-NEXT: .LBB0_3: @ %for.body10
+; CHECK-NEXT: cbnz r6, .LBB0_6
+; CHECK-NEXT: @ %bb.3:
+; CHECK-NEXT: cmp r6, #0
+; CHECK-NEXT: .LBB0_4: @ %for.body10
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cbnz r6, .LBB0_4
-; CHECK-NEXT: le .LBB0_3
-; CHECK-NEXT: .LBB0_4: @ %for.cond4.loopexit
+; CHECK-NEXT: beq .LBB0_4
+; CHECK-NEXT: @ %bb.5: @ %for.cond4.loopexit
; CHECK-NEXT: bl l
-; CHECK-NEXT: .LBB0_5: @ %vector.body105.preheader
+; CHECK-NEXT: .LBB0_6: @ %vector.body105.preheader
; CHECK-NEXT: vldrw.u32 q0, [r5]
; CHECK-NEXT: vldrw.u32 q1, [r4]
; CHECK-NEXT: movs r0, #8
-; CHECK-NEXT: .LBB0_6: @ %vector.body105
+; CHECK-NEXT: cmp r6, #0
+; CHECK-NEXT: .LBB0_7: @ %vector.body105
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vadd.i32 q1, q1, r0
; CHECK-NEXT: vadd.i32 q0, q0, r0
-; CHECK-NEXT: cbz r6, .LBB0_7
-; CHECK-NEXT: le .LBB0_6
-; CHECK-NEXT: .LBB0_7: @ %vector.body115.ph
+; CHECK-NEXT: bne .LBB0_7
+; CHECK-NEXT: @ %bb.8: @ %vector.body115.ph
; CHECK-NEXT: vldrw.u32 q0, [r4]
; CHECK-NEXT: movs r0, #4
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
@@ -68,12 +69,12 @@ define arm_aapcs_vfpcc void @k() {
; CHECK-NEXT: nop
; CHECK-NEXT: @NO_APP
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
-; CHECK-NEXT: .LBB0_8: @ %vector.body115
+; CHECK-NEXT: .LBB0_9: @ %vector.body115
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vadd.i32 q0, q0, r0
-; CHECK-NEXT: b .LBB0_8
+; CHECK-NEXT: b .LBB0_9
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: @ %bb.9:
+; CHECK-NEXT: @ %bb.10:
; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 4 @ 0x4
; CHECK-NEXT: .long 5 @ 0x5
diff --git a/llvm/test/CodeGen/Thumb2/pr52817.ll b/llvm/test/CodeGen/Thumb2/pr52817.ll
index 87615f0a1f7ef..db6b680dae9d5 100644
--- a/llvm/test/CodeGen/Thumb2/pr52817.ll
+++ b/llvm/test/CodeGen/Thumb2/pr52817.ll
@@ -22,11 +22,11 @@ define i32 @test(ptr %arg, ptr %arg1, ptr %arg2) #0 !dbg !6 {
; CHECK-NEXT: mov.w r9, #1
; CHECK-NEXT: movw r12, #4100
; CHECK-NEXT: movs r3, #0
+; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: LBB0_1: @ %bb3
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: adds r5, r3, #1
+; CHECK-NEXT: add.w r5, r3, #1
; CHECK-NEXT: str.w lr, [r2]
-; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: add.w r4, r0, r5, lsl #2
; CHECK-NEXT: add.w r8, r4, r12
; CHECK-NEXT: lsl.w r4, r9, r3
@@ -36,11 +36,11 @@ define i32 @test(ptr %arg, ptr %arg1, ptr %arg2) #0 !dbg !6 {
; CHECK-NEXT: movne r6, #0
; CHECK-NEXT: Ltmp0:
; CHECK-NEXT: @DEBUG_VALUE: test:this <- [DW_OP_LLVM_arg 0, DW_OP_plus_uconst 135168, DW_OP_LLVM_arg 1, DW_OP_constu 4, DW_OP_mul, DW_OP_plus, DW_OP_plus_uconst 4, DW_OP_stack_value] $r0, $r5
-; CHECK-NEXT: .loc 1 28 24 prologue_end @ test.cpp:28:24
+; CHECK-NEXT: .loc 1 28 24 prologue_end @ test.cpp:28:24 @[ test.cpp:204:23 ]
; CHECK-NEXT: strne.w r6, [r8]
; CHECK-NEXT: moveq r6, #1
; CHECK-NEXT: ldr r4, [r4, #4]
-; CHECK-NEXT: orrs r4, r6
+; CHECK-NEXT: orr.w r4, r4, r6
; CHECK-NEXT: str.w r4, [r8]
; CHECK-NEXT: b LBB0_1
; CHECK-NEXT: Ltmp1:
diff --git a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
index 1e5ee2f71d9b4..9e9688c7389bb 100644
--- a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
+++ b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
@@ -27,10 +27,10 @@ define dso_local void @foo(ptr %a0, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5)
; CHECK-NEXT: js .LBB0_14
; CHECK-NEXT: # %bb.12:
; CHECK-NEXT: xorl %r8d, %r8d
+; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_13: # %a25b
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: je .LBB0_13
; CHECK-NEXT: .LBB0_14: # %b85
; CHECK-NEXT: movb $1, %r8b
@@ -38,10 +38,10 @@ define dso_local void @foo(ptr %a0, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5)
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.15:
; CHECK-NEXT: xorl %r8d, %r8d
+; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_16: # %a25b140
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb %r8b, %r8b
; CHECK-NEXT: je .LBB0_16
; CHECK-NEXT: .LBB0_1: # %a29b
; CHECK-NEXT: cmpl %esi, %edi
diff --git a/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll b/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
index 1dd30e8263099..a01ee300a08c5 100644
--- a/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
+++ b/llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
@@ -8,10 +8,10 @@ define i64 @test(ptr %tmp13) nounwind {
; CHECK-NEXT: movl (%rdi), %ecx
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: shrl %eax
+; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %while.cond
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %while.end
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/apx/nf-regressions.ll b/llvm/test/CodeGen/X86/apx/nf-regressions.ll
index 68bd05a0737b6..fd20b3b422b44 100644
--- a/llvm/test/CodeGen/X86/apx/nf-regressions.ll
+++ b/llvm/test/CodeGen/X86/apx/nf-regressions.ll
@@ -9,12 +9,13 @@ define void @convertToThreeAddress(ptr %arg, ptr %arg1) {
; CHECK-NEXT: subq %rax, %rcx
; CHECK-NEXT: leaq 1(%rcx), %rax
; CHECK-NEXT: js .LBB0_1
+; CHECK-NEXT: # %bb.6: # %bb.preheader
+; CHECK-NEXT: cmpq $1, %rax
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_6: # %bb
+; CHECK-NEXT: .LBB0_7: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq $1, %rax
-; CHECK-NEXT: jg .LBB0_6
-; CHECK-NEXT: .LBB0_5: # %bb16
+; CHECK-NEXT: jg .LBB0_7
+; CHECK-NEXT: .LBB0_9: # %bb16
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: xorl %edx, %edx
@@ -23,21 +24,22 @@ define void @convertToThreeAddress(ptr %arg, ptr %arg1) {
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %dl, %dl
; CHECK-NEXT: je .LBB0_3
-; CHECK-NEXT: # %bb.7: # %bb11
+; CHECK-NEXT: # %bb.8: # %bb11
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: testq %rcx, %rcx
; CHECK-NEXT: jns .LBB0_2
-; CHECK-NEXT: jmp .LBB0_5
+; CHECK-NEXT: jmp .LBB0_9
; CHECK-NEXT: .LBB0_3: # %bb10
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testb %cl, %cl
-; CHECK-NEXT: jne .LBB0_5
+; CHECK-NEXT: jne .LBB0_9
+; CHECK-NEXT: # %bb.4:
+; CHECK-NEXT: cmpq $1, %rax
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_4: # %bb12
+; CHECK-NEXT: .LBB0_5: # %bb12
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq $1, %rax
-; CHECK-NEXT: jg .LBB0_4
-; CHECK-NEXT: jmp .LBB0_5
+; CHECK-NEXT: jg .LBB0_5
+; CHECK-NEXT: jmp .LBB0_9
entry:
%i = load i32, ptr %arg, align 4
%i2 = sext i32 %i to i64
diff --git a/llvm/test/CodeGen/X86/assertzext-demanded.ll b/llvm/test/CodeGen/X86/assertzext-demanded.ll
index 33a8c543ed9ab..fd314d8a2d3b9 100644
--- a/llvm/test/CodeGen/X86/assertzext-demanded.ll
+++ b/llvm/test/CodeGen/X86/assertzext-demanded.ll
@@ -7,10 +7,10 @@ define void @simplify_assertzext(ptr %0) {
; CHECK: # %bb.0: # %BB
; CHECK-NEXT: movl $275047, %eax # imm = 0x43267
; CHECK-NEXT: movb $1, %cl
+; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %CF246
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %CF260
; CHECK-NEXT: orl $278403, %eax # imm = 0x43F83
diff --git a/llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll b/llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
index f7906e5a009ae..84c2b7946e1fb 100644
--- a/llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
+++ b/llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
@@ -233,10 +233,10 @@ define i32 @pr128158(i64 %x) {
; X64-NEXT: movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000
; X64-NEXT: addq %rdi, %rax
; X64-NEXT: shrq $32, %rax
+; X64-NEXT: cmpl $9, %eax
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB16_1: # %for.body
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: cmpl $9, %eax
; X64-NEXT: jb .LBB16_1
; X64-NEXT: # %bb.2: # %exit
; X64-NEXT: xorl %eax, %eax
diff --git a/llvm/test/CodeGen/X86/combine-pmuldq.ll b/llvm/test/CodeGen/X86/combine-pmuldq.ll
index 20d42192b993a..bec37d515e283 100644
--- a/llvm/test/CodeGen/X86/combine-pmuldq.ll
+++ b/llvm/test/CodeGen/X86/combine-pmuldq.ll
@@ -208,20 +208,20 @@ define <8 x i64> @combine_zext_pmuludq_256(<8 x i32> %a) {
define void @PR39398(i32 %a0) {
; SSE-LABEL: PR39398:
; SSE: # %bb.0: # %bb
+; SSE-NEXT: cmpl $232, %edi
; SSE-NEXT: .p2align 4
; SSE-NEXT: .LBB5_1: # %bb10
; SSE-NEXT: # =>This Inner Loop Header: Depth=1
-; SSE-NEXT: cmpl $232, %edi
; SSE-NEXT: jne .LBB5_1
; SSE-NEXT: # %bb.2: # %bb34
; SSE-NEXT: retq
;
; AVX-LABEL: PR39398:
; AVX: # %bb.0: # %bb
+; AVX-NEXT: cmpl $232, %edi
; AVX-NEXT: .p2align 4
; AVX-NEXT: .LBB5_1: # %bb10
; AVX-NEXT: # =>This Inner Loop Header: Depth=1
-; AVX-NEXT: cmpl $232, %edi
; AVX-NEXT: jne .LBB5_1
; AVX-NEXT: # %bb.2: # %bb34
; AVX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/constant-pool-sharing.ll b/llvm/test/CodeGen/X86/constant-pool-sharing.ll
index be835f78292e5..647fa4a6e6d9d 100644
--- a/llvm/test/CodeGen/X86/constant-pool-sharing.ll
+++ b/llvm/test/CodeGen/X86/constant-pool-sharing.ll
@@ -12,12 +12,12 @@ define void @share_v4i32_v4f32(ptr %p, ptr %q, i1 %t) nounwind {
; SSE-LINUX-LABEL: share_v4i32_v4f32:
; SSE-LINUX: # %bb.0: # %entry
; SSE-LINUX-NEXT: movaps {{.*#+}} xmm0 = [1073741824,1073741824,1073741824,1073741824]
+; SSE-LINUX-NEXT: testb $1, %dl
; SSE-LINUX-NEXT: .p2align 4
; SSE-LINUX-NEXT: .LBB0_1: # %loop
; SSE-LINUX-NEXT: # =>This Inner Loop Header: Depth=1
; SSE-LINUX-NEXT: movaps %xmm0, (%rdi)
; SSE-LINUX-NEXT: movaps %xmm0, (%rsi)
-; SSE-LINUX-NEXT: testb $1, %dl
; SSE-LINUX-NEXT: jne .LBB0_1
; SSE-LINUX-NEXT: # %bb.2: # %ret
; SSE-LINUX-NEXT: retq
@@ -25,12 +25,12 @@ define void @share_v4i32_v4f32(ptr %p, ptr %q, i1 %t) nounwind {
; SSE-MSVC-LABEL: share_v4i32_v4f32:
; SSE-MSVC: # %bb.0: # %entry
; SSE-MSVC-NEXT: movaps {{.*#+}} xmm0 = [1073741824,1073741824,1073741824,1073741824]
+; SSE-MSVC-NEXT: testb $1, %r8b
; SSE-MSVC-NEXT: .p2align 4
; SSE-MSVC-NEXT: .LBB0_1: # %loop
; SSE-MSVC-NEXT: # =>This Inner Loop Header: Depth=1
; SSE-MSVC-NEXT: movaps %xmm0, (%rcx)
; SSE-MSVC-NEXT: movaps %xmm0, (%rdx)
-; SSE-MSVC-NEXT: testb $1, %r8b
; SSE-MSVC-NEXT: jne .LBB0_1
; SSE-MSVC-NEXT: # %bb.2: # %ret
; SSE-MSVC-NEXT: retq
@@ -39,12 +39,12 @@ define void @share_v4i32_v4f32(ptr %p, ptr %q, i1 %t) nounwind {
; AVX-LINUX: # %bb.0: # %entry
; AVX-LINUX-NEXT: vbroadcastss {{.*#+}} xmm0 = [1073741824,1073741824,1073741824,1073741824]
; AVX-LINUX-NEXT: vbroadcastss {{.*#+}} xmm1 = [1073741824,1073741824,1073741824,1073741824]
+; AVX-LINUX-NEXT: testb $1, %dl
; AVX-LINUX-NEXT: .p2align 4
; AVX-LINUX-NEXT: .LBB0_1: # %loop
; AVX-LINUX-NEXT: # =>This Inner Loop Header: Depth=1
; AVX-LINUX-NEXT: vmovaps %xmm0, (%rdi)
; AVX-LINUX-NEXT: vmovaps %xmm1, (%rsi)
-; AVX-LINUX-NEXT: testb $1, %dl
; AVX-LINUX-NEXT: jne .LBB0_1
; AVX-LINUX-NEXT: # %bb.2: # %ret
; AVX-LINUX-NEXT: retq
@@ -53,12 +53,12 @@ define void @share_v4i32_v4f32(ptr %p, ptr %q, i1 %t) nounwind {
; AVX-MSVC: # %bb.0: # %entry
; AVX-MSVC-NEXT: vbroadcastss {{.*#+}} xmm0 = [1073741824,1073741824,1073741824,1073741824]
; AVX-MSVC-NEXT: vbroadcastss {{.*#+}} xmm1 = [1073741824,1073741824,1073741824,1073741824]
+; AVX-MSVC-NEXT: testb $1, %r8b
; AVX-MSVC-NEXT: .p2align 4
; AVX-MSVC-NEXT: .LBB0_1: # %loop
; AVX-MSVC-NEXT: # =>This Inner Loop Header: Depth=1
; AVX-MSVC-NEXT: vmovaps %xmm0, (%rcx)
; AVX-MSVC-NEXT: vmovaps %xmm1, (%rdx)
-; AVX-MSVC-NEXT: testb $1, %r8b
; AVX-MSVC-NEXT: jne .LBB0_1
; AVX-MSVC-NEXT: # %bb.2: # %ret
; AVX-MSVC-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/postalloc-coalescing.ll b/llvm/test/CodeGen/X86/postalloc-coalescing.ll
index 7430d7a9baf26..ca9cc71ba078e 100644
--- a/llvm/test/CodeGen/X86/postalloc-coalescing.ll
+++ b/llvm/test/CodeGen/X86/postalloc-coalescing.ll
@@ -11,7 +11,6 @@ define fastcc i32 @_Z18yy_get_next_bufferv() nounwind {
; CHECK-NEXT: .LBB0_1: # %bb116
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movb %al, 0
-; CHECK-NEXT: cmpl $-1, %eax
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: .LBB0_3: # %bb158
; CHECK-NEXT: movb %al, 0
diff --git a/llvm/test/CodeGen/X86/pr22338.ll b/llvm/test/CodeGen/X86/pr22338.ll
index bf3967ca8fede..fd8c23c245793 100644
--- a/llvm/test/CodeGen/X86/pr22338.ll
+++ b/llvm/test/CodeGen/X86/pr22338.ll
@@ -21,10 +21,10 @@ define i32 @fn(i32 %a0, i32 %a1) {
; X86-NEXT: addb %dl, %dl
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: shll %cl, %eax
+; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB0_1: # %bb1
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: je .LBB0_1
; X86-NEXT: # %bb.2: # %bb2
; X86-NEXT: popl %ebx
@@ -46,10 +46,10 @@ define i32 @fn(i32 %a0, i32 %a1) {
; X64-NEXT: addb %dl, %dl
; X64-NEXT: movl %edx, %ecx
; X64-NEXT: shll %cl, %eax
+; X64-NEXT: testl %esi, %esi
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB0_1: # %bb1
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: testl %esi, %esi
; X64-NEXT: je .LBB0_1
; X64-NEXT: # %bb.2: # %bb2
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr63108.ll b/llvm/test/CodeGen/X86/pr63108.ll
index b5b80515fc6d9..7f0844c8af65d 100644
--- a/llvm/test/CodeGen/X86/pr63108.ll
+++ b/llvm/test/CodeGen/X86/pr63108.ll
@@ -16,11 +16,11 @@ define i32 @PR63108() {
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: movd {{.*#+}} xmm1 = [57339,0,0,0]
; SSE-NEXT: xorl %eax, %eax
+; SSE-NEXT: testb %al, %al
; SSE-NEXT: .p2align 4
; SSE-NEXT: .LBB0_3: # %vector.body
; SSE-NEXT: # =>This Inner Loop Header: Depth=1
; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: testb %al, %al
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: jne .LBB0_3
; SSE-NEXT: # %bb.4: # %middle.block
@@ -50,12 +50,12 @@ define i32 @PR63108() {
; AVX1-NEXT: .LBB0_2: # %vector.body.preheader
; AVX1-NEXT: vmovss {{.*#+}} xmm0 = [57339,0,0,0]
; AVX1-NEXT: xorl %eax, %eax
+; AVX1-NEXT: testb %al, %al
; AVX1-NEXT: .p2align 4
; AVX1-NEXT: .LBB0_3: # %vector.body
; AVX1-NEXT: # =>This Inner Loop Header: Depth=1
; AVX1-NEXT: vmovaps %ymm0, %ymm1
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: testb %al, %al
; AVX1-NEXT: jne .LBB0_3
; AVX1-NEXT: # %bb.4: # %middle.block
; AVX1-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
@@ -86,12 +86,12 @@ define i32 @PR63108() {
; AVX2-NEXT: .LBB0_2: # %vector.body.preheader
; AVX2-NEXT: vmovd {{.*#+}} xmm0 = [57339,0,0,0]
; AVX2-NEXT: xorl %eax, %eax
+; AVX2-NEXT: testb %al, %al
; AVX2-NEXT: .p2align 4
; AVX2-NEXT: .LBB0_3: # %vector.body
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
; AVX2-NEXT: vmovdqa %ymm0, %ymm1
; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
-; AVX2-NEXT: testb %al, %al
; AVX2-NEXT: jne .LBB0_3
; AVX2-NEXT: # %bb.4: # %middle.block
; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
@@ -122,12 +122,12 @@ define i32 @PR63108() {
; AVX512-NEXT: .LBB0_2: # %vector.body.preheader
; AVX512-NEXT: vmovd {{.*#+}} xmm0 = [57339,0,0,0]
; AVX512-NEXT: xorl %eax, %eax
+; AVX512-NEXT: testb %al, %al
; AVX512-NEXT: .p2align 4
; AVX512-NEXT: .LBB0_3: # %vector.body
; AVX512-NEXT: # =>This Inner Loop Header: Depth=1
; AVX512-NEXT: vmovdqa %ymm0, %ymm1
; AVX512-NEXT: vpxor %xmm0, %xmm0, %xmm0
-; AVX512-NEXT: testb %al, %al
; AVX512-NEXT: jne .LBB0_3
; AVX512-NEXT: # %bb.4: # %middle.block
; AVX512-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
diff --git a/llvm/test/CodeGen/X86/promote-sra-by-itself.ll b/llvm/test/CodeGen/X86/promote-sra-by-itself.ll
index d57411f495b69..001e6bbc5909a 100644
--- a/llvm/test/CodeGen/X86/promote-sra-by-itself.ll
+++ b/llvm/test/CodeGen/X86/promote-sra-by-itself.ll
@@ -19,10 +19,10 @@ define i16 @basic(ptr %p) {
define void @crash(i1 %cond, ptr %p) {
; CHECK-LABEL: crash:
; CHECK: # %bb.0:
+; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB1_1: # %loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB1_1
; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 69a6cdb7081eb..a13255f8c55d4 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -82,11 +82,11 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: movq _syCTRO at GOTPCREL(%rip), %rax
; CHECK-NEXT: movl $1, %r13d
; CHECK-NEXT: movb $1, %cl
+; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB0_9: ## %do.body
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl $0, (%rax)
-; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: jne LBB0_9
; CHECK-NEXT: ## %bb.10: ## %do.end
; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
diff --git a/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll b/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
index c8e31f7088a45..fdde231ded80f 100644
--- a/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
+++ b/llvm/test/CodeGen/X86/split-extend-vector-inreg.ll
@@ -9,10 +9,10 @@ define <4 x i64> @autogen_SD88863() {
; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X86-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[3],ymm1[3]
; X86-NEXT: movb $1, %al
+; X86-NEXT: testb %al, %al
; X86-NEXT: .p2align 4
; X86-NEXT: .LBB0_1: # %CF
; X86-NEXT: # =>This Inner Loop Header: Depth=1
-; X86-NEXT: testb %al, %al
; X86-NEXT: jne .LBB0_1
; X86-NEXT: # %bb.2: # %CF240
; X86-NEXT: retl
@@ -23,10 +23,10 @@ define <4 x i64> @autogen_SD88863() {
; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[3],ymm1[3]
; X64-NEXT: movb $1, %al
+; X64-NEXT: testb %al, %al
; X64-NEXT: .p2align 4
; X64-NEXT: .LBB0_1: # %CF
; X64-NEXT: # =>This Inner Loop Header: Depth=1
-; X64-NEXT: testb %al, %al
; X64-NEXT: jne .LBB0_1
; X64-NEXT: # %bb.2: # %CF240
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/trunc-store.ll b/llvm/test/CodeGen/X86/trunc-store.ll
index 3ce06f7caa28e..925e6c93d8ed2 100644
--- a/llvm/test/CodeGen/X86/trunc-store.ll
+++ b/llvm/test/CodeGen/X86/trunc-store.ll
@@ -29,10 +29,10 @@
define void @fn1(i64 %a0) {
; CHECK-LABEL: fn1:
; CHECK: # %bb.0: # %for.cond
+; CHECK-NEXT: cmpq $8, %rdi
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq $8, %rdi
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %middle.block
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/undef-label.ll b/llvm/test/CodeGen/X86/undef-label.ll
index a2d9bc571f582..a13b10e4f0495 100644
--- a/llvm/test/CodeGen/X86/undef-label.ll
+++ b/llvm/test/CodeGen/X86/undef-label.ll
@@ -14,13 +14,14 @@ define dso_local void @xyz() {
; CHECK-NEXT: xorpd %xmm1, %xmm1
; CHECK-NEXT: ucomisd %xmm1, %xmm0
; CHECK-NEXT: jne .LBB0_1
-; CHECK-NEXT: jnp .LBB0_2
+; CHECK-NEXT: jnp .LBB0_3
+; CHECK-NEXT: .LBB0_1: # %foo.preheader
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_1: # %foo
+; CHECK-NEXT: .LBB0_2: # %foo
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ucomisd %xmm1, %xmm0
-; CHECK-NEXT: ja .LBB0_1
-; CHECK-NEXT: .LBB0_2: # %bar
+; CHECK-NEXT: ja .LBB0_2
+; CHECK-NEXT: .LBB0_3: # %bar
; CHECK-NEXT: retq
entry:
%cmp1 = fcmp oeq double bitcast (i64 ptrtoint (ptr @g to i64) to double), 0.000000e+00
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