[llvm] da27aac - [RISCV][P-ext] Add packed sign and zero extend intrinsics (#208685)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 22 22:55:49 PDT 2026
Author: SiHuaN
Date: 2026-07-23T13:55:44+08:00
New Revision: da27aac10e157e5659ba6dfa0e362b570a236978
URL: https://github.com/llvm/llvm-project/commit/da27aac10e157e5659ba6dfa0e362b570a236978
DIFF: https://github.com/llvm/llvm-project/commit/da27aac10e157e5659ba6dfa0e362b570a236978.diff
LOG: [RISCV][P-ext] Add packed sign and zero extend intrinsics (#208685)
Add SelectionDAG and intrinsic support for the RISC-V P packed sign- and
zero-extend operations.
Sign-extend is matched through `sext_inreg` (folded from the `shl`/`ashr`
idiom by the generic combiner) and selects to `psext.*`. Zero-extend reuses
the existing `PPAIRE` node with a zero operand instead of a new target node,
since `pzext.* rd, rs` is an alias of `ppaire.* rd, rs, x0`: implementing
`isVectorClearMaskLegal` lets the generic `DAGCombiner::XformToShuffleWithZero`
rewrite the `(and vXi16, 0xff)` / `(and vXi32, 0xffff)` idiom into a shuffle
with a zero operand, which `lowerVECTOR_SHUFFLEAsPPair` folds to `PPAIRE`.
Also adds the LLVM IR intrinsics `llvm.riscv.psext.b`/`.h` and
`llvm.riscv.pzext.b`/`.h`. For RV64 32-bit packed results, the lowering widens
to the legal 64-bit type and extracts the low subvector.
Added:
llvm/test/CodeGen/RISCV/rvp-simd-intrinsic-invalid.ll
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoP.td
llvm/test/CodeGen/RISCV/rvp-simd-32.ll
llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index fca28455f2117..b35c555af6a6e 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2095,6 +2095,16 @@ class RVPBinaryIntrinsic
[IntrNoMem, IntrSpeculatable]>;
def int_riscv_pmerge : RVPTernaryIntrinsic;
+ // Packed Sign and Zero Extend.
+ class RVPExtIntrinsic
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable]>;
+ def int_riscv_psext_b : RVPExtIntrinsic;
+ def int_riscv_psext_h : RVPExtIntrinsic;
+ def int_riscv_pzext_b : RVPExtIntrinsic;
+ def int_riscv_pzext_h : RVPExtIntrinsic;
+
// Packed Absolute Difference Sum.
def int_riscv_pabdsumu
: DefaultAttrsIntrinsic<[llvm_anyint_ty],
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4398db2fc0169..23af87a615273 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -723,12 +723,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
{MVT::v4i16, MVT::v2i32}, Legal);
setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, {MVT::v4i16, MVT::v2i32},
Custom);
- // LegalizeVectorOps uses result VT, LegalizeDAG uses ExtVT.
- setOperationAction(ISD::SIGN_EXTEND_INREG,
- {MVT::v2i16, MVT::v4i8, MVT::v2i32, MVT::v4i16},
- Legal);
setOperationAction(ISD::TRUNCATE, {MVT::v4i8, MVT::v2i16}, Custom);
}
+ // LegalizeVectorOps uses result VT, LegalizeDAG uses ExtVT.
+ setOperationAction(
+ ISD::SIGN_EXTEND_INREG,
+ {MVT::v2i8, MVT::v4i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}, Legal);
}
if (Subtarget.hasStdExtZfbfmin()) {
@@ -6458,6 +6458,24 @@ static SDValue lowerVECTOR_SHUFFLEAsPUnzip(ShuffleVectorSDNode *SVN,
return DAG.getNode(Opc, DL, VT, V1, V2);
}
+// Match the packed zero-extend shuffle mask <0, N, 2, N+2, ...>: even result
+// lanes keep operand 0's even lanes and odd result lanes come from operand 1.
+// The odd lanes may select any element of operand 1, which is looser than a
+// strict pair-even mask; DAGCombiner::XformToShuffleWithZero forms exactly this
+// from a packed zero-extend `and`, leaving each zeroed lane at its own
+// position, and lowerVECTOR_SHUFFLEAsPPair then forms the PPAIRE. Undef lanes
+// always match.
+static bool isPackedZExtShuffleMask(ArrayRef<int> Mask) {
+ unsigned NumElts = Mask.size();
+ if (NumElts % 2 != 0)
+ return false;
+ for (unsigned I = 0; I != NumElts / 2; ++I)
+ if ((Mask[2 * I] >= 0 && Mask[2 * I] != (int)(2 * I)) ||
+ (Mask[2 * I + 1] >= 0 && Mask[2 * I + 1] < (int)NumElts))
+ return false;
+ return true;
+}
+
// Match a legalized deinterleave shuffle on two RV32 vector halves and lower
// it to an RV32 P narrowing shift on the concatenated source.
static SDValue
@@ -6509,16 +6527,25 @@ static SDValue lowerVECTOR_SHUFFLEAsPPair(ShuffleVectorSDNode *SVN,
if (V2.isUndef())
return SDValue();
- // Match <start, N+start, start+2, N+start+2, ...>: each widened element of
- // V1/V2 contributes its low (start=0, ppaire) or high (start=1, ppairo) byte.
+ // A splat operand's lanes are all equal, so a lane selecting from it matches
+ // any of its positions. This covers the zero operand XformToShuffleWithZero
+ // forms for a packed zero-extend, which keeps each zeroed lane at its own
+ // position rather than the strided one.
+ bool V1IsSplat = DAG.isSplatValue(V1);
+ bool V2IsSplat = DAG.isSplatValue(V2);
+
+ // Match <start, N+start, start+2, N+start+2, ...>: even lanes come from V1
+ // and odd lanes from V2 (start=0, ppaire) or vice versa (start=1, ppairo).
// Trailing lanes may be undef when a 4-byte source was widened to v8i8.
auto IsStrided = [&](unsigned Start) {
for (unsigned I = 0; I != NumElts / 2; ++I) {
int M0 = Mask[2 * I];
int M1 = Mask[2 * I + 1];
- if (M0 < 0 && M1 < 0)
- continue;
- if (M0 != (int)(Start + 2 * I) || M1 != (int)(NumElts + Start + 2 * I))
+ if (M0 >= 0 &&
+ (V1IsSplat ? M0 >= (int)NumElts : M0 != (int)(Start + 2 * I)))
+ return false;
+ if (M1 >= 0 && (V2IsSplat ? M1 < (int)NumElts
+ : M1 != (int)(NumElts + Start + 2 * I)))
return false;
}
return true;
@@ -7218,6 +7245,20 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V2, V1);
}
+bool RISCVTargetLowering::isVectorClearMaskLegal(ArrayRef<int> M,
+ EVT VT) const {
+ // Enable DAGCombiner::XformToShuffleWithZero to rewrite a packed zero-extend
+ // `and` into shuffle(src, zero, ...), which lowerVECTOR_SHUFFLE turns into
+ // RISCVISD::PPAIRE. Accept the packed byte/halfword views that lowering
+ // handles; the 32-bit views are illegal on RV64 but reachable before type
+ // legalization widens them to the legal 64-bit view.
+ if (!Subtarget.hasStdExtP() || !VT.isSimple())
+ return false;
+ MVT SVT = VT.getSimpleVT();
+ return (SVT == MVT::v4i8 || SVT == MVT::v8i8 || SVT == MVT::v4i16) &&
+ isPackedZExtShuffleMask(M);
+}
+
bool RISCVTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
// Only support legal VTs for other shuffles for now.
if (!isTypeLegal(VT) || !Subtarget.hasVInstructions())
@@ -11976,6 +12017,19 @@ static unsigned getRVPShiftOpcode(Intrinsic::ID IntNo) {
}
}
+static SDValue lowerPZExt(SDValue Src, const SDLoc &DL, SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget) {
+ MVT VT = Src.getSimpleValueType();
+ MVT PPairVT =
+ MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() / 2),
+ VT.getVectorNumElements() * 2);
+ Src = DAG.getBitcast(PPairVT, Src);
+ SDValue Zero = DAG.getNode(ISD::SPLAT_VECTOR, DL, PPairVT,
+ DAG.getConstant(0, DL, Subtarget.getXLenVT()));
+ SDValue Res = DAG.getNode(RISCVISD::PPAIRE, DL, PPairVT, Src, Zero);
+ return DAG.getBitcast(VT, Res);
+}
+
SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
unsigned IntNo = Op.getConstantOperandVal(0);
@@ -12153,6 +12207,35 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(getRVPShiftOpcode(IntNo), DL, Op.getValueType(),
Op.getOperand(1), ShAmt);
}
+ case Intrinsic::riscv_psext_b:
+ case Intrinsic::riscv_psext_h: {
+ EVT VT = Op.getValueType();
+ if (!VT.isSimple() || !Subtarget.isPExtPackedType(VT.getSimpleVT()))
+ reportFatalUsageError("unsupported llvm.riscv.psext intrinsic");
+
+ MVT SimpleVT = VT.getSimpleVT();
+ unsigned SrcEltBits = IntNo == Intrinsic::riscv_psext_b ? 8 : 16;
+ if (SrcEltBits >= SimpleVT.getScalarSizeInBits())
+ reportFatalUsageError("unsupported llvm.riscv.psext intrinsic");
+
+ MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltBits),
+ SimpleVT.getVectorElementCount());
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SimpleVT, Op.getOperand(1),
+ DAG.getValueType(ExtVT));
+ }
+ case Intrinsic::riscv_pzext_b:
+ case Intrinsic::riscv_pzext_h: {
+ EVT VT = Op.getValueType();
+ if (!VT.isSimple() || !Subtarget.isPExtPackedType(VT.getSimpleVT()))
+ reportFatalUsageError("unsupported llvm.riscv.pzext intrinsic");
+
+ MVT SimpleVT = VT.getSimpleVT();
+ unsigned SrcEltBits = IntNo == Intrinsic::riscv_pzext_b ? 8 : 16;
+ if (SimpleVT.getScalarSizeInBits() != SrcEltBits * 2)
+ reportFatalUsageError("unsupported llvm.riscv.pzext intrinsic");
+
+ return lowerPZExt(Op.getOperand(1), DL, DAG, Subtarget);
+ }
case Intrinsic::riscv_pabdsumu:
case Intrinsic::riscv_pabdsumau: {
// On RV32 an i32-result absolute
diff erence sum over a 64-bit (GPRPair)
@@ -16223,6 +16306,31 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
return;
}
+ case Intrinsic::riscv_psext_h:
+ reportFatalUsageError("unsupported llvm.riscv.psext intrinsic");
+ case Intrinsic::riscv_pzext_h:
+ reportFatalUsageError("unsupported llvm.riscv.pzext intrinsic");
+ case Intrinsic::riscv_psext_b:
+ case Intrinsic::riscv_pzext_b: {
+ bool IsSExt = IntNo == Intrinsic::riscv_psext_b;
+ const char *UnsupportedMsg =
+ IsSExt ? "unsupported llvm.riscv.psext intrinsic"
+ : "unsupported llvm.riscv.pzext intrinsic";
+ EVT VT = N->getValueType(0);
+ if (!Subtarget.is64Bit() || VT != MVT::v2i16)
+ reportFatalUsageError(UnsupportedMsg);
+
+ SDValue Src = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i16,
+ N->getOperand(1), DAG.getUNDEF(VT));
+ SDValue Res;
+ if (IsSExt)
+ Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::v4i16, Src,
+ DAG.getValueType(MVT::v4i8));
+ else
+ Res = lowerPZExt(Src, DL, DAG, Subtarget);
+ Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0));
+ return;
+ }
case Intrinsic::riscv_paadd:
case Intrinsic::riscv_paaddu:
case Intrinsic::riscv_pasub:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index f8a99d38e2691..2ca7c392639f7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -100,6 +100,8 @@ class RISCVTargetLowering : public TargetLowering {
/// should be stack expanded.
bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
+ bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override;
+
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
// If the pair to store is a mixture of float and int values, we will
// save two bitwise instructions and one float-to-int instruction and
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 38900e2100bf9..f4798d0a6424c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2530,6 +2530,15 @@ let append Predicates = [IsRV32] in {
def : PatGprPair<riscv_psabs, PSABS_DB, v8i8>;
def : PatGprPair<riscv_psabs, PSABS_DH, v4i16>;
+ // Packed sign extend patterns
+ // Sign extend inreg patterns using psext. sext_invec is lowered to
+ // zext_invec+sext_inreg.
+ def : Pat<(v2i16 (sext_inreg GPR:$rs1, v2i8)), (PSEXT_H_B GPR:$rs1)>;
+ def : Pat<(v4i16 (sext_inreg GPRPair:$rs1, v4i8)), (PSEXT_DH_B GPRPair:$rs1)>;
+ def : Pat<(v2i32 (sext_inreg GPRPair:$rs1, v2i8)), (PSEXT_DW_B GPRPair:$rs1)>;
+ def : Pat<(v2i32 (sext_inreg GPRPair:$rs1, v2i16)),
+ (PSEXT_DW_H GPRPair:$rs1)>;
+
// 16-bit bswap patterns
def : Pat<(v4i16 (bswap GPRPair:$rs)),
(PPAIROE_DB GPRPair:$rs, GPRPair:$rs)>;
@@ -2766,6 +2775,13 @@ let append Predicates = [IsRV64] in {
def : Pat<(v2i32 (vselect (v2i32 GPR:$mask), GPR:$true_v, GPR:$false_v)),
(MERGE GPR:$mask, GPR:$false_v, GPR:$true_v)>;
+ // Packed sign extend patterns
+ // Sign extend inreg patterns using psext. sext_invec is lowered to
+ // zext_invec+sext_inreg.
+ def : Pat<(v4i16 (sext_inreg GPR:$rs1, v4i8)), (PSEXT_H_B GPR:$rs1)>;
+ def : Pat<(v2i32 (sext_inreg GPR:$rs1, v2i8)), (PSEXT_W_B GPR:$rs1)>;
+ def : Pat<(v2i32 (sext_inreg GPR:$rs1, v2i16)), (PSEXT_W_H GPR:$rs1)>;
+
// 32-bit bswap patterns
def : Pat<(v2i32 (bswap GPR:$rs)),
(PPAIROE_W (REV8_RV64 GPR:$rs), (REV8_RV64 GPR:$rs))>;
@@ -2862,10 +2878,5 @@ let append Predicates = [IsRV64] in {
(PPAIRE_H GPR:$rs1, GPR:$rs2)>;
def : Pat<(v4i16 (riscv_ppairo (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
(PPAIRO_H GPR:$rs1, GPR:$rs2)>;
-
- // Sign extend inreg patterns using psext. sext_invec is lowered to
- // zext_invec+sext_inreg.
- def : Pat<(v4i16 (sext_inreg GPR:$rs1, v4i8)), (PSEXT_H_B GPR:$rs1)>;
- def : Pat<(v2i32 (sext_inreg GPR:$rs1, v2i16)), (PSEXT_W_H GPR:$rs1)>;
} // append Predicates = [IsRV64]
} // Predicates = [HasStdExtP]
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 8cd7d29dbf7c3..cb9a4c91a950c 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -2671,6 +2671,44 @@ define <2 x i16> @test_pmerge_mvmn_i16x2(<2 x i16> %rs2, <2 x i16> %rs1, <2 x i1
ret <2 x i16> %res
}
+; Packed sign and zero extend
+define <2 x i16> @test_psext_b_v2i16(<2 x i16> %a) {
+; CHECK-LABEL: test_psext_b_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psext.h.b a0, a0
+; CHECK-NEXT: ret
+ %shl = shl <2 x i16> %a, splat (i16 8)
+ %res = ashr <2 x i16> %shl, splat (i16 8)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pzext_b_v2i16(<2 x i16> %a) {
+; CHECK-LABEL: test_pzext_b_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pzext.h.b a0, a0
+; CHECK-NEXT: ret
+ %res = and <2 x i16> %a, splat (i16 255)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_riscv_psext_b_v2i16(<2 x i16> %a) {
+; CHECK-LABEL: test_riscv_psext_b_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psext.h.b a0, a0
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.psext.b.v2i16(<2 x i16> %a)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_riscv_pzext_b_v2i16(<2 x i16> %a) {
+; CHECK-LABEL: test_riscv_pzext_b_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pzext.h.b a0, a0
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pzext.b.v2i16(<2 x i16> %a)
+ ret <2 x i16> %res
+}
+
; Packed absolute
diff erence sum
define i32 @test_pabdsumu_u8x4_u32(<4 x i8> %a, <4 x i8> %b) {
; RV32-LABEL: test_pabdsumu_u8x4_u32:
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 3088f49a27396..d92d93737a426 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -5838,6 +5838,150 @@ define <2 x i32> @test_pmerge_mvmn_i32x2(<2 x i32> %rs2, <2 x i32> %rs1, <2 x i3
ret <2 x i32> %res
}
+; Packed sign and zero extend
+define <4 x i16> @test_psext_b_v4i16(<4 x i16> %a) {
+; RV32-LABEL: test_psext_b_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: psext.dh.b a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psext_b_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: psext.h.b a0, a0
+; RV64-NEXT: ret
+ %shl = shl <4 x i16> %a, splat (i16 8)
+ %res = ashr <4 x i16> %shl, splat (i16 8)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_psext_b_v2i32(<2 x i32> %a) {
+; RV32-LABEL: test_psext_b_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: psext.dw.b a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psext_b_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: psext.w.b a0, a0
+; RV64-NEXT: ret
+ %shl = shl <2 x i32> %a, splat (i32 24)
+ %res = ashr <2 x i32> %shl, splat (i32 24)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_psext_h_v2i32(<2 x i32> %a) {
+; RV32-LABEL: test_psext_h_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: psext.dw.h a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psext_h_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: psext.w.h a0, a0
+; RV64-NEXT: ret
+ %shl = shl <2 x i32> %a, splat (i32 16)
+ %res = ashr <2 x i32> %shl, splat (i32 16)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_pzext_b_v4i16(<4 x i16> %a) {
+; RV32-LABEL: test_pzext_b_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pzext.dh.b a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pzext_b_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pzext.h.b a0, a0
+; RV64-NEXT: ret
+ %res = and <4 x i16> %a, splat (i16 255)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_pzext_h_v2i32(<2 x i32> %a) {
+; RV32-LABEL: test_pzext_h_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: pzext.dw.h a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pzext_h_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pzext.w.h a0, a0
+; RV64-NEXT: ret
+ %res = and <2 x i32> %a, splat (i32 65535)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_riscv_psext_b_v4i16(<4 x i16> %a) {
+; RV32-LABEL: test_riscv_psext_b_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: psext.dh.b a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_riscv_psext_b_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: psext.h.b a0, a0
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.psext.b.v4i16(<4 x i16> %a)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_riscv_psext_b_v2i32(<2 x i32> %a) {
+; RV32-LABEL: test_riscv_psext_b_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: psext.dw.b a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_riscv_psext_b_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: psext.w.b a0, a0
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psext.b.v2i32(<2 x i32> %a)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_riscv_psext_h_v2i32(<2 x i32> %a) {
+; RV32-LABEL: test_riscv_psext_h_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: psext.dw.h a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_riscv_psext_h_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: psext.w.h a0, a0
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psext.h.v2i32(<2 x i32> %a)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_riscv_pzext_b_v4i16(<4 x i16> %a) {
+; RV32-LABEL: test_riscv_pzext_b_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pzext.dh.b a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_riscv_pzext_b_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pzext.h.b a0, a0
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pzext.b.v4i16(<4 x i16> %a)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_riscv_pzext_h_v2i32(<2 x i32> %a) {
+; RV32-LABEL: test_riscv_pzext_h_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: pzext.dw.h a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_riscv_pzext_h_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pzext.w.h a0, a0
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pzext.h.v2i32(<2 x i32> %a)
+ ret <2 x i32> %res
+}
+
; Packed absolute
diff erence sum
define i32 @test_pabdsumu_u8x8_u32(<8 x i8> %a, <8 x i8> %b) {
; RV32-LABEL: test_pabdsumu_u8x8_u32:
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-intrinsic-invalid.ll b/llvm/test/CodeGen/RISCV/rvp-simd-intrinsic-invalid.ll
new file mode 100644
index 0000000000000..28b1d7c53a6e7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-intrinsic-invalid.ll
@@ -0,0 +1,39 @@
+; RUN: sed -n '/^; BEGIN-PSEXT-LEGAL$/,/^; END-PSEXT-LEGAL$/p' %s \
+; RUN: | not llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
+; RUN: -o /dev/null 2>&1 | FileCheck %s --check-prefix=PSEXT
+; RUN: sed -n '/^; BEGIN-PSEXT-WIDEN$/,/^; END-PSEXT-WIDEN$/p' %s \
+; RUN: | not llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
+; RUN: -o /dev/null 2>&1 | FileCheck %s --check-prefix=PSEXT
+; RUN: sed -n '/^; BEGIN-PZEXT$/,/^; END-PZEXT$/p' %s \
+; RUN: | not llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
+; RUN: -o /dev/null 2>&1 | FileCheck %s --check-prefix=PZEXT
+
+; PSEXT: LLVM ERROR: unsupported llvm.riscv.psext intrinsic
+; PZEXT: LLVM ERROR: unsupported llvm.riscv.pzext intrinsic
+
+; BEGIN-PSEXT-LEGAL
+define <4 x i16> @bad_psext_legal_type(<4 x i16> %a) {
+ %res = call <4 x i16> @llvm.riscv.psext.h.v4i16(<4 x i16> %a)
+ ret <4 x i16> %res
+}
+
+declare <4 x i16> @llvm.riscv.psext.h.v4i16(<4 x i16>)
+; END-PSEXT-LEGAL
+
+; BEGIN-PSEXT-WIDEN
+define <2 x i16> @bad_psext_widen_type(<2 x i16> %a) {
+ %res = call <2 x i16> @llvm.riscv.psext.h.v2i16(<2 x i16> %a)
+ ret <2 x i16> %res
+}
+
+declare <2 x i16> @llvm.riscv.psext.h.v2i16(<2 x i16>)
+; END-PSEXT-WIDEN
+
+; BEGIN-PZEXT
+define <2 x i32> @bad_pzext(<2 x i32> %a) {
+ %res = call <2 x i32> @llvm.riscv.pzext.b.v2i32(<2 x i32> %a)
+ ret <2 x i32> %res
+}
+
+declare <2 x i32> @llvm.riscv.pzext.b.v2i32(<2 x i32>)
+; END-PZEXT
More information about the llvm-commits
mailing list