[llvm] [VPlan] Compute blend masks from minimum set of edge masks (PR #201783)

[Luke Lau via llvm-commits]

================
@@ -1145,14 +1146,16 @@ define float @reduction_conditional(ptr %A, ptr %B, ptr %C, float %S) {
 ; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = select <4 x i1> [[TMP6]], <4 x i1> [[TMP8]], <4 x i1> zeroinitializer
 ; CHECK-INTERLEAVED-NEXT:    [[TMP17:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[WIDE_LOAD]]
 ; CHECK-INTERLEAVED-NEXT:    [[TMP18:%.*]] = fadd fast <4 x float> [[VEC_PHI1]], [[WIDE_LOAD2]]
+; CHECK-INTERLEAVED-NEXT:    [[TMP27:%.*]] = xor <4 x i1> [[TMP5]], splat (i1 true)
+; CHECK-INTERLEAVED-NEXT:    [[TMP28:%.*]] = xor <4 x i1> [[TMP6]], splat (i1 true)
 ; CHECK-INTERLEAVED-NEXT:    [[TMP20:%.*]] = select <4 x i1> [[TMP19]], <4 x i1> [[TMP11]], <4 x i1> zeroinitializer
 ; CHECK-INTERLEAVED-NEXT:    [[TMP22:%.*]] = select <4 x i1> [[TMP21]], <4 x i1> [[TMP12]], <4 x i1> zeroinitializer
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI:%.*]] = select <4 x i1> [[TMP20]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP13]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI5:%.*]] = select <4 x i1> [[TMP15]], <4 x float> [[TMP17]], <4 x float> [[PREDPHI]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI6]] = select <4 x i1> [[TMP5]], <4 x float> [[PREDPHI5]], <4 x float> [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI7:%.*]] = select <4 x i1> [[TMP22]], <4 x float> [[VEC_PHI1]], <4 x float> [[TMP14]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI8:%.*]] = select <4 x i1> [[TMP16]], <4 x float> [[TMP18]], <4 x float> [[PREDPHI7]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI9]] = select <4 x i1> [[TMP6]], <4 x float> [[PREDPHI8]], <4 x float> [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT:    [[TMP25:%.*]] = or <4 x i1> [[TMP20]], [[TMP27]]
+; CHECK-INTERLEAVED-NEXT:    [[TMP26:%.*]] = or <4 x i1> [[TMP22]], [[TMP28]]
+; CHECK-INTERLEAVED-NEXT:    [[PREDPHI:%.*]] = select <4 x i1> [[TMP25]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP13]]
----------------
lukel97 wrote:

Double checked the test-suite diffs there, they all seem to be improvements, mostly on TSVC, e.g.

```diff
--- build.armv9-a-O3-base/MultiSource/Benchmarks/TSVC/ControlFlow-dbl/CMakeFiles/ControlFlow-dbl.dir/tsc.s	2026-07-23 04:32:57.798801819 +0000
+++ build.armv9-a-O3-head/MultiSource/Benchmarks/TSVC/ControlFlow-dbl/CMakeFiles/ControlFlow-dbl.dir/tsc.s	2026-07-23 04:17:36.704060642 +0000
@@ -11344,37 +11344,35 @@
 	ldr	z0, [x12]
 	decd	x13
 	fcmgt	p0.d, p4/z, z0.d, #0.0
-	not	p2.b, p4/z, p0.b
-	ld1d	{ z1.d }, p2/z, [x11]
-	ld1d	{ z2.d }, p2/z, [x10]
+	not	p1.b, p4/z, p0.b
+	ld1d	{ z1.d }, p1/z, [x11]
+	ld1d	{ z2.d }, p1/z, [x10]
 	fnmls	z1.d, p4/m, z2.d, z2.d
-	fcmge	p3.d, p4/z, z0.d, z1.d
-	st1d	{ z1.d }, p2, [x11]
-	bic	p1.b, p2/z, p2.b, p3.b
-	not	p2.b, p4/z, p3.b
-	ld1d	{ z0.d }, p1/z, [x8]
-	ld1d	{ z3.d }, p1/z, [x9]
-	mov	p2.b, p0/m, p0.b
+	fcmge	p2.d, p4/z, z0.d, z1.d
+	st1d	{ z1.d }, p1, [x11]
+	bic	p3.b, p1/z, p1.b, p2.b
+	not	p1.b, p4/z, p2.b
+	ld1d	{ z0.d }, p3/z, [x8]
+	ld1d	{ z3.d }, p3/z, [x9]
+	mov	p1.b, p0/m, p0.b
 	fmad	z0.d, p4/m, z2.d, z3.d
-	not	p2.b, p4/z, p2.b
-	ld1d	{ z3.d }, p2/z, [x9]
-	st1d	{ z0.d }, p1, [x9]
+	not	p1.b, p4/z, p1.b
+	ld1d	{ z3.d }, p1/z, [x9]
+	st1d	{ z0.d }, p3, [x9]
 	ld1d	{ z4.d }, p0/z, [x9]
 	ld1d	{ z5.d }, p0/z, [x8]
-	mov	z0.d, p3/m, z3.d
+	mov	z0.d, p2/m, z3.d
 	incb	x8
 	fnmls	z4.d, p4/m, z5.d, z5.d
 	st1d	{ z4.d }, p0, [x9]
 	mov	z0.d, p0/m, z4.d
 	incb	x9
-	ld1d	{ z5.d }, p0/z, [x10]
-	ld1d	{ z6.d }, p0/z, [x11]
+	ld1d	{ z3.d }, p0/z, [x10]
+	ld1d	{ z5.d }, p0/z, [x11]
 	incb	x10
 	incb	x11
-	sel	z3.d, p0, z5.d, z2.d
-	sel	z5.d, p0, z6.d, z1.d
-	sel	z2.d, p1, z2.d, z3.d
-	sel	z1.d, p1, z1.d, z5.d
+	mov	z2.d, p0/m, z3.d
+	mov	z1.d, p0/m, z5.d
 	fmad	z0.d, p4/m, z2.d, z1.d
 	str	z0, [x12]
 	incb	x12
```

https://github.com/llvm/llvm-project/pull/201783