[llvm] [AMDGPU] Using feature to define vmem cacheline size (PR #207884)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 22 21:51:56 PDT 2026
https://github.com/Shoreshen updated https://github.com/llvm/llvm-project/pull/207884
>From 53223cd02925ea6f39c26cdc973fd875b45659da Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Wed, 8 Jul 2026 07:36:45 +0800
Subject: [PATCH 1/6] [AMDGPU] Define VMEM cache line size via subtarget
feature
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 22 +-
.../AMDGPU/AMDGPUTargetTransformInfo.cpp | 4 +
.../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 2 +-
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 7 +
.../LoopDataPrefetch/AMDGPU/lit.local.cfg | 4 +
.../AMDGPU/vmem-cache-line-size.ll | 213 ++++++++++++++++++
6 files changed, 247 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/Transforms/LoopDataPrefetch/AMDGPU/lit.local.cfg
create mode 100644 llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 9da123c517b81..84ebd50ce4edc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -409,6 +409,15 @@ class SubtargetFeatureInstCacheLineSize <int Value> : SubtargetFeature <
def FeatureInstCacheLineSize64 : SubtargetFeatureInstCacheLineSize<64>;
def FeatureInstCacheLineSize128 : SubtargetFeatureInstCacheLineSize<128>;
+class SubtargetFeatureDataCacheLineSize <int Value> : SubtargetFeature <
+ "datacachelinesize"#Value,
+ "DataCacheLineSize",
+ !cast<string>(Value),
+ "Data (VMEM) cache line size in bytes."
+>;
+
+def FeatureDataCacheLineSize128 : SubtargetFeatureDataCacheLineSize<128>;
+
defm GCN3Encoding : AMDGPUSubtargetFeature<"gcn3-encoding",
"Encoding format for VI",
/*GenPredicate=*/0
@@ -2149,6 +2158,7 @@ def FeatureISAVersion12 : FeatureSet<
FeatureRealTrue16Insts,
FeatureMTBUFInsts,
FeatureFormattedMUBUFInsts,
+ FeatureDataCacheLineSize128
]>;
def FeatureISAVersion12_50_Common : FeatureSet<
@@ -2253,7 +2263,8 @@ def FeatureISAVersion12_50 : FeatureSet<
FeatureSWMMACGfx1200Insts,
FeatureSWMMACGfx1250Insts,
FeatureTransCoexecutionHazard,
- FeatureWMMACoexecutionHazards])>;
+ FeatureWMMACoexecutionHazards,
+ FeatureDataCacheLineSize128])>;
def FeatureISAVersion12_51 : FeatureSet<
!listconcat(FeatureISAVersion12_50_Common.Features,
@@ -2279,11 +2290,13 @@ def FeatureISAVersion12_51 : FeatureSet<
FeatureSWMMACGfx1250Insts,
FeatureUseAddPC64Inst,
FeatureTransCoexecutionHazard,
- FeatureWMMACoexecutionHazards])>;
+ FeatureWMMACoexecutionHazards,
+ FeatureDataCacheLineSize128])>;
def FeatureISAVersion12_Generic: FeatureSet<
!listconcat(FeatureISAVersion12.Features,
- [FeatureRequiresCOV6])>;
+ [FeatureDataCacheLineSize128,
+ FeatureRequiresCOV6])>;
def FeatureISAVersion12_5_Generic: FeatureSet<
!listconcat(FeatureISAVersion12_50_Common.Features,
@@ -2293,7 +2306,8 @@ def FeatureISAVersion12_5_Generic: FeatureSet<
FeatureSupportsXNACK,
FeatureGFX125xLowestRateWMMA,
FeatureTransCoexecutionHazard,
- FeatureWMMACoexecutionHazards])>;
+ FeatureWMMACoexecutionHazards,
+ FeatureDataCacheLineSize128])>;
def FeatureISAVersion13 : FeatureSet<
[FeatureGFX13,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 5125735faddd6..6f685c40c833a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -1746,6 +1746,10 @@ GCNTTIImpl::getTypeLegalizationCost(Type *Ty) const {
return Cost;
}
+unsigned GCNTTIImpl::getCacheLineSize() const {
+ return ST->getDataCacheLineSize();
+}
+
unsigned GCNTTIImpl::getPrefetchDistance() const {
return ST->hasPrefetch() ? 128 : 0;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index e20ef3f7524a6..df7b6d339e6c2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -290,7 +290,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
TTI::TargetCostKind CostKind) const override;
/// Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.
- unsigned getCacheLineSize() const override { return 128; }
+ unsigned getCacheLineSize() const override;
/// How much before a load we should place the prefetch instruction.
/// This is currently measured in number of IR instructions.
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 7e4d9bd20cb2f..1bf0a53234777 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -80,6 +80,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
// Instruction cache line size in bytes; set from TableGen subtarget features.
unsigned InstCacheLineSize = 0;
+ // Data (VMEM) cache line size in bytes; set from TableGen subtarget features.
+ unsigned DataCacheLineSize = 0;
+
// Dynamically set bits that enable features.
bool DynamicVGPR = false;
bool DynamicVGPRBlockSize32 = false;
@@ -197,6 +200,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
/// Instruction cache line size in bytes (64 for pre-GFX11, 128 for GFX11+).
unsigned getInstCacheLineSize() const { return InstCacheLineSize; }
+ /// Data (VMEM) cache line size in bytes (128 for gfx12), has no use before
+ /// GFX12.
+ unsigned getDataCacheLineSize() const { return DataCacheLineSize; }
+
unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {
return (ForBufferRSrc || !hasFlatScratchEnabled()) ? MaxPrivateElementSize
: 16;
diff --git a/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/lit.local.cfg b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/lit.local.cfg
new file mode 100644
index 0000000000000..62c2904960cbe
--- /dev/null
+++ b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/lit.local.cfg
@@ -0,0 +1,4 @@
+config.suffixes = [".ll"]
+
+if not "AMDGPU" in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
new file mode 100644
index 0000000000000..047872cbd8cde
--- /dev/null
+++ b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
@@ -0,0 +1,213 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -mtriple=amdgcn -mcpu=gfx1250 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX12,GFX1250
+; RUN: opt -mtriple=amdgcn -mcpu=gfx1251 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX12,GFX1251
+; RUN: opt -mtriple=amdgcn -mcpu=gfx1100 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1100
+
+define amdgpu_kernel void @prefetch_two_streams_80B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
+; GFX12-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
+; GFX12-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; GFX12-NEXT: [[ENTRY:.*]]:
+; GFX12-NEXT: br label %[[FOR_BODY:.*]]
+; GFX12: [[FOR_BODY]]:
+; GFX12-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX12-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX12-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 28
+; GFX12-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
+; GFX12-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
+; GFX12-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX12-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 20
+; GFX12-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX12-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX12-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX12-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX12-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX12-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX12-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX12-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX12: [[FOR_END]]:
+; GFX12-NEXT: ret void
+;
+; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
+; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; GFX1100-NEXT: [[ENTRY:.*]]:
+; GFX1100-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1100: [[FOR_BODY]]:
+; GFX1100-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1100-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1100-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1100-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 20
+; GFX1100-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1100-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1100-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1100-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1100-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1100-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1100-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1100-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1100: [[FOR_END]]:
+; GFX1100-NEXT: ret void
+;
+entry:
+ br label %for.body
+
+for.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %idx0 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv
+ %v0 = load i32, ptr addrspace(1) %idx0, align 4
+ %iv.off = add i64 %iv, 20
+ %idx1 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv.off
+ %v1 = load i32, ptr addrspace(1) %idx1, align 4
+ %sum = add i32 %v0, %v1
+ %sidx = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %iv
+ store i32 %sum, ptr addrspace(1) %sidx, align 4
+ %iv.next = add nuw nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, %n
+ br i1 %ec, label %for.end, label %for.body
+
+for.end:
+ ret void
+}
+
+define amdgpu_kernel void @prefetch_two_streams_160B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
+; GFX12-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
+; GFX12-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; GFX12-NEXT: [[ENTRY:.*]]:
+; GFX12-NEXT: br label %[[FOR_BODY:.*]]
+; GFX12: [[FOR_BODY]]:
+; GFX12-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX12-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX12-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 188
+; GFX12-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
+; GFX12-NEXT: [[TMP2:%.*]] = shl i64 [[IV]], 2
+; GFX12-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 28
+; GFX12-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
+; GFX12-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
+; GFX12-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX12-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 40
+; GFX12-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
+; GFX12-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX12-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX12-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX12-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX12-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX12-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX12-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX12: [[FOR_END]]:
+; GFX12-NEXT: ret void
+;
+; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
+; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; GFX1100-NEXT: [[ENTRY:.*]]:
+; GFX1100-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1100: [[FOR_BODY]]:
+; GFX1100-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1100-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1100-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1100-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 40
+; GFX1100-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1100-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1100-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1100-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1100-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1100-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1100-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1100-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1100: [[FOR_END]]:
+; GFX1100-NEXT: ret void
+;
+entry:
+ br label %for.body
+
+for.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %idx0 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv
+ %v0 = load i32, ptr addrspace(1) %idx0, align 4
+ %iv.off = add i64 %iv, 40
+ %idx1 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv.off
+ %v1 = load i32, ptr addrspace(1) %idx1, align 4
+ %sum = add i32 %v0, %v1
+ %sidx = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %iv
+ store i32 %sum, ptr addrspace(1) %sidx, align 4
+ %iv.next = add nuw nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, %n
+ br i1 %ec, label %for.end, label %for.body
+
+for.end:
+ ret void
+}
+
+define amdgpu_kernel void @prefetch_two_streams_320B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
+; GFX12-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
+; GFX12-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; GFX12-NEXT: [[ENTRY:.*]]:
+; GFX12-NEXT: br label %[[FOR_BODY:.*]]
+; GFX12: [[FOR_BODY]]:
+; GFX12-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX12-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX12-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 348
+; GFX12-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
+; GFX12-NEXT: [[TMP2:%.*]] = shl i64 [[IV]], 2
+; GFX12-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 28
+; GFX12-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
+; GFX12-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
+; GFX12-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX12-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 80
+; GFX12-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
+; GFX12-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX12-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX12-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX12-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX12-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX12-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX12-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX12: [[FOR_END]]:
+; GFX12-NEXT: ret void
+;
+; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
+; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; GFX1100-NEXT: [[ENTRY:.*]]:
+; GFX1100-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1100: [[FOR_BODY]]:
+; GFX1100-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1100-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1100-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1100-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 80
+; GFX1100-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1100-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1100-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1100-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1100-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1100-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1100-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1100-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1100: [[FOR_END]]:
+; GFX1100-NEXT: ret void
+;
+entry:
+ br label %for.body
+
+for.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %idx0 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv
+ %v0 = load i32, ptr addrspace(1) %idx0, align 4
+ %iv.off = add i64 %iv, 80
+ %idx1 = getelementptr inbounds i32, ptr addrspace(1) %b, i64 %iv.off
+ %v1 = load i32, ptr addrspace(1) %idx1, align 4
+ %sum = add i32 %v0, %v1
+ %sidx = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %iv
+ store i32 %sum, ptr addrspace(1) %sidx, align 4
+ %iv.next = add nuw nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, %n
+ br i1 %ec, label %for.end, label %for.body
+
+for.end:
+ ret void
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1250: {{.*}}
+; GFX1251: {{.*}}
>From 48a6606a5e4699ebdaa553eec00f93348a822221 Mon Sep 17 00:00:00 2001
From: shore <shorshen at amd.com>
Date: Fri, 17 Jul 2026 17:24:21 +0800
Subject: [PATCH 2/6] fix comments
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 12 +-
.../AMDGPU/vmem-cache-line-size.ll | 229 +++++++++++-------
2 files changed, 149 insertions(+), 92 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index ffde380e99154..fedb95231acbd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -414,7 +414,7 @@ class SubtargetFeatureDataCacheLineSize <int Value> : SubtargetFeature <
"Data (VMEM) cache line size in bytes."
>;
-def FeatureDataCacheLineSize128 : SubtargetFeatureDataCacheLineSize<128>;
+def FeatureCanPrefetchData128 : SubtargetFeatureDataCacheLineSize<128>;
defm GCN3Encoding : AMDGPUSubtargetFeature<"gcn3-encoding",
"Encoding format for VI",
@@ -2172,7 +2172,7 @@ def FeatureISAVersion12 : FeatureSet<
FeatureRealTrue16Insts,
FeatureMTBUFInsts,
FeatureFormattedMUBUFInsts,
- FeatureDataCacheLineSize128
+ FeatureCanPrefetchData128
]>;
def FeatureISAVersion12_50_Common : FeatureSet<
@@ -2279,7 +2279,7 @@ def FeatureISAVersion12_50 : FeatureSet<
FeatureSWMMACGfx1250Insts,
FeatureTransCoexecutionHazard,
FeatureWMMACoexecutionHazards,
- FeatureDataCacheLineSize128,
+ FeatureCanPrefetchData128,
FeatureRequiresInitialUnclausedVmem,
])>;
@@ -2308,13 +2308,13 @@ def FeatureISAVersion12_51 : FeatureSet<
FeatureUseAddPC64Inst,
FeatureTransCoexecutionHazard,
FeatureWMMACoexecutionHazards,
- FeatureDataCacheLineSize128,
+ FeatureCanPrefetchData128,
FeatureRequiresInitialUnclausedVmem,
])>;
def FeatureISAVersion12_Generic: FeatureSet<
!listconcat(FeatureISAVersion12.Features,
- [FeatureDataCacheLineSize128,
+ [FeatureCanPrefetchData128,
FeatureRequiresCOV6])>;
def FeatureISAVersion12_5_Generic: FeatureSet<
@@ -2326,7 +2326,7 @@ def FeatureISAVersion12_5_Generic: FeatureSet<
FeatureGFX125xLowestRateWMMA,
FeatureTransCoexecutionHazard,
FeatureWMMACoexecutionHazards,
- FeatureDataCacheLineSize128,
+ FeatureCanPrefetchData128,
FeatureRequiresInitialUnclausedVmem,
])>;
diff --git a/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
index 047872cbd8cde..fda4f77150634 100644
--- a/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
+++ b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
@@ -1,35 +1,55 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -mtriple=amdgcn -mcpu=gfx1250 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX12,GFX1250
-; RUN: opt -mtriple=amdgcn -mcpu=gfx1251 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX12,GFX1251
-; RUN: opt -mtriple=amdgcn -mcpu=gfx1100 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1100
+; RUN: opt -mtriple=amdgpu12.50 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1250
+; RUN: opt -mtriple=amdgpu12.00 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1200
+; RUN: opt -mtriple=amdgpu11.00 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1100
define amdgpu_kernel void @prefetch_two_streams_80B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
-; GFX12-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
-; GFX12-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
-; GFX12-NEXT: [[ENTRY:.*]]:
-; GFX12-NEXT: br label %[[FOR_BODY:.*]]
-; GFX12: [[FOR_BODY]]:
-; GFX12-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
-; GFX12-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
-; GFX12-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 28
-; GFX12-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
-; GFX12-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
-; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
-; GFX12-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
-; GFX12-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 20
-; GFX12-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
-; GFX12-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
-; GFX12-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
-; GFX12-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
-; GFX12-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
-; GFX12-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; GFX12-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; GFX12-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
-; GFX12: [[FOR_END]]:
-; GFX12-NEXT: ret void
+; GFX1250-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
+; GFX1250-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
+; GFX1250-NEXT: [[ENTRY:.*]]:
+; GFX1250-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1250: [[FOR_BODY]]:
+; GFX1250-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1250-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX1250-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 28
+; GFX1250-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
+; GFX1250-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1250-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
+; GFX1250-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1250-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 20
+; GFX1250-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1250-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1250-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1250-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1250-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1250-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1250-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1250-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1250: [[FOR_END]]:
+; GFX1250-NEXT: ret void
+;
+; GFX1200-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
+; GFX1200-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
+; GFX1200-NEXT: [[ENTRY:.*]]:
+; GFX1200-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1200: [[FOR_BODY]]:
+; GFX1200-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1200-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1200-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1200-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 20
+; GFX1200-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1200-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1200-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1200-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1200-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1200-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1200-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1200-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1200: [[FOR_END]]:
+; GFX1200-NEXT: ret void
;
; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
-; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1100-NEXT: [[ENTRY:.*]]:
; GFX1100-NEXT: br label %[[FOR_BODY:.*]]
; GFX1100: [[FOR_BODY]]:
@@ -70,36 +90,56 @@ for.end:
}
define amdgpu_kernel void @prefetch_two_streams_160B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
-; GFX12-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
-; GFX12-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
-; GFX12-NEXT: [[ENTRY:.*]]:
-; GFX12-NEXT: br label %[[FOR_BODY:.*]]
-; GFX12: [[FOR_BODY]]:
-; GFX12-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
-; GFX12-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
-; GFX12-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 188
-; GFX12-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
-; GFX12-NEXT: [[TMP2:%.*]] = shl i64 [[IV]], 2
-; GFX12-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 28
-; GFX12-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
-; GFX12-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
-; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
-; GFX12-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
-; GFX12-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 40
-; GFX12-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
-; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
-; GFX12-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
-; GFX12-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
-; GFX12-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
-; GFX12-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
-; GFX12-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; GFX12-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; GFX12-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
-; GFX12: [[FOR_END]]:
-; GFX12-NEXT: ret void
+; GFX1250-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
+; GFX1250-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
+; GFX1250-NEXT: [[ENTRY:.*]]:
+; GFX1250-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1250: [[FOR_BODY]]:
+; GFX1250-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1250-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX1250-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 188
+; GFX1250-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
+; GFX1250-NEXT: [[TMP2:%.*]] = shl i64 [[IV]], 2
+; GFX1250-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 28
+; GFX1250-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
+; GFX1250-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1250-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
+; GFX1250-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1250-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 40
+; GFX1250-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1250-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
+; GFX1250-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1250-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1250-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1250-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1250-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1250-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1250-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1250: [[FOR_END]]:
+; GFX1250-NEXT: ret void
+;
+; GFX1200-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
+; GFX1200-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
+; GFX1200-NEXT: [[ENTRY:.*]]:
+; GFX1200-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1200: [[FOR_BODY]]:
+; GFX1200-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1200-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1200-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1200-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 40
+; GFX1200-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1200-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1200-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1200-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1200-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1200-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1200-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1200-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1200: [[FOR_END]]:
+; GFX1200-NEXT: ret void
;
; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_160B(
-; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1100-NEXT: [[ENTRY:.*]]:
; GFX1100-NEXT: br label %[[FOR_BODY:.*]]
; GFX1100: [[FOR_BODY]]:
@@ -140,36 +180,56 @@ for.end:
}
define amdgpu_kernel void @prefetch_two_streams_320B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
-; GFX12-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
-; GFX12-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
-; GFX12-NEXT: [[ENTRY:.*]]:
-; GFX12-NEXT: br label %[[FOR_BODY:.*]]
-; GFX12: [[FOR_BODY]]:
-; GFX12-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
-; GFX12-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
-; GFX12-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 348
-; GFX12-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
-; GFX12-NEXT: [[TMP2:%.*]] = shl i64 [[IV]], 2
-; GFX12-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 28
-; GFX12-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
-; GFX12-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
-; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
-; GFX12-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
-; GFX12-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 80
-; GFX12-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
-; GFX12-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
-; GFX12-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
-; GFX12-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
-; GFX12-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
-; GFX12-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
-; GFX12-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; GFX12-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; GFX12-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
-; GFX12: [[FOR_END]]:
-; GFX12-NEXT: ret void
+; GFX1250-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
+; GFX1250-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
+; GFX1250-NEXT: [[ENTRY:.*]]:
+; GFX1250-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1250: [[FOR_BODY]]:
+; GFX1250-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1250-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX1250-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 348
+; GFX1250-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
+; GFX1250-NEXT: [[TMP2:%.*]] = shl i64 [[IV]], 2
+; GFX1250-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 28
+; GFX1250-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
+; GFX1250-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1250-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
+; GFX1250-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1250-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 80
+; GFX1250-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1250-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
+; GFX1250-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1250-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1250-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1250-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1250-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1250-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1250-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1250: [[FOR_END]]:
+; GFX1250-NEXT: ret void
+;
+; GFX1200-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
+; GFX1200-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
+; GFX1200-NEXT: [[ENTRY:.*]]:
+; GFX1200-NEXT: br label %[[FOR_BODY:.*]]
+; GFX1200: [[FOR_BODY]]:
+; GFX1200-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1200-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1200-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
+; GFX1200-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 80
+; GFX1200-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1200-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
+; GFX1200-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
+; GFX1200-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
+; GFX1200-NEXT: store i32 [[SUM]], ptr addrspace(1) [[SIDX]], align 4
+; GFX1200-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; GFX1200-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; GFX1200-NEXT: br i1 [[EC]], label %[[FOR_END:.*]], label %[[FOR_BODY]]
+; GFX1200: [[FOR_END]]:
+; GFX1200-NEXT: ret void
;
; GFX1100-LABEL: define amdgpu_kernel void @prefetch_two_streams_320B(
-; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; GFX1100-SAME: ptr addrspace(1) captures(none) [[A:%.*]], ptr addrspace(1) readonly captures(none) [[B:%.*]], i64 [[N:%.*]]) {
; GFX1100-NEXT: [[ENTRY:.*]]:
; GFX1100-NEXT: br label %[[FOR_BODY:.*]]
; GFX1100: [[FOR_BODY]]:
@@ -208,6 +268,3 @@ for.body:
for.end:
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1250: {{.*}}
-; GFX1251: {{.*}}
>From 53a9146498d1c12f3bdc5da1cb93b35894ae0b7d Mon Sep 17 00:00:00 2001
From: shore <shorshen at amd.com>
Date: Fri, 17 Jul 2026 18:13:34 +0800
Subject: [PATCH 3/6] fix test
---
.../AMDGPU/vmem-cache-line-size.ll | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
index fda4f77150634..50203eb868023 100644
--- a/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
+++ b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
@@ -34,7 +34,11 @@ define amdgpu_kernel void @prefetch_two_streams_80B(ptr addrspace(1) nocapture %
; GFX1200-NEXT: br label %[[FOR_BODY:.*]]
; GFX1200: [[FOR_BODY]]:
; GFX1200-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1200-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX1200-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 28
+; GFX1200-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
; GFX1200-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1200-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1200-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1200-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 20
; GFX1200-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
@@ -124,10 +128,18 @@ define amdgpu_kernel void @prefetch_two_streams_160B(ptr addrspace(1) nocapture
; GFX1200-NEXT: br label %[[FOR_BODY:.*]]
; GFX1200: [[FOR_BODY]]:
; GFX1200-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1200-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX1200-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 188
+; GFX1200-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
+; GFX1200-NEXT: [[TMP2:%.*]] = shl i64 [[IV]], 2
+; GFX1200-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 28
+; GFX1200-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
; GFX1200-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1200-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1200-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1200-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 40
; GFX1200-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1200-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
; GFX1200-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1200-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1200-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
@@ -214,10 +226,18 @@ define amdgpu_kernel void @prefetch_two_streams_320B(ptr addrspace(1) nocapture
; GFX1200-NEXT: br label %[[FOR_BODY:.*]]
; GFX1200: [[FOR_BODY]]:
; GFX1200-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; GFX1200-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
+; GFX1200-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 348
+; GFX1200-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP1]]
+; GFX1200-NEXT: [[TMP2:%.*]] = shl i64 [[IV]], 2
+; GFX1200-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 28
+; GFX1200-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[B]], i64 [[TMP3]]
; GFX1200-NEXT: [[IDX0:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV]]
+; GFX1200-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP]], i32 0, i32 3, i32 1)
; GFX1200-NEXT: [[V0:%.*]] = load i32, ptr addrspace(1) [[IDX0]], align 4
; GFX1200-NEXT: [[IV_OFF:%.*]] = add i64 [[IV]], 80
; GFX1200-NEXT: [[IDX1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[B]], i64 [[IV_OFF]]
+; GFX1200-NEXT: call void @llvm.prefetch.p1(ptr addrspace(1) [[SCEVGEP1]], i32 0, i32 3, i32 1)
; GFX1200-NEXT: [[V1:%.*]] = load i32, ptr addrspace(1) [[IDX1]], align 4
; GFX1200-NEXT: [[SUM:%.*]] = add i32 [[V0]], [[V1]]
; GFX1200-NEXT: [[SIDX:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[A]], i64 [[IV]]
>From d66e0f288b7038fb7197846335b34ca9eaa7cba7 Mon Sep 17 00:00:00 2001
From: shore <shorshen at amd.com>
Date: Mon, 20 Jul 2026 10:00:49 +0800
Subject: [PATCH 4/6] fix comments
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 12 ++++++------
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 6 +++++-
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index fedb95231acbd..ffde380e99154 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -414,7 +414,7 @@ class SubtargetFeatureDataCacheLineSize <int Value> : SubtargetFeature <
"Data (VMEM) cache line size in bytes."
>;
-def FeatureCanPrefetchData128 : SubtargetFeatureDataCacheLineSize<128>;
+def FeatureDataCacheLineSize128 : SubtargetFeatureDataCacheLineSize<128>;
defm GCN3Encoding : AMDGPUSubtargetFeature<"gcn3-encoding",
"Encoding format for VI",
@@ -2172,7 +2172,7 @@ def FeatureISAVersion12 : FeatureSet<
FeatureRealTrue16Insts,
FeatureMTBUFInsts,
FeatureFormattedMUBUFInsts,
- FeatureCanPrefetchData128
+ FeatureDataCacheLineSize128
]>;
def FeatureISAVersion12_50_Common : FeatureSet<
@@ -2279,7 +2279,7 @@ def FeatureISAVersion12_50 : FeatureSet<
FeatureSWMMACGfx1250Insts,
FeatureTransCoexecutionHazard,
FeatureWMMACoexecutionHazards,
- FeatureCanPrefetchData128,
+ FeatureDataCacheLineSize128,
FeatureRequiresInitialUnclausedVmem,
])>;
@@ -2308,13 +2308,13 @@ def FeatureISAVersion12_51 : FeatureSet<
FeatureUseAddPC64Inst,
FeatureTransCoexecutionHazard,
FeatureWMMACoexecutionHazards,
- FeatureCanPrefetchData128,
+ FeatureDataCacheLineSize128,
FeatureRequiresInitialUnclausedVmem,
])>;
def FeatureISAVersion12_Generic: FeatureSet<
!listconcat(FeatureISAVersion12.Features,
- [FeatureCanPrefetchData128,
+ [FeatureDataCacheLineSize128,
FeatureRequiresCOV6])>;
def FeatureISAVersion12_5_Generic: FeatureSet<
@@ -2326,7 +2326,7 @@ def FeatureISAVersion12_5_Generic: FeatureSet<
FeatureGFX125xLowestRateWMMA,
FeatureTransCoexecutionHazard,
FeatureWMMACoexecutionHazards,
- FeatureCanPrefetchData128,
+ FeatureDataCacheLineSize128,
FeatureRequiresInitialUnclausedVmem,
])>;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index b1169a7449d77..5fb368dfa567b 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -202,7 +202,11 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
/// Data (VMEM) cache line size in bytes (128 for gfx12), has no use before
/// GFX12.
- unsigned getDataCacheLineSize() const { return DataCacheLineSize; }
+ unsigned getDataCacheLineSize() const {
+ if (hasVmemPrefInsts() || hasSmemPrefetchInsts())
+ return DataCacheLineSize;
+ return 0;
+ }
unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {
return (ForBufferRSrc || !hasFlatScratchEnabled()) ? MaxPrivateElementSize
>From 36cc4510b41725d12a77c2ded850c072f405a84e Mon Sep 17 00:00:00 2001
From: Shoreshen <372660931 at qq.com>
Date: Thu, 23 Jul 2026 09:24:46 +0800
Subject: [PATCH 5/6] Update
llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
---
.../LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
index 50203eb868023..8cca57c170eee 100644
--- a/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
+++ b/llvm/test/Transforms/LoopDataPrefetch/AMDGPU/vmem-cache-line-size.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -mtriple=amdgpu12.50 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1250
-; RUN: opt -mtriple=amdgpu12.00 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1200
-; RUN: opt -mtriple=amdgpu11.00 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1100
+; RUN: opt -mtriple=amdgpu12.50 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1250
+; RUN: opt -mtriple=amdgpu12.00 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1200
+; RUN: opt -mtriple=amdgpu11.00 -passes=loop-data-prefetch -S < %s | FileCheck %s --check-prefix=GFX1100
define amdgpu_kernel void @prefetch_two_streams_80B(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture readonly %b, i64 %n) {
; GFX1250-LABEL: define amdgpu_kernel void @prefetch_two_streams_80B(
>From e922aa40837e327e26330ad89a4027cf8f7a9623 Mon Sep 17 00:00:00 2001
From: shore <shorshen at amd.com>
Date: Thu, 23 Jul 2026 09:38:26 +0800
Subject: [PATCH 6/6] fix comments
---
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 4 +++-
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 6 +-----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 64e7d0c480374..fa9e736234762 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -1754,7 +1754,9 @@ GCNTTIImpl::getTypeLegalizationCost(Type *Ty) const {
}
unsigned GCNTTIImpl::getCacheLineSize() const {
- return ST->getDataCacheLineSize();
+ if (ST->hasVmemPrefInsts() || ST->hasSmemPrefetchInsts())
+ return ST->getDataCacheLineSize();
+ return 0;
}
unsigned GCNTTIImpl::getPrefetchDistance() const {
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 37713a69a7534..62675503efee1 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -204,11 +204,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
/// Data (VMEM) cache line size in bytes (128 for gfx12), has no use before
/// GFX12.
- unsigned getDataCacheLineSize() const {
- if (hasVmemPrefInsts() || hasSmemPrefetchInsts())
- return DataCacheLineSize;
- return 0;
- }
+ unsigned getDataCacheLineSize() const { return DataCacheLineSize; }
unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {
return (ForBufferRSrc || !hasFlatScratchEnabled()) ? MaxPrivateElementSize
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