[llvm] [AMDGPU] Fix instruction size of LDS-DMA buffer loads (PR #211302)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Michael Halkenhäuser (mhalk)

<details>
<summary>Changes</summary>

Mark i1imm_0 as OPERAND_IMMEDIATE type, so its packed 1-bit value is not mistaken for a trailing literal.
Applies to the swz/IsAsync fields of buffer and FLAT LDS-DMA instructions.

Add lit test, checking encoded size is 8 bytes (was: 12).

AI-assisted.

---
Full diff: https://github.com/llvm/llvm-project/pull/211302.diff


2 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructions.td (+4-1) 
- (added) llvm/test/CodeGen/AMDGPU/buffer-load-lds-size.ll (+20) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 2387afe1cd362..ae644490228a6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -94,7 +94,10 @@ def FMA : Predicate<"Subtarget->hasFMA()">;
 
 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
 
-def i1imm_0 : OperandWithDefaultOps<i1, (ops (i1 0))>;
+// Packed 1-bit field; mark immediate so it is not counted as a literal.
+def i1imm_0 : OperandWithDefaultOps<i1, (ops (i1 0))> {
+  let OperandType = "OPERAND_IMMEDIATE";
+}
 
 class CustomOperandClass<string name, bit optional, string predicateMethod,
                          string parserMethod, string defaultMethod>
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-load-lds-size.ll b/llvm/test/CodeGen/AMDGPU/buffer-load-lds-size.ll
new file mode 100644
index 0000000000000..b6a4cc2d5d543
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/buffer-load-lds-size.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=amdgpu9.00 -filetype=obj < %s | llvm-objdump --triple=amdgpu9.00 --disassemble - | FileCheck %s
+
+; Make sure the computed instruction size for LDS-DMA buffer loads is correct
+; and passes the instruction size verifier. The offset/cpol/swz fields are
+; packed into the instruction word and must not be counted as a trailing
+; literal, so each load is 8 bytes (two 32-bit words).
+
+declare void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8), ptr addrspace(3) nocapture, i32, i32, i32, i32, i32)
+
+; CHECK: buffer_load_dword v0, s[0:3], 0 offen lds{{.*}}E0511000 80000000
+define amdgpu_ps void @buffer_load_lds_dword_offen(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
+  call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 2048, i32 0, i32 0, i32 0)
+  ret void
+}
+
+; CHECK: buffer_load_dword off, s[0:3], 0 lds{{.*}}E0510000 80000000
+define amdgpu_ps void @buffer_load_lds_dword_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
+  call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 0, i32 0, i32 0)
+  ret void
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/211302